JPS60193335A - Production of semiconductor device - Google Patents

Production of semiconductor device

Info

Publication number
JPS60193335A
JPS60193335A JP4980384A JP4980384A JPS60193335A JP S60193335 A JPS60193335 A JP S60193335A JP 4980384 A JP4980384 A JP 4980384A JP 4980384 A JP4980384 A JP 4980384A JP S60193335 A JPS60193335 A JP S60193335A
Authority
JP
Japan
Prior art keywords
film
aperture
resist
insulating film
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4980384A
Other languages
Japanese (ja)
Inventor
Masamitsu Yamauchi
山内 正充
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP4980384A priority Critical patent/JPS60193335A/en
Publication of JPS60193335A publication Critical patent/JPS60193335A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

Abstract

PURPOSE:To obtain an electrode wiring free of interruption in steps, by utilizing the features a P type photoresist for forming films of Si3N4, SiO2 and the like in a stepped shape with the use of resist once formed as a mask and for subsequently providing an electrode metal in self-alignment again with the use of this resist. CONSTITUTION:An SiO2 film 2 and an Si3N4 film 3 are layered and adhered on a semiconductor substrate 1, which is wholly covered with a P type photoresist film 6. The film 6 is first formed with an aperture (a). Anisotropic etching is performed with the use of the residual film 6 as a mask to remove the film 3 exposed in the aperture and then the film 2. The side walls of the aperture (a) thus produced are trimmed to be vertical. After that, the substrate 1 is dipped in a resist developing solution to overdevelop the resist film 6, whereby the resist film 6 is retreated to be a film 6'. The exposed end of the film 3 is removed by dry etching to form a stepped shape in the ends of the films 3 and 2 within the aperture (a). An electrode metal is then vapor deposited with the sue of the film 6' as a mask so as to obtain an electrode having a stepped end within the aperture (a).

Description

【発明の詳細な説明】 (技術分野) 本発明は半導体基板上に形成された工、チングレートの
異なる2種類の絶縁膜に開孔部を設けて電極金属を形成
させる半導体装置の製造方法に係る。
Detailed Description of the Invention (Technical Field) The present invention relates to a method for manufacturing a semiconductor device in which an electrode metal is formed by forming an opening in two types of insulating films having different cutting rates formed on a semiconductor substrate. It depends.

(従来技術) 近年半導体装置の信頼度向上のための手段としてシリコ
ン窒化膜が半導体装置の表面保護膜として多く用いられ
るようになった。
(Prior Art) In recent years, silicon nitride films have come to be widely used as surface protection films of semiconductor devices as a means to improve the reliability of semiconductor devices.

しかしシリコン窒化膜はシリコン酸化膜に比較して工、
チングレートが非常に遅いため、半導体装置の製造プロ
セス上いくつかの難点があった。
However, silicon nitride film is more difficult to process than silicon oxide film.
The extremely slow rate of conversion caused several difficulties in the manufacturing process of semiconductor devices.

例えば第1図に示す様VC半導体基板1上にシリコン酸
化膜2及びシリコ/窒化膜3t−それぞれ2000 A
づつ気相成長法により形成させ、この表面に7オトレジ
スト4を形成させて開孔部aを設ける。次にフォトレジ
スト4をマスクにしてシリコン窒化膜3、シリコン酸化
膜2に例えば1:6バツフアード弗酸を用いてエツチン
グを施すと、シリコン酸化llI2の方がシリコン窒化
膜3よりエツチングレートが非常に速いために第2図に
示す様なオーバーハングの部分が発生する。従ってこの
状態で電棒金属5を形成すると第3図に示す様にオーバ
ーハング部分で電極金属の段切れ7が発生する。
For example, as shown in FIG. 1, a silicon oxide film 2 and a silicon/nitride film 3t each have a thickness of 2000 A on a VC semiconductor substrate 1.
A photoresist 4 is formed on the surface of the photoresist 4 to form an opening a. Next, using the photoresist 4 as a mask, the silicon nitride film 3 and the silicon oxide film 2 are etched using, for example, 1:6 buffered hydrofluoric acid. Because of the high speed, an overhang portion as shown in FIG. 2 occurs. Therefore, if the electric rod metal 5 is formed in this state, a step break 7 will occur in the electrode metal at the overhang portion, as shown in FIG.

そこでこの問題を解決するために前記絶縁膜の開孔を二
度に分離し第1回目のエツチングでシリコン窒化膜3の
みを所望の開孔面積よシ広く、例えばドライエ、チング
法を用いてエツチング除去し、鶴2回目のエツチングで
第4図に示すフォトレジスト4′をマスクにしてシリコ
ン酸化膜2のみを工、?/グ除去し最後に電極金[5を
形成する方法がある。この状態を第5図に示すがこの方
法ではシリコン窒化膜3とシリコン酸化膜2の端部が階
段状に形成されているので、前述の電極金属5の段切れ
7の発生は無い。
Therefore, in order to solve this problem, the opening in the insulating film is separated into two parts, and in the first etching, only the silicon nitride film 3 is etched to a larger area than the desired opening, using a dry etching method, for example. Then, in the second etching process, only the silicon oxide film 2 is etched using the photoresist 4' shown in FIG. 4 as a mask. There is a method of removing the / and finally forming the electrode gold [5]. This state is shown in FIG. 5. In this method, the ends of the silicon nitride film 3 and the silicon oxide film 2 are formed in a step-like manner, so that the step break 7 of the electrode metal 5 described above does not occur.

しかしながら、この方法を用いた場合社、フォトエツチ
ング工程を絶縁膜の開孔に2回、電極形成に1回の合計
3回も行なわけれはならない事、またそれぞれのフォト
エツチング工程における相対位置合わせ′lII度を考
慮すると、この方法はマイクロ波トランジスタの様な微
小パターンの場合には採用できない欠点があった。
However, when using this method, the photoetching process must not be performed more than three times, twice for opening holes in the insulating film and once for electrode formation, and the relative positioning in each photoetching process must be Considering the degree of III, this method has the disadvantage that it cannot be used in the case of minute patterns such as microwave transistors.

(発明の目的) 本発明の目的は、かがる欠点を解消せしめるために、ポ
ジ型フォトレジストの特徴を利用して、1度形成したフ
ォトレジストをマスクにしてシリコン窒化膜、シリコン
酸化膜を階段状に形成し、且つこのフォトレジストを用
いて電極金属もセルファラインで形成する事により段切
れの発生する事の無い、相対位置合わせ精度の高い半導
体装置の製造方法を提供するものである。
(Objective of the Invention) An object of the present invention is to utilize the characteristics of a positive photoresist to form a silicon nitride film and a silicon oxide film using the once-formed photoresist as a mask, in order to eliminate such defects. The present invention provides a method for manufacturing a semiconductor device with high relative positioning accuracy, which does not cause step breakage by forming the semiconductor device in a stepwise manner and also forming the electrode metal in a self-aligned manner using the photoresist.

(実施例) 次に本発明を好ましい実施例について図面を用いて、よ
り詳細に説明する。
(Embodiments) Next, preferred embodiments of the present invention will be described in more detail with reference to the drawings.

第6図は、半導体基板l上のシリコン酸化膜2上にシリ
コン窒化膜3を有し、この表面にポジ型フォトレジスト
6を形成し、開孔部aを設けた後。
FIG. 6 shows a silicon nitride film 3 on a silicon oxide film 2 on a semiconductor substrate l, after a positive photoresist 6 is formed on this surface and an opening a is provided.

平行平板型ドライエ、チング装置を用いてシリコン窒化
[3シリコン酸化膜2にも順次開孔部aを設けた状態を
示す。平行平板型ドライエ、チング装置による工、チン
グ社異方性エツチングであるので、横方向へのエツチン
グは進行せず垂直に工、チングされる。
A state in which openings a are sequentially formed in the silicon nitride [3 silicon oxide film 2] using a parallel plate type dryer and etching device is shown. Since this is anisotropic etching using a parallel plate type dryer and etching device, etching is performed vertically without proceeding in the lateral direction.

次に、このように処理された半導体基板を再度ポジ型フ
ォトレジスト現像液中に浸漬しオーバー現像を施すと、
第7図に示す様に前記ポジ型フォトレジスト6の端部が
後退しパターン6′となりシリコン窒化膜3の端部が露
呈される。更に該半導体基板にドライエ、チングを施す
と第8図に示す如く前記露呈されたシリコン窒化膜3の
端部が除去されシリコン窒化膜3とシリコン酸化膜2は
階段状に形成される。次にとの半導体基板表面に蒸着法
若しくはスバ、り法によシミ他金属(例えばTi −P
L −AU )を被着せしめリフトアクエイ法によって
電極金属5を形成した状態を第9図に示す。
Next, the semiconductor substrate treated in this way is immersed again in a positive photoresist developer and over-developed.
As shown in FIG. 7, the edge of the positive photoresist 6 is recessed to form a pattern 6' and the edge of the silicon nitride film 3 is exposed. Further, when the semiconductor substrate is subjected to dry etching and etching, the exposed end portions of the silicon nitride film 3 are removed, and the silicon nitride film 3 and the silicon oxide film 2 are formed in a stepped shape, as shown in FIG. Next, the surface of the semiconductor substrate is stained with other metals (e.g. Ti-P
FIG. 9 shows a state in which electrode metal 5 is formed by depositing L-AU) and using the lift-aqua method.

第9図よシ明らかな様に実施例による半導体装置の製造
方法を用いるとオーバーハング部が無いので電極金属の
段切れが発生する事は無いし、またシリコン醸化膜2と
シリコン窒化膜3の開孔部と電極金属5の相対位置合わ
せがセルファラインになっているので、位置関係がずれ
る事は皆無である。更にアルファラインであるためにこ
の方法は、開孔部が数μの微細パターンを有するマイク
ロ波トランジスタやマイクロ波ICの製造プロセスに於
て特にその効果を発揮するものである。
As is clear from FIG. 9, when the method for manufacturing a semiconductor device according to the embodiment is used, there is no overhang part, so there is no breakage of the electrode metal, and the silicon nitride film 2 and the silicon nitride film 3 Since the relative positioning of the opening and the electrode metal 5 is self-aligned, there is no possibility that the positional relationship will shift. Furthermore, since it is an alpha line, this method is particularly effective in the manufacturing process of microwave transistors and microwave ICs having fine patterns with openings of several microns.

尚、本実施例に於いて絶縁膜としてシリコン酸化膜とシ
リコン窒化膜を用いて説明したが、これは特に限定され
るものでなく、エツチングレートの異なる絶縁膜であれ
ば、他のいかなる絶縁膜であってもさしつかえない。ま
た′@電極金属Ti−pt −Atr を例に示したが
その種類は全く限定されない。
Although this embodiment has been described using a silicon oxide film and a silicon nitride film as the insulating films, this is not particularly limited, and any other insulating film with different etching rates may be used. It's okay even if it is. Further, although '@electrode metal Ti-pt-Atr is shown as an example, its type is not limited at all.

【図面の簡単な説明】[Brief explanation of drawings]

第1図乃至第5図は従来の半導体装置の製造方法を説明
するための断面図である。第6図乃菌第9図は本発明の
一実施例による半導体装置の製造方法を説明するための
断面図である。 1・・・・・・半導体基板、2・・・・・・シリコン酸
化膜、3・・・・・・シリコン”A(tJs 4,4’
・・・・・・フォトレジス)、5. 5’・・・・・・
電極金属、6. 6’・・・・・・ポジ型フォトレジス
ト。 第1区 第2図 第4区 8b図 第7図 第6〆
1 to 5 are cross-sectional views for explaining a conventional method of manufacturing a semiconductor device. 6 to 9 are cross-sectional views for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. 1... Semiconductor substrate, 2... Silicon oxide film, 3... Silicon "A (tJs 4,4'
...Photoregis), 5. 5'・・・・・・
Electrode metal, 6. 6'・・・Positive photoresist. Section 1, Figure 2, Section 4, Figure 8b, Figure 7, Figure 6.

Claims (1)

【特許請求の範囲】[Claims] 半導体基板上に第1の絶縁膜を有し、該第1の絶縁膜上
にこの第1の絶縁膜よりも工、チングレートの遅い第2
の絶縁膜を有する半導体基板に開孔部を設けて電極金属
を形成するに際し、前記第2の絶縁膜上をポジ型フォト
レジストで被覆しての絶縁膜を順次エツチング除去する
工程と、更に該半導体基板に現像処理を施して、前記第
2の絶縁膜の端部を露呈させる工程と、然る後に再度エ
ツチング処理を施して前記第2の絶縁膜の端部をエツチ
ング除去する工程と、該半導体基板上に電極金属を被着
し前記フォトレジストを用いてリフトアウェイ法によっ
て電極を形成する工程とを含む事を特徴とする半導体装
置の製造方法。
A first insulating film is provided on a semiconductor substrate, and a second insulating film having a lower processing rate than the first insulating film is disposed on the first insulating film.
When forming an electrode metal by forming an opening in a semiconductor substrate having an insulating film, a step of covering the second insulating film with a positive photoresist and sequentially etching away the insulating film; a step of performing a development process on the semiconductor substrate to expose an end portion of the second insulating film; a step of subsequently performing an etching process again to remove the end portion of the second insulating film; 1. A method of manufacturing a semiconductor device, comprising the steps of depositing an electrode metal on a semiconductor substrate and forming an electrode by a lift-away method using the photoresist.
JP4980384A 1984-03-15 1984-03-15 Production of semiconductor device Pending JPS60193335A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4980384A JPS60193335A (en) 1984-03-15 1984-03-15 Production of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4980384A JPS60193335A (en) 1984-03-15 1984-03-15 Production of semiconductor device

Publications (1)

Publication Number Publication Date
JPS60193335A true JPS60193335A (en) 1985-10-01

Family

ID=12841299

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4980384A Pending JPS60193335A (en) 1984-03-15 1984-03-15 Production of semiconductor device

Country Status (1)

Country Link
JP (1) JPS60193335A (en)

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