JPS60192357A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPS60192357A JPS60192357A JP59048711A JP4871184A JPS60192357A JP S60192357 A JPS60192357 A JP S60192357A JP 59048711 A JP59048711 A JP 59048711A JP 4871184 A JP4871184 A JP 4871184A JP S60192357 A JPS60192357 A JP S60192357A
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- power supply
- gate
- surge voltage
- channel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 18
- 239000003990 capacitor Substances 0.000 claims abstract description 8
- 230000003071 parasitic effect Effects 0.000 description 13
- 230000015556 catabolic process Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 235000006732 Torreya nucifera Nutrition 0.000 description 1
- 244000111306 Torreya nucifera Species 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（技術分野）
本発明は半導体集積回路に係り、特に相補をＭＯＳトラ
ンジスタ（以下ＣＭＯ８Ｔｒと記す）Ｉ１１成を有する
半導体集積回路に使用される電源に対するサージ電圧に
よるラッチアップ現象防止回路に関する。Detailed Description of the Invention (Technical Field) The present invention relates to a semiconductor integrated circuit, and in particular to a latch-up phenomenon caused by a surge voltage to a power supply used in a semiconductor integrated circuit having a complementary MOS transistor (hereinafter referred to as CMO8Tr) I11 configuration. Regarding the prevention circuit.
（従来技術）
第１図は従来のＣＭＯ８Ｔｒ構成を有する半導体集積回
路（以下ＣＭＯ８乗積回路と記す）の断面図である。同
図において５本ＣＭＯ８業積回路は、Ｎ−型の半導体基
板１１の主面に、Ｐウェル領域１２と、Ｐ 駿半導体領
賊からなるチャンネルストッパ１９．２０とＮｉｌ半導
体領域からなるチャンネルストッパ１７．１８とが形成
され、さらに前記Ｐウェル領ｂｊｔｔ２内にはＮＵ半導
体領賊からなるンース、ドレイン領ＦＪＡ１５．１６が
形成され、Ｐウェル領１１１２の境界域表面にはＰ５ｉ
半導体領域からなるチャンネルストッパ１３゜１４が形
成されている。さて、釆集積回路は、その構造上寄生Ｎ
ＰＮ）ランラスタ２３．寄生ＰＮＰトランジスタ２１が
存在し、これら寄生トランジスタ２３．２１は、ＰＮＰ
Ｎａのサイリスタを形成している。第２図は、これらの
寄生ＮＰＮ。(Prior Art) FIG. 1 is a cross-sectional view of a semiconductor integrated circuit (hereinafter referred to as a CMO8 multiplication circuit) having a conventional CMO8Tr configuration. In the same figure, the five CMO8 product circuit has a P well region 12, a channel stopper 19 and 20 made of a P well semiconductor region, and a channel stopper 17 made of a Nil semiconductor region on the main surface of an N-type semiconductor substrate 11. Furthermore, a drain region FJA15.16 made of NU semiconductor regions is formed in the P well region bjtt2, and a P5i region is formed on the surface of the boundary area of the P well region 1112.
Channel stoppers 13 and 14 made of semiconductor regions are formed. Now, the integrated circuit has a parasitic N due to its structure.
PN) Run raster 23. There are parasitic PNP transistors 21, these parasitic transistors 23.21 are PNP
It forms a Na thyristor. Figure 2 shows these parasitic NPNs.
ＰＮＰ ）ランジスタ２３．２１によるサイリスタ等価
回路を示す回路図である。第１のトランジスタ２１’は
、第１図における寄生ＰＮＰ トランジスタ２１であ凱
抵抗２２′は第１図のＮ−型の半導体基板１１と電源端
子２５との間の抵抗である。又第２のトランジスタ２３
′は第１図の寄生ＮＰＮトランジスタ２３であり、抵抗
２４′は第１図のＰ−ウェル１２と接地端子との間の抵
抗である。電源端子２５は第１の電源端子２５′である
。このような第１．第２のトランジスタ２１′。FIG. 3 is a circuit diagram showing a thyristor equivalent circuit using transistors 23 and 21. The first transistor 21' is the parasitic PNP transistor 21 in FIG. 1, and the resistor 22' is a resistor between the N- type semiconductor substrate 11 and the power supply terminal 25 in FIG. Also, the second transistor 23
' is the parasitic NPN transistor 23 of FIG. 1, and resistor 24' is the resistance between the P-well 12 of FIG. 1 and the ground terminal. The power supply terminal 25 is a first power supply terminal 25'. Such a first. Second transistor 21'.
２３′よりなるサイリスタ回路をＭするＣＭＯ８集積回
路において、今電源端子２５′にサージ電圧が加わり、
第１のトランジスタ２１’又は第２のトランジスタ２３
′のコレクタ、エミッタ間がブレークダウンを起こした
場合を想定する。In a CMO8 integrated circuit that has a thyristor circuit M23', a surge voltage is now applied to the power supply terminal 25',
First transistor 21' or second transistor 23
Assume that a breakdown occurs between the collector and emitter of .
まず、電源端子２５′に何らかの原因でサージ電圧が加
わり、第１のトランジスタ２１’のエミッタコレクタ間
がブレークダウンした場合について述べる。この場合、
第１のトランジスタ２１’のコレクタ電流は、抵抗２４
′を通して接地点へと流れる。この抵抗２４′による電
圧降下により、第２のトランジスタ２３′のベース電位
が上昇しトランジスタ２３′は導通状態となる。第２の
トランジスタ２３′が導通状態となると、抵抗２２′へ
電流が流れ、その電圧降下により第１のトランジスタ２
１’のベースがバイアスされ、トランジスタ２１’ も
導通状態となる。この状態になると。First, a case will be described in which a surge voltage is applied to the power supply terminal 25' for some reason and the emitter-collector of the first transistor 21' breaks down. in this case,
The collector current of the first transistor 21' is
′ to the grounding point. Due to the voltage drop across the resistor 24', the base potential of the second transistor 23' increases and the transistor 23' becomes conductive. When the second transistor 23' becomes conductive, current flows to the resistor 22', and the resulting voltage drop causes the first transistor 23' to become conductive.
The base of transistor 1' is biased, and transistor 21' is also rendered conductive. When it comes to this state.
サージ電圧がなくなっても第１．第２のトランジスタ２
１’、２３’は導通状態のままであり、電源端子、接地
端子間に低インピーダンスのバスができるため、大電流
が流れ、ひいてはデバイスの破壊を引き起こすこともあ
る。Even if the surge voltage disappears, the first second transistor 2
1' and 23' remain in a conductive state, creating a low impedance bus between the power supply terminal and the ground terminal, causing a large current to flow, which may even destroy the device.
また、第２のトランジスタ２３′のコレクタ。Also, the collector of the second transistor 23'.
エミッタ間がブレークダウンした場合も同様にして、第
１．第２のトランジスタ２１’、２３’が導通状態とな
る。Similarly, if there is a breakdown between the emitters, the first. The second transistors 21' and 23' become conductive.
以上述べた如く、従来のＣＭＯ８集積回路は。As mentioned above, the conventional CMO8 integrated circuit.
その構造上肩する寄生トランジスタからなるサイリスタ
回路が電源に加わるサージ電圧によりトリガーされ、過
電流破壊する現象（以下ラヅチアヴプと記す）１ｒ、有
するという欠点がある。Due to its structure, a thyristor circuit consisting of parasitic transistors is triggered by a surge voltage applied to a power supply, resulting in an overcurrent breakdown phenomenon (hereinafter referred to as "radiation") 1r.
（発明の目的）
本発明の目的は、このような欠点が改善δれ、電源にサ
ージ電圧が加わっても容易に７−ｙチアヅプが発生しな
い半導体集積回路を提供することにある。(Object of the Invention) An object of the present invention is to provide a semiconductor integrated circuit in which the above drawbacks are improved and 7-y chiadup does not easily occur even when a surge voltage is applied to the power supply.
（発明の構成）
本発明の半導体集積回路の構成は、ドレインが電源に接
続されかつソースが接地点に接続されたＮチャンネル・
エンハンスメント形ＭＯ１ｌランジスタト、このＮチャ
ンネル・エンハンスメント形ＭＯ８）ランジスタのゲー
トと前記接地点との間に介在した抵抗と、前記ゲートと
前記電源との間に介在したコンデンサとを有する回路を
備えたことｔ−特徴とする。(Structure of the Invention) The structure of the semiconductor integrated circuit of the present invention is an N-channel semiconductor integrated circuit whose drain is connected to a power supply and whose source is connected to a ground point.
an enhancement type MO1l transistor, comprising a circuit having a resistor interposed between the gate of the N-channel enhancement type MO8 transistor and the ground point, and a capacitor interposed between the gate and the power source; -Characteristics.
（実施例） 次に図面を参照しながら本発明の詳細な説明する。(Example) Next, the present invention will be described in detail with reference to the drawings.
第３図は本発明の実施例の半導体集積回路を示す回路図
である。同図において、本半導体集積回路は、第２図と
同等な従来回路３４’ｉｉする他に。FIG. 3 is a circuit diagram showing a semiconductor integrated circuit according to an embodiment of the present invention. In the figure, the present semiconductor integrated circuit includes a conventional circuit 34'ii which is equivalent to that in FIG.
電源端子２５′と接地点との間に、ドレインが電５−
源に接続されかつソースが接地され、ゲートが抵抗３３
を介して接地されたＮチャンネルエンハンスメントＩｊ
ｊ１ＭＯ８）ランラスタ３１Ｌ−有し、さらにＮチャン
ネルエンハンスメント！ＩＩＩＭＯ８）ランジスタ３１
のゲートと電源端子２５′との間に容量３２ｔ−有する
ことである。Between the power supply terminal 25' and the ground point, the drain is connected to the power source, the source is grounded, and the gate is connected to the resistor 33.
N-channel enhancement Ij grounded through
j1MO8) Run raster 31L-equipped with N channel enhancement! IIIMO8) Transistor 31
A capacitance of 32t- is provided between the gate of the power supply terminal 25' and the power supply terminal 25'.
次に電源端子２５′にサージ電圧が加わった場合の本回
路の動作について述べる。今、電源端子２５′にサージ
電圧が加わるとＮチャンネルＭＯＳトランジスタ３１の
ゲート電圧は、コンデンサ３２、抵抗３３より構成され
る微分回路により上昇し、チャンネルを形成するのに十
分な値となると、ＮチャンネルＭＯ８）ランジスタ３１
はオン状態となり、電源端子２５′と接地端子との間に
低インピーダンスのパスができ、その結果サージ電圧は
急激に低下する。サージ電圧が低くなると。Next, the operation of this circuit when a surge voltage is applied to the power supply terminal 25' will be described. Now, when a surge voltage is applied to the power supply terminal 25', the gate voltage of the N-channel MOS transistor 31 is increased by a differentiating circuit composed of a capacitor 32 and a resistor 33, and when it reaches a value sufficient to form a channel, N Channel MO8) transistor 31
turns on, creating a low impedance path between the power supply terminal 25' and the ground terminal, resulting in a sudden drop in surge voltage. When the surge voltage becomes low.
ＮチャンネルＭＯ８）ランジスタ３１のゲート電圧も低
下し、トランジスタ３１はオフ状態となる。N-channel MO8) The gate voltage of the transistor 31 also decreases, and the transistor 31 is turned off.
ここで、ＮチャンネルＭＯＳトランジスタ３１がオン状
態となるのに十分なサージ電圧は、サイリ６−
スタを構成する第１．第２の寄生トランジスタ２１’、
２３’のコレクタエミ・ツタ間がブレークダウンする電
圧に比較し十分低い値であるため。Here, a surge voltage sufficient to turn on the N-channel MOS transistor 31 is applied to the first . second parasitic transistor 21',
This is because the voltage is sufficiently low compared to the voltage that causes breakdown between the collector emitter and ivy of 23'.
電源に加わったサージ電圧は第１．第２の寄生トランジ
スタ２１’、２３’のコレクタエミッタ間をブレークダ
ウンさせることができる電圧に達する前に、トランジス
タ３１により低下させられる。The surge voltage applied to the power supply is the first. It is lowered by the transistor 31 before reaching a voltage that can cause a breakdown between the collector and emitter of the second parasitic transistor 21', 23'.
従って、従来回路のように電源にサージ電圧が加わって
もラッチアップが発生することはない。Therefore, unlike conventional circuits, latch-up does not occur even if a surge voltage is applied to the power supply.
サージ電圧により上昇したトランジスタ３１のゲート電
圧は、コンデンサ３２にチャージされた電荷が抵抗３３
を通じてディスチャージされるのにつれて低下する。従
って、サージ電圧によりトランジスタ３１がオン状態に
保たれる時間は、コンデンサ３２及び抵抗３３により決
定される。つまり１時間が長いサージ電圧に対してもト
ランジスタａｌｔ−オン状態に保つには、コンデンサ３
２及び抵抗３３を大きな値とすればよい。The gate voltage of the transistor 31 increased due to the surge voltage, and the electric charge charged in the capacitor 32 is transferred to the resistor 33.
It decreases as it is discharged through. Therefore, the time period during which the transistor 31 is kept on due to the surge voltage is determined by the capacitor 32 and the resistor 33. In other words, in order to keep the transistor alt-on state even in the case of a surge voltage that lasts for an hour, the capacitor 3
2 and the resistor 33 may have large values.
また、サージ電圧が加わらない状態においては、トラン
ジスタ３１のゲートは、抵抗３３ｔ−介して接地されて
いるので、オフ状態にあり、不夾施例で付加された回路
は従来回路の動作には何ら影響を与えない。Furthermore, when no surge voltage is applied, the gate of the transistor 31 is grounded through the resistor 33t, so it is in an off state, and the circuit added in the non-contaminated embodiment has no effect on the operation of the conventional circuit. No impact.
（発明の効果）
以上述べた如く２本発明によれば、電源にサージ電圧が
印加されてもラッチアップが発生しないという効果が得
られる。(Effects of the Invention) As described above, according to the two aspects of the present invention, it is possible to obtain the effect that latch-up does not occur even if a surge voltage is applied to the power supply.
第１図は従来のＣＭＯ８渠積回路を示す断面図。
第２図は第１図のＣＭＯ８乗積回路が有する寄生トラン
ジスタからなるサイリスタ等両回路を示す回路図、第３
図は本発明の一実施例の半導体集積回路を示す回路図で
ある。
同図において、１１・・・・・・へ一基板、１２・・・
・・・Ｐ−ウェル領域、１３．１４・・・・・・ｐＨチ
ャンネルストッパ、＋５．ｔｓ・・・・・・Ｎチャンネ
ルＭＯＳトランジスタのソース、ドレイン領Ｌｔ７．ｔ
ｓ・・・・・・ＮＵチャンネルストッパ、１９．２０・
・・・・・ＰチャンネルＭＯ８）ランジスタのソース、
ドレイン領域、２５．２５’・・・・・・電源端子、２
３・・・・・・寄生ＮＰＮ）ランジスタ、２１・・・・
・・寄生ＰＮＰ ）ランジスタ、２１′・・・・・・第
１のトランジスタ、２３′・・・・・・第２のトランジ
スタ、２２′・・・・・・Ｎ−賊半導体基板領域の抵抗
、２４′・・・・・・Ｐ−ウェル領域のｍ抗、３１・・
・・・・Ｎチャンネルエンハンスメント形ＭＯＳトラン
ジスタ、３２・・・・・・コンデンサ、３３・・・・・
・抵抗％ ３４・・・・・・寄生トランジスタからなる
サイリスタを有する従来回路。
９−
茅１回
）
第２図 Ｊダ
事３習FIG. 1 is a sectional view showing a conventional CMO 8-channel circuit. Figure 2 is a circuit diagram showing both circuits such as thyristors made of parasitic transistors included in the CMO8 multiplication circuit in Figure 1;
The figure is a circuit diagram showing a semiconductor integrated circuit according to an embodiment of the present invention. In the same figure, 11... one board, 12...
... P-well region, 13.14 ... pH channel stopper, +5. ts... Source and drain region Lt7 of N-channel MOS transistor. t
s...NU channel stopper, 19.20.
...P channel MO8) transistor source,
Drain region, 25.25'...Power terminal, 2
3... Parasitic NPN) transistor, 21...
...parasitic PNP) transistor, 21'...first transistor, 23'...second transistor, 22'...resistance in N-parasitic semiconductor substrate region, 24'... m anti of P-well area, 31...
...N-channel enhancement type MOS transistor, 32... Capacitor, 33...
-Resistance% 34...Conventional circuit with a thyristor consisting of a parasitic transistor. 9- Kaya 1 time) Figure 2 J da thing 3 lessons
Claims (1)
れたＮチャンネル・エンハンスメント形ＭＯ８）ランジ
スメと、このＮチャンネル・エンハンスメント形ＭＯ８
）ランジスタのゲートと前記接地点との間に介在した抵
抗と、前記ゲートと前記電源との間に介在したコンデン
サとを有する回路を備えたことを特徴とする半導体集積
回路。An N-channel enhancement type MO8 whose drain is connected to a power supply and a source connected to a ground point, and this N-channel enhancement type MO8
) A semiconductor integrated circuit comprising a circuit including a resistor interposed between the gate of a transistor and the ground point, and a capacitor interposed between the gate and the power supply.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59048711A JPS60192357A (en) | 1984-03-14 | 1984-03-14 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59048711A JPS60192357A (en) | 1984-03-14 | 1984-03-14 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60192357A true JPS60192357A (en) | 1985-09-30 |
Family
ID=12810891
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59048711A Pending JPS60192357A (en) | 1984-03-14 | 1984-03-14 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60192357A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5629545A (en) * | 1991-03-28 | 1997-05-13 | Texas Instruments Incorporated | Electrostatic discharge protection in integrated circuits, systems and methods |
-
1984
- 1984-03-14 JP JP59048711A patent/JPS60192357A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5629545A (en) * | 1991-03-28 | 1997-05-13 | Texas Instruments Incorporated | Electrostatic discharge protection in integrated circuits, systems and methods |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5218222A (en) | Output ESD protection circuit | |
| JP3174636B2 (en) | Electrostatic discharge protection for CMOS integrated circuits | |
| US6399990B1 (en) | Isolated well ESD device | |
| US5760446A (en) | Electrostatic discharge structure of semiconductor device | |
| US4647956A (en) | Back biased CMOS device with means for eliminating latchup | |
| JPH06163824A (en) | Semiconductor integrated circuit | |
| JPH08274267A (en) | Semiconductor device | |
| JPH07193195A (en) | Cmos integrated circuit device | |
| US6894881B1 (en) | ESD protection methods and devices using additional terminal in the diode structures | |
| EP0292327A2 (en) | Electrostatic breakdown protection circuits | |
| US20030116778A1 (en) | Semiconductor apparatus | |
| JP2783191B2 (en) | Semiconductor device protection circuit | |
| US20030230781A1 (en) | Semiconductor device | |
| JPS60192357A (en) | Semiconductor integrated circuit | |
| JPH044755B2 (en) | ||
| JPH11145454A (en) | Semiconductor device, electrostatic protective element, and dielectric breakdown preventing method | |
| JP3100137B2 (en) | Semiconductor integrated device | |
| US4591895A (en) | CMOS circuit with separate power lines to suppress latchup | |
| JPH06244371A (en) | Semiconductor device | |
| JPH05267586A (en) | Output protection network | |
| JPH0532908B2 (en) | ||
| US5432369A (en) | Input/output protection circuit | |
| JPH0766405A (en) | Semiconductor protection device | |
| JPS63301558A (en) | Semiconductor integrated circuit device | |
| JPH0753307Y2 (en) | ESD protection circuit |