JPS6019032B2 - Vector arithmetic processing unit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a vector arithmetic processing device, particularly a vector arithmetic processing device in which elements of a vector are computed in pipeline processing using one instruction. Alternatively, even if an arithmetic exception occurs in multiple stages, for example, only the temporally or logically generated exception information is retained at the end point gE of the one instruction, and the exception information is retained after the end of the one instruction. The present invention relates to a vector arithmetic processing device that checks occurrence.

Conventionally, in data processing devices, when an arithmetic exception occurs, for example, a program is interrupted at that point to extract exception information, which is used to check the cause of the exception.

For this reason, even when elements are computed at high speed under pipeline processing in a vector processing unit, when an operation exception occurs in any one of the multiple steps that make up the pipeline processing. , a method of immediately issuing an interrupt was considered. However, if an arithmetic exception occurs in the first stage of pipeline processing or a stage close to it, other arithmetic exceptions may occur in subsequent steps, and (ii) even if an arithmetic exception occurs in one step, Even if an exception occurs, multiple elements are being processed in parallel at that point, and processing can be restarted from the element where the exception occurred, so it is extremely troublesome to stop the machine and maintain and record information about the internal state. many. Furthermore, since the recovery process corresponding to the above operation exception is performed by other means, there is no need to restart the vector operation process from the point at which the above operation exception occurs. Furthermore, in vector operation execution, the operand data wide, b, ... bn and Co, C, ...
・If cn retains its original data after performing the calculation, then
Since it is possible to analyze in which element the above calculation process occurred during the recovery process, the result is a. ，
It has been found that even if all of an is calculated, there is no problem in the recovery process. In view of the above points, the present invention checks whether or not an arithmetic exception has occurred during the execution of one instruction at the time when one instruction is completed, and preferably the arithmetic exception that has occurred earliest in time or logically. The purpose is to make it possible to extract information.

For this reason, the vector arithmetic processing device of the present invention uses the elements bo, b... belonging to the vector 8 and the vector C.
Elements Co, C, ... belonging to pot vector A, ao, a. . . . and a plurality of steps in the pipeline calculation section, and by one instruction, the element B . . . and/or the element Co,
C. . . . by calculating the above elements ao, a.・・・
In a vector arithmetic processing device that obtains ..., an exception information extraction section is provided corresponding to a step stage in which an operation exception occurs in the pipeline operation section, and the exception information detected by the exception information extraction section is retained. The present invention is characterized in that the presence or absence of the exception information is checked after the timing when the one instruction is completed. This will be explained below with reference to the drawings. FIG. 1 shows an embodiment of the present invention, and FIG. 2 shows an explanatory diagram for explaining its operation.

Codes in the diagram #OVR, #IVR, ..., #7V
R is a vector register that can store, for example, 256 vector elements belonging to one vector, 1-0 is not included, and 1-7 are banks that can be accessed independently, and each bank The contents of the vector registers #OVR to #7VR are stored in a mixed manner, 2-0 and 2-1 are output buses, and 3-0 and 3-1 are read buffers.・Register (REG(R)), 4 is pipeline operation section, 6-0
None, 5-4 are step stages constituting the pipeline operation unit 4, and 6 is a write buffer register (REG).
(W)), 7 is a write bus, 8 is an exception information pipeline, 9-10 to 9-4 are step stages forming the exception information pipeline 8, 10 is an exception information stack, and G is a gate. . In the apparatus shown in FIG. 1, for example, elements L, q, .
... are similarly interleaved and stored in vector register #2VR, and #OVR(i)←(#
IVR(i))+(#2VR(i))(where i=0~2
55) The elements et al. of the result of the operation −'11, a・'. Let us consider a case where ... are interleaved and stored in vector register #OVR as elements belonging to vector A.

In this case, at the timing To shown in FIG.
The element of vector register #IVR from bank 1-1 and the element co of vector register #2VR from bank 1-2 are read out and set in registers 3-0 and 3-1 at timing T.

At timing T, elements 0 of vector register #IVR and banks 1-3 are simultaneously transferred from banks 1-2.
Element c of vector register #2VR is read from. Thereafter, elements bi and bi are read out from each bank in the same manner. and elements b, and c,
At timing T2, the calculation according to step 5-01 is performed, and at timing T3, the calculation according to step 5-- is performed, and so on. At timing L, banks 1-2 are accessed to read elements b8 and c8, but
At this time, a write access is made to bank 1-0', and the contents ao of register 6 are changed to vector register #O.
Set to VR. As described above, the elements ao, a, ... are computed and stored through pipeline processing, but when a computation exception occurs in steps 5-10 to 5-4, the exception information is transferred to the exception information pipe. The corresponding step stage 9-0 of line 8 is set to 9-4.

The contents of each of the steps 9-10 to 9-4 are shifted downward in the diagram one step at a time in synchronization with the processing in the pipeline calculation section 4. In this case, at the timing when the exception information from the step stage 91i is shifted to the step stage 9-(i11), the step stage 51-(i11) of the pipeline calculation unit 4
Step stage 9-(i11) with the same exception information from i+1)
For example, step stage 9
Exception information from -i is given priority and exception information from step 51 (i+1) is ignored. No matter which element is operated on, if it is first set in the step stage 9-4 and then set in the illustrated exception information stack 10 in the next cycle, the illustrated gate G will be turned off thereafter. That is, subsequent exception information is ignored. In this way, the contents of the exception information stack 10 are checked at the stage when all one instruction, for example, the instruction shown in equation '11 above, has been executed.

That is, if the exception information is not stacked, it is assumed that an arithmetic exception did not occur during the execution of the instruction, and if the exception information is stacked, it is assumed that an arithmetic exception has occurred. In this case, the stacked exception information corresponds to an operation exception that occurred in an element with a lower element number, and if it is an element with the same element number, it corresponds to an operation exception that occurred in a higher step in the diagram. It is something. This can be useful within a certain range for estimating the cause of an operation exception. Of course, it goes without saying that the error range for cause estimation may be narrowed by writing the element number in the exception information. In addition, when collecting exception information corresponding to the calculation exception that occurs first, extract the exception information from each step 5-0 None and 5-4 using OR logic, and collect even one of them. It is sufficient to ignore the exception information after the time when the exception information is collected, and the present invention does not exclude such collection. As described above, according to the present invention, it is sufficient to check whether an operation exception has occurred at the end of one instruction.

For this reason, the interrupt control circuit during pipeline processing is greatly simplified, the amount of information stored as exception information can be reduced, the storage capacity can be reduced, and the operation control of each vector instruction can be made uniform. becomes possible.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of the present invention, and FIG. 2 shows an explanatory diagram for explaining its operation. In the figure, #OVR, #IVR, ... are vectors, respectively.
There are no registers, 1-0, and 1-7 are banks, 3-0, respectively.
, 3 and 1 are registers, 4 is a pipeline operation unit, and 5 is a register.
-0 is absent, 5-4 is a step stage, 6 is a register,
8 represents an exception information pipeline, 9 10 does not exist, 9 and 4 each represent a step stage, 10 represents an exception information stack, and G represents a gate. Sai 1 zu spear 2

Claims (1)

[Claims] 1 Elements b_0, b_1... belonging to vector B
and elements c_0, c_1... belonging to vector C, and elements a_0, a_1... belonging to vector A, and a pipeline operation section with multiple steps. ,
The above elements b_0, b_1... and/or elements c_0, c_1... are operated to calculate the above element a.
In the vector arithmetic processing device that obtains _0, a_1..., an exception information extraction section is provided corresponding to a step stage in which an operation exception occurs in the pipeline operation section, and exception information detected by the exception information extraction section is retained. The vector arithmetic processing device is characterized in that the presence or absence of the exception information is checked after the timing when the one instruction is completed.