JPS601871A - High withstand voltage semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device of a field plate structure which can be readily manufactured and be hardly affected by the influence of contamination from the exterior by forming a laminar structure with a plurality of insulating layers and respectively providing field plates on the respective layers. CONSTITUTION:The first insulating layer 12 formed of an SiO2 is formed on the surface of a silicon semiconductor substrate 1, and the first layer electrode 13a and the first field plate 13b are formed by depositing aluminum and photoetching. A polyimide regin is coated, photoetched and heat treated to form the second insulating layer 14. The second layer electrode 15a and the second field plate 15b of alumina are formed, and the third insulating layer 16 of polyimide resin is formed. The third layer electrode 17a and the third field plate 17b of aluminum are formed. Since a plurality of insulating layers and field plates are formed not only on the end of a depletion layer 10 but in the vicinity of the exposed part of the P-N junction 9, shielding effect is performed against contamination from the exterior, thereby stabilizing the withstand characteristics.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to high voltage semiconductor devices such as diodes and transistors having field plates.

In order to increase the withstand voltage of the conventional brainer structure semiconductor device, 5i
A field plate may be provided on an insulating layer such as 02. However, if the field-grate structure is adopted, a new problem arises in that the insulator under the tip of the field plate is destroyed, and it is not possible to obtain a significant effect of improving the withstand voltage. In addition, in order to form the insulating layer thinly to obtain a field plate effect, it is necessary to prevent the influence of external contamination (for example, the influence of residual charge inside the package).
It has the disadvantage that it is easily susceptible to damage and its withstand voltage characteristics become unstable.

In order to solve this problem, a field plate structure as shown in FIG. 1 has been proposed. A silicon semiconductor substrate fi constituting a planar + type PNN diode with a field plate structure shown in FIG.
+ indicates a first semiconductor region (2) of P type (first conductivity type) having a high impurity concentration (low resistance) and a second semiconductor region (2) of N type (second conductivity type) having a low impurity concentration (high resistance). It consists of a semiconductor region (3) and an N-type semiconductor region (4). The first semiconductor region (2) is transformed into the second semiconductor region (2) by impurity diffusion.
3), and is surrounded by the second semiconductor region (3) except for the portion that becomes the surface of the substrate (1). The second semiconductor region (3) surrounds the first semiconductor region (2) with an annular surface portion serving as the surface of the substrate (1).

The N-type semiconductor region (4) has a lower resistivity than the second semiconductor region (3). (5) is the first semiconductor region (
2) a first electrode provided by AI vapor deposition on the surface of (6);
is the second electrode provided in the N-type semiconductor region (4), (7
) has a thin part (7a) and a thick part (7b) 5
An insulating layer consisting of an iOz film, (8) is a field plate provided above the insulating layer (force).

In the device shown in FIG. 1, the vicinity of the part where the PN junction (9) is exposed to the surface is covered with a thin part (7a) of the insulating layer (7), and the tip of the depletion layer expanded by the PN junction (9). is covered with a thick part (7b) of an insulating layer (7).

Therefore, the insulating layer (7) on the tip of the depletion layer (lO)
In other words, since the thick part (7b) of the insulating layer (7) is provided above the tip of the depletion layer (101), the thickness of the insulating layer (7) per unit thickness is The voltage sharing becomes smaller, making it difficult to break down.In addition, since there is an insulating layer (portion (7a) with a weak force) in the part where the PN junction (9) is exposed to the surface, the field plate effect can still be obtained as before. .

However, there is a thin part (7a) etched into the insulating layer (7).
It is difficult to provide a thick portion (7b). Further, the thick portion (7b) of the insulating layer (7) is susceptible to external contamination (although the thin portion (7a) is still susceptible to contamination).

OBJECTS OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor device having a field plate structure that is easy to manufacture and is less susceptible to external contamination.

Structure of the Invention To achieve the above object, the present invention includes: a first semiconductor region of a first conductivity type having a portion that becomes a surface of a semiconductor substrate;
has a second conductivity type opposite to the first conductivity type, and has a second conductivity type opposite to the first conductivity type;
A first semiconductor region having an impurity concentration lower than that of the semiconductor region, and having a portion that becomes the surface of the semiconductor substrate, and surrounding the first semiconductor region except for the surface of the first semiconductor region. the second semiconductor region, the first semiconductor region and the second semiconductor region; a plurality of insulating layers provided, an electrode provided on the first semiconductor region, and a plurality of insulating layers connected to the electrode and extending beyond the exposed portion of the PN junction on the surface of the semiconductor substrate. and a plurality of field plates respectively provided on the plurality of insulating layers, and the tip of the upper field plate is closer to the tip of the lower field plate than the first field plate.
Each of the plurality of field plates is provided so as to be located away from the semiconductor region of the plurality of field plates, and each of the plurality of field plates is provided such that another field plate does not exist below the tip of each of the plurality of field plates. The present invention relates to a high voltage semiconductor device characterized in that the plurality of insulating layers and the plurality of field plates are alternately stacked.

Effects of invention According to the above invention, the following effects can be obtained.

(b) It has a laminated structure with multiple insulating layers, field plates are provided on each of the multiple insulating layers, and the positions of the tips of the multiple field plates are changed, so it is possible to change the thickness of the insulating layer. Equivalent effects can be obtained.

(b) Since it is only necessary to sequentially provide a plurality of insulating layers and a plurality of field plates in a predetermined pattern, a field plate structure with high breakdown voltage can be easily obtained.

(c) The total thickness of multiple insulating layers can be increased in all regions where the depletion layer spreads, and multiple field plates are present near the exposed portion of the PN junction. Therefore, contamination from the outside can be prevented. Therefore, it is possible to provide a semiconductor device with stable breakdown voltage characteristics.

Embodiment Next, a planar diode having a field plate structure according to an embodiment of the present invention will be described with reference to FIGS. 2 to 7.

2 to 7 show a field structure diode in the order of manufacturing steps. When manufacturing this diode, first, the first and second semiconductor regions (
A silicon semiconductor substrate (1) consisting of 21 (31) and an N-type semiconductor region (4) is prepared, and a first insulating layer (121) of 5 iOz having an opening (11) on its surface is provided. ) +21 (31 (41
1 is a region formed in exactly the same manner as in FIG. 1, and the insulating layer α2 is formed so as to cover the entire region in which the depletion layer eventually spreads.

Next, as shown in FIG. 3, a first layer electrode (13a) and a first field layer (13b) are formed by vapor deposition of A1 and photoetching. At this time, the opening old]
An electrode (13a) is provided so as to be connected to the first semiconductor region (2) via the electrode (13a), and a first field plate (
13b) is provided. Also, the first field gray)
(13b) is formed to cover the vicinity of the surface exposed portion of the PN junction (9).

Next, as shown in FIG. 4, polyimide resin, which is a heat-resistant thermosetting insulating resin, is applied, photoetched and heat treated to form the first field play (13b) and the first field play. The second layer covers the insulating layer Oz.
An insulating layer Q41 is formed.

Next, as shown in FIG. 5, by AI vapor deposition and photoetching, the second layer electrode (15a) and the second layer electrode (15a) are formed so as to cover the first layer N pole (13a) and a part of the second insulating layer α4. 2 field play) (15b). The second field plate (15b) is formed to annularly surround the electrode (15a), and its tip extends beyond the tip of the first field plate (13b). That is, the second field plate (15b
) is located further away from the first semiconductor region (2) and the PN junction (9) than the tip of the first field play (13b). As a result, there are first and second insulators # (121a4J) in the lower part near the tip of the second field plate (15b) without intervening the first field plate (13b). Field play) The vicinity of the tip (15b) functions equivalent to a field plate on a thick insulating layer.

Next, as shown in FIG. 6, a third insulating layer Q61 is formed by applying polyimide resin, photoetching, and heat treatment to cover the second field plate (15b) and the second insulating layer Q4). .

Next, as shown in FIG. 7, a third layer electrode (17a) is formed by vapor deposition of AI, photo-etching, and K to cover the second layer electrode (15a), and at the same time, a third insulating layer (17a) is formed to cover the second layer electrode (15a). 16)
third field play) (17
b) form. In addition, a protective metal layer (1
7c) is simultaneously formed to cover the end of the third insulating layer αG and to be connected to the second semiconductor region (3).

This protective metal layer (17c) not only contributes to improving voltage resistance characteristics as an equipotential ring, but also exhibits a shielding effect against contamination from the outside. 3rd field play) (
The tip of 17b) is the second field play) (15b
) extends outward beyond the tip. Therefore, the first and second field plates (13b) (15b) do not exist under the vicinity of the tip of the third field plate (17b), and the first and second field plates (13b) (15b) do not exist under the vicinity of the tip of the third field plate (17b). The second and third insulating layers (Lz (141
(Only I61 exists and is a field play on a thick insulating layer) This is equivalent to forming (17b).

The electrode (6) on the back surface of the substrate 11+ shown in FIG. 7 is formed before, after, or at the same time as the electrodes (13a), (15a), and (17a) on the front surface.

When a reverse voltage is applied to the diode configured as shown in FIG.
A thin first insulating layer (1
Since the first field plate (13b) is provided through the second semiconductor region (3), an inversion region is generated due to the field plate effect in the surface portion of the second semiconductor region (3), and this inverts the first semiconductor region (2). Contributes to improved pressure resistance in some corners and peripheral areas. 3 field plays) (1
Since the tip positions of 3b) (15b) and (17b) change stepwise, the field plate effect also changes stepwise, and the depletion layer α0) also expands corresponding to the field plate effect. Then, at the top of the tip, that is, the periphery of the depletion layer 0, the first, second, and third insulating layers ag <141 (16
Since only the third field plate (17b) exists through the thick insulating layer consisting of ) and three insulating layers u (1
4) The voltage per unit thickness in ue becomes small, and the insulation layer aa a4116! destruction is prevented. That is, the structure of FIG. 7 can provide the same effect as the insulating layer (7) of FIG. 1.

As is clear from the above, according to this embodiment, the following effects can be obtained.

(al First, second and third insulating layers (12) α4J
(161 and first, second and third field plays)
(13b x 15b) (17b) can be obtained by sequentially forming (13b x 15b) (17b) through common processes such as vapor deposition, coating, photoetching, heat treatment, etc., so the structure is different from that shown in Fig. 1. Even if the field plate structure is complicated, the manufacturing difficulty is small and the target field plate structure can be easily obtained.

(b) Not only the tip of the depletion layer a [but also the PN junction (
There are also first, second and third insulating layers αe near the exposed portion of the field plate (13b).
), (15b), and (17b), these exhibit a shielding effect against contamination from the outside, contribute to stabilizing the breakdown voltage characteristics, and provide a highly reliable element.

(C) A protective metal layer (17c) is provided and an insulating layer (161
Since it covers the periphery of the ring, it not only provides an equipotential ring effect but also provides a shielding effect against contamination from the outside.

Modifications The present invention is not limited to the above-described embodiments, but can be modified, for example, as follows.

(4) There is no problem in increasing or decreasing the insulating layer aa (141αQ) and the field plates (13b, 15b, and 17b).

(B) The protective metal layer (t'yc) is attached to the second semiconductor region (
3), and the metal layer (17c) may provide only a shielding effect against contamination.

(Q Second and third insulating layers (14J) (161 may be a 5i02 film formed by vapor phase growth.

(2) A layer corresponding to the metal layer (17c) may also be provided at the periphery of the first and second insulating layers 02α.

(2) It is also applicable to various semiconductor devices such as transistors other than diodes.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing a diode with a conventional field plate structure, and FIG. 2, FIG. 3, FIG. 4, FIG. 5, FIG. 6, and FIG. FIG. 3 is a cross-sectional view showing the diodes in the order of steps. (1)...Silicon semiconductor substrate, (2)...First semiconductor region, (3)...Second semiconductor region, (9)...
...PN junction, α0)...depletion layer, α2...first insulating layer, (13a)...first layer electrode, (13b)
. . . 1st field plate, α leakage 2nd insulation) fJ, (15g) . . . 2nd layer electrode, (15b
)...Second field plate, (161-...Third insulating layer, (17a)...Third layer electrode, (17
b)...Third field plate, (17c)...
・Metal layer. Agent Takano Deputy Figure 1 Figure 2 Figure 4 @ Figure 5

Claims (1)

[Scope of Claims] 11) A first semiconductor region of a first conductivity type having a portion that becomes a surface of a semiconductor substrate; and a first semiconductor region having a second conductivity type opposite to the first conductivity type and
has an impurity concentration lower than that of the semiconductor region, has a portion that becomes the surface of the semiconductor substrate, and is provided in a region 5 surrounding the first semiconductor region except for the surface of the first semiconductor region. a second semiconductor region; and a stacked layer formed and laminated so as to cover at least a portion of a depletion layer exposed on the surface of the semiconductor substrate, which is generated by a PN junction between the first semiconductor region and the second semiconductor region. a plurality of insulating layers provided in the structure; an electrode provided on the first semiconductor region; a plurality of field plates each extending over the plurality of insulating layers, and a tip of the upper field plate is further away from the first semiconductor region than a tip of the lower field plate. Each of the plurality of field plates is provided such that the plurality of field plates are located at the same position, and each of the plurality of field plates is provided such that no other field plate exists below the tip of each of the plurality of field plates, and A high voltage semiconductor device, characterized in that an insulating layer and the plurality of field plates are alternately stacked. (2) The semiconductor device according to claim 1, wherein the plurality of insulating layers include a lowermost insulating layer made of a 5i02 film and an upper insulating layer made of polyimide resin.