JPH0277128A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the deterioration of breakdown strength caused by hydrogen ion generated at the time of forming a silicon nitride film by selectively arranging an amorphous or polycrystalline silicon layer in the upper region of a field insulating film in a coating insulative film, in the manner in which said silicon layer does not come into contact with a silicon nitride passivation film, and is kept in an electrically floating state. CONSTITUTION:A non-doped polycrystalline (amorphous) silicon pattern 17 is buried, so as not to be connected with a field plate 10 sandwiched by a first PSG coating insulative film 14A and a second PSG coating insulative film 14B, and an annular ring 13. A good deal of H<+> contained in an Si3N4 passivation film 11, is apt to diffuse in the second PSG coating insulative film 14B and the first PSG coating insulative film 14A and to reach an exposed region of a field insulating film 6. The greater part of H<+> is captured by the energy level of dangling bond and crystal grain boundary existing in the polycrystalline (amorphous) silicon pattern 17. As the result, H<+> loses potential, and is fixed and vanishes, so that the positive charge of the field insulating film 6 caused by H<+> is avoided.

Description

[Detailed Description of the Invention] [Summary] Regarding a semiconductor device, particularly a high voltage semiconductor device that improves moisture resistance by using a silicon nitride film as a passivation film, hydrogen ions generated during the formation of the silicon nitride film are used. The purpose of the present invention is to provide a protective insulating film structure that prevents breakdown voltage degradation due to In a semiconductor device having a covering insulating film made of
An electrically floating amorphous or polycrystalline silicon layer that does not contact the silicon nitride passivation film is selectively disposed in the upper region of the field insulating film in the covering insulating film. It has the following configuration.

[Industrial application field]

The present invention relates to a semiconductor device, and particularly to a high voltage semiconductor device that uses a silicon nitride film as a passivation film to improve moisture resistance.

In recent years, high-voltage semiconductor devices having a resin mold structure have been produced in large quantities due to improved quality of mold resin, improved moisture resistance due to improved molding technology, and superior price.

However, as the required withstand voltage increases, improvements in the molding resin and molding technology alone are insufficient in terms of reliability in high-humidity environments, and the passivation film on the surface of the semiconductor chip is replaced with silicon nitride, which has excellent moisture resistance. (S
The reliability is improved by forming the iJ, ) film.

[Conventional technology]

FIG. 3 is a plan view (al and a cross-sectional view taken along the line A--A (b)) schematically showing an example of a high-voltage transistor chip with the covering insulating film removed.

In the figure, 1 is an n-type silicon (Si) substrate (collector layer) with an impurity concentration of about 101 a cm -2, 2 is an n-type collector contact layer with an impurity concentration of about 10'8 to 10"am-", and 3 is a Impurity concentration 10"~10"cm-
4 is the impurity concentration B□zo~
5 is an n-type emitter region with an impurity concentration of about 1020 to 10 cm-z, which is provided to prevent leakage current through the end face of the chip.
゛-type channel cut region, 6 is silicon dioxide (SiO
z), 7 is a lower insulating film made of Sing, 8 is a base contact window, 9 is an emitter contact window, 10 is aluminum (AI) or A1
11 is an emitter electrode made of the same material; 12 is a collector bridge made of the same material; 13 is made of the same material. The annular ring that contributes to preventing leakage current through the tip end is shown.

In such high-voltage transistors, the protective film on the surface of the chip has conventionally been made of phosphosilicate glass (PSG) or the like, which has the effect of fixing and blocking contaminant ions such as heavy metals and mechanically protecting the chip surface. It consisted of a covering insulating film of about 1 .mu.m and a silicon nitride (Si, Ni) film of about 0.2 to 0.3 .mu.m thick formed on the upper surface thereof and having excellent moisture resistance and moisture blocking effect.

FIG. 4 is a schematic cross-sectional view of the region corresponding to the part B in FIG. 3 of the high voltage transistor chip covered with the protective film of the conventional structure, and in the figure, I4 is a PSG with a thickness of about 1 μm.
The covering insulating film 15 is Si with a thickness of about 0.2 to 0.3 μm.
, N, passivation film, and other symbols indicate the same objects as in FIG.

(Problem to be Solved by the Invention) In order to prevent the quality of the wiring made of AI or A1 alloy disposed below the protective film from deteriorating,
It is necessary to form the film at a temperature of at least 450°C or lower.

For this purpose, the Si3N4 bath basin film 15 is formed using a plasma chemical vapor phase using a mixed gas of a silicon hydride compound gas such as monosilane (Si) or dichlorosilane (SiHzClz), which can be grown at a low temperature, and ammonia (NH). Since it is formed by a growth (CVD) method, a large amount of hydrogen ions (Ho) are generated during the growth reaction, and the formed Si3N4 becomes a film containing a large amount of 110.

Therefore, in the conventional structure in which the protective film is composed of only the S40g-based insulating film, for example, the PSG insulation film 14 and the 5iJn passivation film 15, as shown in FIG. 4, the I! The positive (+) charges due to the PSG insulating film 14 reach the vicinity of the substrate surface in the field insulating film 6, and a charge storage layer 16 in which negative (-) charges are accumulated on the surface of the group +Ii1 is formed.

(An inversion layer is formed in a p-type substrate.) This accumulation layer (-) charge functions equivalently to increasing the n-type impurity concentration near the surface of the substrate l, and therefore, during operation, In the vicinity of the surface of the substrate 1, the expansion of the depletion layer extending from the base-collector junction formed between the p-type heath region 3 and the n-type collector layer 1 to the collector-collector breakdown voltage is suppressed, and the base-collector This caused the problem of deterioration of the breakdown voltage.

Therefore, the present invention aims to provide a protective insulating film structure that prevents breakdown voltage deterioration due to hydrogen ions generated during formation of a silicon nitride film in a high voltage semiconductor device that uses a silicon nitride film as a passivation film to improve moisture resistance. do.

[Means to solve the problem]

The above object has a field insulating film, an active region defined by the field insulating film, a covering insulating film made of silicon dioxide or phosphosilicate glass that covers the field insulating film and the active region, and the covering In a semiconductor device in which an insulating riser is covered with a silicon nitride passivation film, the method selectively applies to the upper S and W regions of the field insulating film within the covering insulating film without contacting the silicon nitride passivation film; This problem is solved by the semiconductor device according to the present invention, which includes an electrically floating amorphous or polycrystalline silicon layer that is not connected to the electrode wires in order to maintain insulation between the electrode wires.

[For production]

That is, in the structure of the protective insulating film according to the present invention, an electrically floating amorphous or polycrystalline silicon layer that is not connected to the electrode wiring is provided in the covering insulating film on the field insulating film that defines the active area of the semiconductor device. The dangling bonds (non-bonds) contained in large amounts in the silicon layer are used to remove H contained in the 5iJ4 passivation film formed on the coating insulating film by the plasma CVD method and diffused into the coating insulating film. The H° is captured and fixed at crystal grain boundaries with levels (saturated bonds) and levels, thereby preventing the H° from reaching the field insulating film.

Therefore, positive (+) charges are not accumulated in the field insulating film, so a charge storage layer is formed on the substrate surface under the field insulating film in the case of an n-type substrate, and an inversion layer is formed in the case of a p-type substrate. This prevents the phenomenon that the withstand voltage between the base and the collector deteriorates due to the formation of the base-collector.

The reason why the silicon layer and the 5iJ4 passivation film are not brought into contact with each other is to reduce the amount of II" captured in the silicon layer during 5isNa growth, and to maintain a large number of dangling bonds and levels in the silicon layer during operation. This is to maximize the effect.

〔Example〕

The present invention will be specifically explained below with reference to illustrated embodiments.

FIG. 1 is a schematic cross-sectional view of one embodiment of the present invention, and FIG. 2 is a schematic plan view showing the shape arrangement of a silicon (Si) layer pattern in the same embodiment.

In FIG. 1 showing the cross section of the region corresponding to B in FIG.
2 n-type silicon (Si) substrate (collector layer),
3 is the impurity concentration 10111~l Q "elm -"
5 is the impurity concentration of 1020~
n° type channel c) Si region of about 10"CI!-",
6 is a field insulating film made of silicon dioxide (SiO□), 7 is a lower insulating film made of Sing, 8 is a base contact window, and 10 is aluminum (A1) or A1.
13 is an annular ring made of A1 or A1 alloy, etc., and 14A is a first P having a thickness of about 0.5 μm.
SG coated insulating film, 17 is a polycrystalline (amorphous) silicon pattern, 14B is a second PSG with a thickness of about 0.5 to 1 μm
The covering insulating film 11 is a Si3N passivation film having a thickness of about 0.2 to 0.3 μm.

As shown in this figure, in the high voltage bipolar transistor according to the present invention, the PS on the upper part of the field insulating film 6 defining the active region 18 where the base region 3 is formed is
For example, a first PSG-covered insulating film 14A is formed in the G-covered insulating film so as to surround the active region 18 along the outer periphery thereof.
For example, a non-doped polycrystalline (amorphous) silicon pattern 17 is buried between the second PSG-coated insulating film 14B and the second PSG-coated insulating film 14B, and is not connected to the field plate 10 or the annular ring 13. In a structure without a field plate or an annular ring, this polycrystalline silicon pattern is preferably disposed over the entire upper part of the field insulating film, but as in this embodiment, each edge of the field insulating film 6 is In the structure covered with the field plate 10 and the annular ring 13, the polycrystalline (amorphous) silicon pattern 17 is at least part of the field insulating film exposed between the field plate 10 and the annular ring 13, as shown in the figure. FIG. 2 is a plan view schematically showing the shape and arrangement of the polycrystalline (amorphous) silicon pattern 17 on the entire surface of the chip in the above embodiment. Polycrystalline (
The amorphous silicon pattern 17 covers the upper part of the field insulating film exposed in the gap between the field plate (base electrode) 10 and the annular ring 13, and surrounds the active region 18 in which the base region 3 is formed. They are arranged in a ring shape.

As a result, a large amount of Si3N is included in the passivation film 11, and the second PSG coating insulating film 14B and the first PSG
Most of the H that diffuses within the SG covering insulating film 14A and attempts to reach the exposed area of the field insulating film 6 is caused by dangling bonds and crystals existing within the polycrystalline (amorphous) silicon pattern 17. It is captured in units of grain boundaries, loses its potential, is fixed, and disappears, so that the field insulating film 6 is no longer charged by the H. Therefore, a charge storage region with one potential is not formed on the substrate surface under the field insulating film 6, so that the apparent impurity concentration on the substrate surface is maintained at the substrate concentration, and the base-collector Deterioration of the junction breakdown voltage is prevented.

In the above embodiment, since AI or A1 alloy is used for the base electrode lO, the emitter electrode (11 in FIG. 3), the annular ring 13, etc., the polycrystalline (non-polycrystalline) used for the polycrystalline silicon pattern 17 is The crystalline silicon layer is formed by a plasma CVD method, a sputtering method, etc.
It is necessary to form at a temperature below ℃. At this time, if the plasma CVD method is used, a large amount of polycrystalline silicon is formed, and if the sputtering method is used, amorphous silicon is mainly formed.

Further, the reason why non-doped silicon is used for the polycrystalline (amorphous) silicon pattern 17 is that the polycrystalline (amorphous) silicon pattern 17 is used in the field plate 10 and the annular ring 13 in order to increase the effect. This is to prevent the field plate 10 and annular ring 13 from being short-circuited through the polycrystalline (amorphous) silicon pattern 17 with low resistance when they are disposed close to each other.

〔Effect of the invention〕

As described above, according to the present invention, a silicon nitride film is used as a passivation film to improve moisture resistance, and hydrogen ions that diffuse from the silicon nitride film into the insulating film can damage the substrate surface under the field insulating film. By preventing charge accumulation or inversion, the breakdown voltage of the junction formed in this region is prevented from deteriorating.

Therefore, the present invention is extremely effective when forming a resin mold type high voltage semiconductor device.

[Brief explanation of the drawing]

Fig. 1 is a schematic cross-sectional view of an embodiment of the present invention, Fig. 2 is a schematic plan view showing the shape arrangement of a silicon (Si) pattern in the same embodiment, and Fig. 3 is a schematic diagram showing a high voltage transistor chip. The plan view (a), the sectional view taken along the line A-A (b), and FIG. 4 are schematic sectional views of the conventional structure. In the figure, 1 is an n-type silicon substrate, 3 is a p-type base region, 5 is an n-type channel cut region, 6 is a field insulating film, 7 is a lower layer insulating film, 8 is a base contact window, and 10 is a base electrode. (field plate), 11 is 5i
J4 passivation film, 13 is an annular ring, 14A is a first PSG-covered insulating film, 14B is a second PSG-covered insulating film, 17 is a polycrystalline (amorphous) silicon pattern, and 18 is an active region. l 2 (2) (a) Plane opening (b), A-A arrow cross section 1% 1 withstand voltage transistor
3 A cross-section image of a cross-sectional image of the stubborn man of Fufuu Umaikongo 4-, times

Claims (1)

[Scope of Claims] A field insulating film, an active region defined by the field insulating film, and a covering insulating film made of silicon dioxide or phosphosilicate glass that covers the field insulating film and the active region, and In a semiconductor device in which the covering insulating film is covered with a silicon nitride passivation film, selectively applying the method to an upper region of the field insulating film within the covering insulating film without contacting the silicon nitride passivation film; A semiconductor device comprising an electrically floating amorphous or polycrystalline silicon layer.