JPS60186952A - Common bus connection system - Google Patents

Abstract

PURPOSE:To facilitate the easy package exchange by connecting an output circuit having a different power supply system from an I/O system control part in parallel to a connection circuit which secures connection to a common processor bus of said I/O system control part. CONSTITUTION:A processor part 200, a memory part 201 and an I/O control part 202 are connected to a common processor bus 100. The part 202 includes a control logical part 301, an interface fan-out part (connection circuit) 302 which connects the part 301 to the bus 100, and an output circuit 303 which consists of an output element using a different power supply from the part 302 and is connected in parallel to the part 302 to keep the output at a fixed level. Then an output circuit 303 using a different power supply is added to prevent the mixture of noises to the bus 100 in case the power supply of the part 202 is cut off.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a connection scheme to a common processor bus, and more particularly to eliminating the effects of power interruption during a failure.

Conventionally, when repairing a failure in a package connected to a common bus, it was necessary to turn off the power at the time of repair in consideration of the impact on the common bus.
F is handled by inserting and removing a through package, etc. For this reason, there are disadvantages in that manual intervention is often required, leading to erroneous operations and having a large impact on the system.

°The present invention has been made in view of the above-mentioned conventional circumstances.Therefore, an object of the present invention is to solve the above-mentioned drawbacks and to facilitate package replacement by connecting a simple output circuit in parallel with the bus. The objective is to provide a new bus connection method that makes it possible.

In order to achieve the above object, the common bus connection system according to the present invention provides a common bus connection method for the I10 control unit in a device in which a processor, memory, and other I10 control units are connected by a common grosser bus.
An output circuit having a power supply system different from that of the I10 system control section is connected in parallel with a connection circuit of the I10 system control section to the common processor bus.

Next, a preferred embodiment of the present invention will be specifically explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, a common processor bus 100 includes a processor section 200, a memory section 201. An I control unit 202 is connected thereto. ■ββ copper steel 1 section 202, control logic section 301.
An interface that connects the control logic section 301 and the common bus 100, a fan-out section (connection circuit) 302, and an interface that is composed of output elements with different power supplies from the fan-out section 302 and the interface, the fan-out section 302 and An output circuit 303 is connected in parallel to keep the output constant.

The failure of the I10 control section 202 largely depends on the number of fits in the control logic section 301, which occupies the main part. Therefore, in the event of a failure in the control logic unit 301, it is necessary to turn off the power to the β control unit 202 in order to replace the package. At this time, if the output circuit 303 does not exist, I
10 The effect of power failure of the control unit 202 is on the connection circuit 302.
This leads to the power being cut off, which causes noise to flow to the common bus 100.

On the other hand, as in the present invention, the output circuit 3 uses different power supplies.
By adding 03, it is possible to prevent noise from flowing to the common bus 100 when the power to the I10 control unit 202 is turned off.

As described above, the present invention allows a faulty package to be accurately replaced without complicated operations by connecting power supplies with different output circuits in parallel with a common bus access fanout circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. 100Φ・e common processor bus, 200--processor, 201...memory lJ, 202--l1011
i control section, 301...■ρ control logic section, 302...φ
Interface, fan-out section (connection circuit), 30
3... Output circuit patent applicant NEC Corporation Representative Patent attorney Yutabe Kumagai

Claims (1)

Claims: In an apparatus in which a processor, memory and other I10 control units are connected by a common processor bus. (1) A common bus connection system characterized in that an output circuit having a different power supply system from the I10 system control section is connected in parallel with a connection circuit of the ρ system control section to the common processor bus.