JPS6097452A - Memory control system - Google Patents

Abstract

PURPOSE:To allow a device to function normally even if a fault occurs to some RAM element by switching an RAM address part where an error is detected to an unused RAM address part and using it. CONSTITUTION:When the power source is turned on, a main control part 1 starts operating to write optional data in RAM parts 1-4, and then reads it to check whether the written contents coincide with the read contents or not. For example, if an error occurs in an address 1000H, 1000H is set in a buffer memory 12a and a check on the RAM parts is restarted at the head. In this case, the address 1000H is sent out the main storage part 7, a coincidence circuit 13a obtains a coincidence with the contents of the buffer 12a, so an address from an address generating circuit 14 is signified and an address of an unused part of the RAM parts is selected corresponding to the address 1000H. When an error is detected in another address, the same operation is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention provides a method for replacing a part of the defective RAM with an unused RAM when a defect occurs in a part of the RAM in a device using a RAM.
This relates to a memory control method that switches to a part of the memory.

(Background Art) As devices become more general-purpose, their program capacity increases, and a large number of memory elements are used accordingly. The memory element is read-only memory (hereinafter referred to as R).
There are ROM (abbreviated as OM), RAM, etc., but ROM is not suitable for increasing capacity due to implementation or maintenance reasons, so R
AM is used, and a floppy disk device (
A program is transferred from a FDD) or a cassette magnetic tape (CMT), and the device is operated by the RAM to which the program is transferred. Before transferring the program, a RAM write/read check is performed, and if normal, the program is transferred. If an abnormality is detected, a lamp will be displayed as an error or a buzzer will sound to prompt the non-specialist operator to make an error, and at that point the device will be at fault and will no longer function, which may cause a hindrance to business operations.

(Problem to be solved by the invention) The present invention is designed to solve the problem of detecting an error when a part of the damage W becomes an error due to a defective RAM element or the like during a RAM check.
Switch the AM address section to an unused RAM address section,
The present invention relates to a memory control method that is intended to function normally as a device even if a certain portion of a RAM element fails.

(Structure and operation of the invention) FIG. 2 shows an embodiment of the present invention, in which 1 to 4 are RAM sections for storing programs, 6 is an FDD (or CMT) section, and 7 is a RAM section in which the RAM sections 1 to 4 are stored when the power is turned on. The main control unit 8 is used to check whether the FDD is normal or not, to transfer the program from the FDD 6 to the RAM units 1 to 4, or to issue operation commands to each unit based on the program transferred to the RAM units 1 to 4. Which R of the RAM sections 1 to 4 is selected according to the address from the main control section 7?
Decoder for determining whether to select the AM section, 12a~
12n is a buffer memory for storing error addresses, 1
Reference numerals 38 to 13n refer to matching circuits that compare the error addresses accumulated in the above-mentioned 12a to 12n with the content of the address from the main control unit 7 and change the output if they are the same, and 14 refers to the matching circuits 13a to 13n of the above-mentioned matching circuits. An address generation circuit 5 generates an unused address according to the output state, and an address switching circuit 5 switches between an address from the main control section 7 and an address from the address generation circuit 14.

Next, the RAM unit control method with the above configuration will be explained with reference to the flowchart shown in FIG.

FIG. 3 is an operation flowchart from when the power is turned on until it is possible to start operation. First, when the power is turned on, an initial reset of the circuit is performed, the main control section 7 starts operation, and the RAM section 1 Write arbitrary data to ~4, read it, and check whether the written content matches the read content.If there is no abnormality as a result of this check, operate the device from the FDD unit 6. A program for doing this is transferred to the RAM units 1 to 4, and when the transfer is completed, operation can be started. If the result of the above check,
For example, if an error occurs at address 100OH, 100OH is set in the buffer memory 12a and the RAM check is started again from the beginning. When address 100OH is sent from the main control unit 7, the match circuit 13a matches the contents of the buffer 12a and the RAM is checked. An address generation circuit 14 that disables the decoder 8 that selects sections 1 to 4 and at the same time enables a RAM section that has an unused section (RAM section 4 in this embodiment) to generate an address for the unused RAM section. The address from is made valid by the address switching circuit 5, and the address from the RAM
An address for an unused portion of the section will be selected corresponding to address 100OH. Next, when an error occurs at address 150OH, set 1500H in the buffer memory 12b and start the RAM check from the beginning again.
When the OH address and the 150OH address are sent from the main control unit 7, a RAM section with an unused portion is selected as described above, and the address portion from the address generation circuit 14 is set to 100.
It will be selected corresponding to the OH address and the 1500H address, and each time an error is detected, the error address is set in the buffer memory 12c, 12d, etc.
Repeat until the AM check becomes normal or until the panzer memories 12a to 12n become full. Note that the address generation circuit 14 determines, for example, that the address of the unused portion of the RAM section is 20, depending on the state of the output of the matching circuits 13a to 13n.
If it is located after address 0OH, it may be a FROM (programmable read only memory) that can be programmed in advance so that when the matching circuit 13a outputs, the address 200OH is generated, and when the matching circuit 13b outputs, the address 2001H is generated. However, it goes without saying that it may be constructed using a logic circuit.

As explained above, even if a defect occurs in a certain part of the RAM, it is switched to an unused part of the RAM, so there is no need to prepare a spare RAM, and there is no impact on operator communication. It has the advantage of being easily realized.

(Effects of the Invention) The present invention enables operation by switching to a part of unused RAM when a part of the RAM used in normal operation is defective. It can also be used in various fields. This is particularly effective for systems that lose their system functionality due to a defect in a part of the RAM and the device goes down.

[Brief explanation of the drawing]

Figure 1 is an operational flowchart of a conventional embodiment;
The figure is a circuit diagram of one embodiment of the present invention, and FIG. 3 is an operation flowchart of the circuit of FIG. 1. 1-4...RAM section, 5...Address switching circuit, 6
...FDD section, 7... Main control section, 8... Decoder, 1.2 a to 12n... Buffer memory, 13a to
13n... Matching circuit, J4... Address generation circuit, 1
5...NOR gate, 16.AND gate. Special ¥ [Applicant Oki Electric Industry Co., Ltd. Patent application agent Megumi Yamamoto −

Claims (1)

[Claims] Random access memo IJ (RAM) before operation
In a memory control method that performs read/write checks, there is a buffer memory for specifying a memory address where an error occurred in the check, and a memory address for invalidating the memory address specified by the buffer memory and validating an unused memory address. and a memory address switching circuit.
When an error is detected in AM write/read check,
A memory control method characterized in that data specifying the memory address is written in the buffer memory and a read/write check of the RAM is performed again.