JPS601861A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain a substrate structure for performing a CMOS integrated circuit having less leakage current and high reliability by employing a silicon substrate which contains boron of special amount. CONSTITUTION:An n type epitaxial layer 102 which contains phosphorus is formed on a p type silicon substrate 101 which contains boron of 5X10<18>/cm<3> or more, and a p-well 103 is formed. Since gettering effect of ultrafine defect formed in the substrate 101 is strong to contamination of introducing in the later manufacturing steps, the leakage current in the bonding of a source drain formed on the main surface and p-well 103 or n type epitaxial layer 102 can be remarkably reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, and more particularly to a substrate structure of a semiconductor integrated circuit device using complementary insulated gate field effect transistors (CMOS transistors).

In integrated circuit devices using CMOS transistors, the p-channel or n-channel transistors are turned off during standby, so power consumption is limited to leakage current, resulting in significant power consumption savings. In order to further pursue this objective, the demand for reducing leakage current has become even stronger.

The purpose of this invention is to provide a highly reliable carbon fiber with low leakage current.
The objective is to provide a new substrate structure that realizes MO8 integrated circuits.

An integrated circuit device according to the present invention is used as a semiconductor substrate.
A silicon substrate containing boron (Bl) of ×1018/crrL3 or more is provided, an epitaxial layer grown on this substrate is doped with an n-type impurity, and a p-type impurity is introduced from the main surface. It is characterized by having a p-type impurity diffusion layer formed by a diffusion indentation method.

According to this invention, as a substrate, 5×10”/CI
Since a p-type silicon substrate containing boron with IL3 or higher is used, micro defects occur in the substrate at a high density, and defects and heavy metals are generated or introduced into the n-type epitaxial layer formed on the substrate. Contaminants such as those caused by use can be removed. Therefore, a highly reliable p-well type CMO with low leakage current
3 integrated circuit devices can be realized.

Next, embodiments of the present invention will be described with reference to the drawings. The structure shown in FIG.
On a (100) silicon substrate 101 containing boron of 3,
phosphorus with a thickness of 30 microns]
An n-type epitaxial layer 102 containing Tn'' is formed, and the surface f) center is l, X I Q'''/C
N-type Ebicataki 7yal Jfi l 0 containing m3 boron
A p-well 103 is formed with a junction depth of about 5 microns with 2.

N-type epitaxial layers 102 and 10 with this structure
The crystallinity of the p-well 103 formed in 2 is extremely good, and it is resistant to contamination introduced in the post-manufacturing process.
Since the gettering effect of micro defects formed in the 01 is strong, leakage current at the junction between the source drain formed on the main surface and the p-well 103 or the n-type epitaxial layer can be significantly reduced.

This structure corresponds to a CMO8 integrated circuit device called a p-well type, and the p-well 103 and n-type epitaxial layer 102 are connected to a ground potential (fl V ) and a 't11 source potential ( +V
cc) 1fr: It is desirable to give t p substrate] 0
It is desirable to set it in a floating state or at the power supply potential (Vcc).

FIG. 2 is a diagram showing a second embodiment of the invention. In this case, the n-type epitaxial layer 202 is 4 microns thick,
The p-well 203 has a depth of 6 microns. Therefore, p-well 203 and p+ substrate 203 are in a conductive state. In this structure as well, the rl type epitaxial layer 202 and the p-well 203 have good crystallinity as in Example 1, and the leakage NN source formed in these regions can be made extremely small. In addition, in the example, p
The well 203 and the p+ substrate 201 are electrically connected, and it is desirable that their potential is set to the ground potential (Ov).
It is desirable that the n-type epitaxial layer 202 take the power supply potential (+Vcc) from the main surface 1111. Also, it is desirable that the periphery of the device be completely obscured by the p-well 203.

[Brief explanation of the drawing]

1 and 2 are cross-sectional views of first and second actual Mti example devices, respectively, according to the present invention. In the figure, 1.01, 201-...-1) + board, 1
62,202-...n-type epitaxial R110
3,203... p-well.

Claims (1)

[Claims] In a semiconductor integrated circuit device using a complementary insulated gate field effect type i-transistor, a 5×10
A semiconductor integrated circuit device comprising a silicon substrate containing boron (131) of 18/C1n3 or more, and comprising an n-type epitaxial layer and a p-type impurity region on the substrate.