JPS60185989A - Expanded/reduced display address generator - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an enlargement/reduction display address generation device for a multi-window system.

Conventional structure and its problems In recent years, methods have been developed to facilitate the operations of comparing, collating, or transcribing and editing multiple document information by dividing and managing the display screen into several rectangular display areas called "windows." is attracting attention. However, if you want to make the window flexible so that multiple windows can be opened at any position and you want to enlarge or reduce the image data within the window, you will need an efficient enlargement or reduction display method. A reduced address generator is required.

The conventional enlargement/reduction display method is shown below.

Figure 1 shows a conventional enlargement/reduction display method, in which 1 is an image memory that holds image information, 2 is a display device, and 3 is a frame memory that corresponds one-to-one to the display pixels of the despray device 2. It is.

The operation of the conventional enlargement/reduction display method configured as described above will be described below.

In FIG. 1, when the contents of image memory 1 are to be enlarged and displayed in window 4, for example, the area of image memory 1-1 is enlarged and transferred to the area of frame memory 3-1 corresponding to the pixels of window 4. .

When displaying the contents of the image memory 1 in a reduced size within the window 4, for example, the area of the image memory 1-2 is compressed and transferred to the area of the frame memory 3-1. Usually, this transfer is controlled by software and has the problems of being time consuming and requiring a frame memory.

FIG. 2 shows an enlargement/reduction display method using a conventional display address generator that does not require a frame memory. FIG. 2(,) shows a block diagram of a conventional equal-magnification display device, and 5 is a conventional display address generation device which generates a read address of an image memory in units of words. 6 is a shift register which softens one word (n bits) of data from the image memory by one bit each time a control signal is input. The operation of the same-size display device using the conventional display address generation device configured as described above will be described below. One word (n bits) of the image memory selected by the address generator is transferred to the shift register 6.
It transmits display data (DATA1) bit by bit to the display in synchronization with a timing signal that displays one pixel on the display screen (approximately 60 MHz when displaying 6Q images per second with 1000 x 1000 display pixels, hereinafter referred to as DCLK). ) is the signal that the soft register is empty when there are no valid bits in the shift register (
EMP) is output, one word to be displayed next is fetched from the image memory, and the above operation is repeated.

FIG. 2(1)) is a block diagram showing a reduced display method using a conventional display address generator. Figure 2(a)
The difference is that the control signal has a frequency that is a reduction rate (20) times that of DCLK. Display data (DATA2) is generated in synchronization with this control signal. If the contents of this DATA2 are sampled and displayed with DCLK, 1/ZO
Can be displayed in reduced size.

However, this method requires a control signal that is twice the reduction rate of DCLK. For example, if 1/8 reduction is performed at 60 images per second with 1000 x 1000 display pixels, the control signal will be approximately 480 MHz, which requires a high-speed shift register. and DATA2 synchronized to 480 MHz.
The problem is that it is necessary to sample at 60 MHz.

FIG. 2(C) is a block diagram showing an enlarged display method using a conventional display address generator.

The difference from the second figure (Figure 2) is that a signal obtained by dividing DCLK by an expansion factor (ZI) is input as the control signal of the soft register 6. 7 is a rate multiplier that divides DCLK by an expansion rate. By this method, display data (DATA3) is generated in synchronization with the signal obtained by dividing the DCLK magnification rate.
is generated. If the contents of DATA3 are sampled and displayed using DCLK, the displayed contents will have the same ZI bit, and the display can be enlarged by ZI times.

However, with this enlargement method, there are cases where overlapping windows cannot be correctly enlarged.

Problems with this method will be explained below using FIG. 3.

FIG. 3 (-) shows an example of overlapping windows. 8-1.8-2 indicates a window and window 8
Assume that −1 is a higher priority window, and x1~
X4. Y1 to Y4 do not indicate the horizontal and vertical boundary coordinates of the window on the display screen.
) shows a problem that occurs when the window 8-2 of 1.) is displayed with zr magnification.

For example, when displaying on the Y2 scanning line, the display of the window 8-2 starts from the end boundary x3 of the window 8-1. Starting boundary of window 8-2
(7) If the interval 94ΔX (=X3-X2) is not an integer multiple of 75EZI, if you do not control how many times the display data at x3 is repeatedly displayed, for example, the display on the Y3 scanning line and the bit deviation may occur. arise. Generally, the number R of this repetition is called an expansion initial value, and is defined as ΔX R−Z I 2110 d (z□) ΔX. Here, mo and d(-) are the remainder when ΔX is divided by ZIl, and ΔX is the width (number of display pixels) where the display is hidden by the high priority window. 0 Enlargement method shown in Figure 2 (C) above In this case, this initial value of enlargement cannot be handled, and it is impossible to enlarge and display a window with a heavy weight of +Fl.

OBJECT OF THE INVENTION The present invention solves the above-mentioned conventional problems, and provides an enlargement/reduction display address generation device that introduces the idea of an initial value for enlargement and can perform correct enlargement/reduction display in real time without requiring a frame memory. The purpose is to provide

Structure of the Invention The present invention includes a boundary table that holds display parameters at window boundaries that exist on one scanning line, a register that holds the address of data to be displayed, an adder that updates the address, and a register that holds the address of the data to be displayed. This is an enlargement/reduction display address generator equipped with a register and decrementer to control updates, and a counter and comparator to manage boundary positions.It is realized by dedicated hardware and introduces the idea of an initial value for expansion. And it is possible to generate the correct address of enlargement/reduction of life in real time.

DESCRIPTION OF EMBODIMENTS FIG. 4 shows a block diagram of an enlarged/reduced display address generator in the first embodiment of the present invention. In FIG. 4, 9 is a one-word boundary management table, and horizontal Coordinate of window border in direction (3).

Display start address at window border (ADR8)
, the number of enlargement magnifications (hereinafter referred to as enlargement ratio) (Z-work), the number of reduction magnifications (hereinafter referred to as reduction ratio) (20).

Holds the expansion initial value ([(). 10 is an address register that stores the display start address (AD) of the boundary management table 9.
R3)-1: Or inputs the output of the adder 11 and holds the address (ADDRESS) of the image memory to be displayed. Reference numeral 11 denotes an adder which adds the contents of the address register 10 and the reduction ratio 20 to calculate the result (address to be displayed next). When the ZERO signal, which will be described later, is "'ON", the result is stored in the address register. Reference numeral 12 denotes a register which inputs the expansion initial value R of the boundary management table 9, the expansion rate ZI, or the output of the decrementer 13. 13 is a decrementer which inputs the output of register 12 and returns the output to the decrementer 12 until the value subtracted by 1 becomes Q''', and the value becomes "0".
If so, a second input control signal (ZERO) is output to the address register 10 and register 12. A horizontal counter 14 is reset by the horizontal retrace signal H8YNC, counts up every dot clock DCLK during each horizontal scan, and holds the coordinates of pixels in the horizontal direction. 15 is a comparator that calculates the coordinate X of the boundary management table 9 and the horizontal counter 1
Compare the contents of 4 and if they match, address register 1o
and outputs a first input control signal (EQ) to the register 12.

The operation of the enlarged/reduced display address generator of this embodiment, which is constructed as described above, will be explained below with reference to FIG.

FIG. 6(a) shows the case of enlarged display. (G) shows the window boundary. Here, the window boundary coordinates are x1 display start address, DR8, expansion initial value 2, and expansion rate 4. In other words, in the boundary management table 9, ADR8-"ADR3 ”, 20-“”1” (
Due to enlarged display, the reduction ratio is 1), R="2", ZI="
4", 0 horizontal counter 14 containing X="X" (
When 1) becomes "x", the EQ output ←) of the comparator 15 becomes 'ON', and the address register 10 (
4), 2" is input to "ADRS"75; register 120). Adder 11 inputs 'ADR3+1
The decrementer 13 inputs °゛2''' and subtracts it by 1, which then outputs the value "1".
4 (one) advances to "X+1"), it is returned to register 12ψ). When the timing of the horizontal counter 14 (one) is "X+1", the signal ZERO (to) is 'ON'
Therefore, the contents of the address register 10 are the same as when the timing is "X", and the register 12 becomes "P1".

The decrementer 13 inputs °゛1'' and subtracts it by 1, and the value becomes PA0''. Therefore, at the next timing (when (1) advances to "X + 2"), it turns on the signal ZERO (to) °'ON'
At the timing of ``X + 2'', the ZERO signal (E) is ``ON'', so the address register 10 (3) is filled with ``ADR8+1'' prepared by the adder 11. The value is entered and register 1
2ψ) is inputted with an enlargement rate of "4". Thereafter, this operation is repeated every time the decrementer 13 reaches °゛○'''.

FIG. 5(b) shows the case of reduced display. ) This is a diagram showing the window boundary, where the window boundary coordinates are X2 and the display start address is ADR3'.

The reduction rate is set to 4. That is, in the boundary management table 9, ADRS="ADR3"' and ZO="4".

R=ZI=“1” (initial value for enlargement for reduced display.

The magnification ratio is "I")X-"When the 0 horizontal counter 14 (one)' containing "X/" becomes It "A D RS'" is inputted to the register 12 (the enlarged initial value "1"). Adder 1
1 outputs "ADR8'+4'". At this time, the decrementer 13 inputs “1” and the value subtracted by 1 is °°Q.
'', so the next ((tsu)' is °'X'+ 1 '''
ZERO signal (e)' at the timing of "0"
Set to "N".Horizontal counter 1ts (tsu)'ka"
'+ 1' Note C is ZERO signal (E)'
is “ON”, address register 10 (3
)′ prepared by the adder 11 in °'ADH3'+
The value of 4" is input, and the magnification rate is entered in register 12 γ.
1” is input. From then on, the value of register 12 is always ’1.
'', the ZERO signal (→' is "ON") The value of the tonary address register 10 (2)' is added by 4' (reduced value) every time, and the horizontal force counter 5' is "X".
'+2''', ...... ``X + 6'', address register 1o (, d''j' is ``ADR3''+
B'',...

"A D RS' + 24"'.

As described above, according to this embodiment, by introducing the idea of an initial value for enlargement and providing hardware that can be used for both enlargement and reduction, the enlargement/reduction display address can be generated from any position using the minimum amount of hardware. can do.

A second embodiment of the present invention will be described below with reference to the drawings.

FIG. 6 is a block diagram of an enlarged/reduced display address generator showing a second embodiment of the present invention. In the figure, 1Q is an address register, 11 is an adder, 12 is an address register,
13 is a register, 13 is a decrementer, 14 is a horizontal counter, and 15 is a comparator, which is the same as the configuration shown in FIG. 4.

The difference from the configuration shown in FIG. 4 is that the boundary bone tile table 16 is
When the output signal EQ of the comparator 15 is 1'', the reduction rate (20) of the boundary management table 16 is calculated by comparing the total number of window boundary words appearing on two horizontal scans and the latch circuits 17-a and 17-b.

The two points are that the enlargement ratio (ZI) is provided to be latched, and that the pointer 18 is provided to indicate the reading position of the boundary management table 16.

The operation of the expansion/reduction address generator of the second embodiment configured as described above will be explained below.

The display parameters at the window boundary appearing on the next scanning line during the horizontal retrace time are stored in the boundary management table 16 in the order in which the window boundary appears in the horizontal direction. The pointer 18 is reset by the horizontal synchronization signal (H, 5YNC) so as to point to the beginning of the boundary management table at the start of each horizontal scan.

When entering the CRT display area, the contents of the boundary table 16 indicated by the pointer 18 are selected, and the comparator 15 compares the coordinates (3) of the window boundary with the contents of the horizontal counter 14 that holds the horizontal coordinates on the screen. be done. When the window boundary coordinates match the coordinates on the screen, the comparator 16 sets the EQ multiplication signal 1". Since the EQ multiplication signal 1" is -), the address register 1o
, the register 12, and the latches 17-a and 17-b respectively calculate the display start address (ADR8), initial expansion value (however), and reduction rate (2) from one word of the boundary table indicated by the pointer 18.
0) and enlargement ratio (ZI) data. When the pointer 18 also becomes the EQ multiplication signal 1'', it is advanced one step to indicate the next word in the boundary management table 16.

When the pointer 18 points to the next word in the boundary management table 16, the window boundary coordinate (3) changes and the EQ multiplication signal becomes On. Until the new window boundary coordinates (3) match the contents of the horizontal counter 14, the address (ADD
RESS) is generated by dedicated hardware (configured similarly to FIG. 4).

The new window boundary coordinate (3) is horizontal counter 1
If it matches the contents of 4, repeat the above-mentioned operation.

According to this embodiment, by providing a boundary management table on the side of the total number of window boundaries so as to hold display parameters in the order in which the window boundaries appear, the enlargement/reduction display address can be adjusted in any continuous area. It can occur.

In addition, the reduction rate (ZO) of boundary management table 9t taba 16
, initial enlargement value (however), and enlargement ratio (ZI) are all set to 1n, it goes without saying that a same-size display address can be generated.

Effects of the Invention The enlargement/reduction display addressing device of the present invention includes a boundary table that holds display parameters at a window boundary existing on one scanning line, a register that holds the address of data to be displayed, and a register that holds the address of data to be displayed. an adder that updates;
By providing registers and decrementers to control address updates, and counters and comparators to manage boundary positions, it is possible to generate addresses for enlarged/reduced display in real time, and the practical effect is big.

[Brief explanation of the drawing]

Figure 1 is a block diagram for explaining the conventional enlargement/reduction display method, Figures 2 (,) to (c) are block diagrams for explaining other conventional enlargement/reduction display methods, and Figure 3 (a)
, (b) is a schematic diagram showing the relationship between window overlap and the initial enlargement value, FIG. 4 is a block diagram of the enlargement/reduction display address generator in the first embodiment of the present invention, and FIG.
Figures (a) and (b) are timing diagrams of the first embodiment,
FIG. 6 is a block diagram of an enlarged/reduced display address generator according to a second embodiment of the present invention. 9...1 word boundary management table, 10...
...Address register, 11...Adder, 12.
...Register, 13 ...Decrementer, 1
4 ... Karan Hisa 16 ... Comparator, 1
6...Multi-word boundary management tabletop 1y-a
, 17-b-- Chitch, 18... Pointer. Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
r! ! 4 Figure 3 4 Cause ADDRESS 5th Figure ZERO 7: ERo Figure 6 DDtN:,b

Claims (1)

[Claims] CR7 Start of display indicating the readout address of the image memory device that stores display data corresponding to the window boundaries for multiple windows defined with display priority in the overlapping portion of the display area on the display screen. Address and scaling of the horizontal image memory display in the window, yet scaling down the high priority window from the starting point of the lower priority window? - An initial expansion value, which is the value obtained by subtracting the remainder obtained by dividing the horizontal displacement to the lower boundary in the scanning direction by the expansion magnification number, and the coordinates of the window boundary in the order of appearance in the horizontal direction. A boundary management table to be held, a first register whose first input is the display start address of the boundary management table, the reduction magnification number of the boundary management table, and the output of the first register are added together, and the result is added to the an adder having a second input to the first register; a second register having the expansion initial value of the boundary management table as the first input and the expansion magnification number as the second input; The output of the register is input and the value subtracted by 1 is obtained from the second
as the third input to the register, and the output is °′0
'', a decrementer that generates a second input control signal to the first and second registers, a counter that counts the display pixels in the horizontal direction of the screen, and a boundary of the boundary management table of the boundary management table. It is characterized by comprising a comparator that compares the coordinates with the contents of the counter and generates a first input control signal to the first and second registers if they match, and uses the contents of the first register as a display address. Enlarged/reduced display address generator.