JPH1124650A - Image enlarging/reducing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enlarge/reduce an image at an arbitrary magnification including a fraction rate despite of a simple constitution by setting an enlarging/reducing process timing at two or more different cycles being integer times as many as a readout clock. SOLUTION: When an image signal S is inputted, respective pixel signals Sn are stored in an image memory 2. Then, no compensation is performed for the respective pixel signals Sn. In enlarging/reducing an image, a host processor 5 provides a timing generation processor 4 with parameters P1-4 according to the magnification of the enlargement and the reduction. It reads out the respective pixel signals Sn stored in the image memory 2 in order and increases a count value K of an address generation circuit 3 by synchronizing it with a pixel clock DCLK. In relation to the image signals stored in the image memory 2, the count value K showing the readout address is thus controlled as holding or thinning out along the cycle shown by the parameters so that the image signal S is enlarged or reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image enlargement / reduction apparatus for enlarging or reducing a digital image signal.

[0002]

2. Description of the Related Art Conventionally, as a method of enlarging a video screen to an integral multiple or reducing it to an even number, an A / D conversion of an image signal constituting the video screen is performed. There is known a technique of temporarily storing data in a video buffer and controlling the read address or the write address of a pixel on a video screen.

For example, in the case of enlarging an image signal in the main scanning direction, the increase of the read address may be stopped, and control may be performed so that the same image signal is repeatedly read into adjacent pixels. In the case of reduction, the increment of the read address in the main scanning direction may be increased, and control may be performed so that the image signal is skipped and read while being thinned out.

Also, in the case of enlarging or reducing an image signal in the sub-scanning direction, control to stop the increase of the read address or control to increase the increment of the read address may be similarly performed. For example, in the case of enlargement, if the read address is reduced by returning it from the current value by one horizontal retrace (hereinafter referred to as a line), control is performed so that image signals of the same line are read in duplicate. Good. In the case of reduction, the read address may be controlled to be increased by one line from the current value so that the image signal for one line is skipped and skipped.

For example, when an original image is enlarged twice in the main scanning direction and the sub-scanning direction, the read address is increased and stopped alternately in the main scanning direction, and on the other hand, in the sub-scanning direction. The normal increase of the read address and the decrease of the increase are alternately performed, so that each image signal of the original image is displayed twice on the screen as the main scan direction, while the sub-scan direction is displayed. Each image signal for one line in the original image is displayed twice.

By the way, the image signal is doubled or 1/2.
It is important not only to use a simple integer ratio such as doubling, but also to easily perform scaling at any fractional ratio.

For example, there is no problem in displaying a video signal on a video screen as it is when the video signal is enlarged or reduced. However, the video signal is displayed on a screen having a different aspect ratio of pixels, for example, a monitor such as a CRT for a computer. Is displayed, the original image may not be displayed normally.

That is, a video signal typically represented by NTSC is composed of vertically elongated pixels having an aspect ratio of 4: 3. This is because humans are sensitive to the visual resolution in the horizontal direction, so that the number of pixels in the horizontal direction is increased to make the image finer. On the other hand, the pixels of a computer monitor have a square shape and different aspect ratios. For this reason, when a video signal is projected on this monitor, the original image is distorted horizontally. In this case, if the number of pixels in the horizontal direction is increased to 3/4 or the number of pixels in the vertical direction is increased to 4/3, an image is formed with a correct image.

For example, in recent computers, a graphic user interface (GUI) is used as an operating system, and the size of the window in which the user works can be set arbitrarily in the vertical and horizontal directions. Therefore, even when a video image is displayed in a window, it is necessary to flexibly scale the video image in accordance with the size and aspect ratio of the set window.

For example, if the number of pixels in the horizontal direction × the vertical direction is 5
In the case where a video signal of 12 × 240 pixels is scaled up to 332 × 255 pixels, a fractional ratio such as 83/128 is reduced in the horizontal direction and a fractional ratio such as 51/48 is expanded in the vertical direction. become.

The apparatus disclosed in Japanese Patent Laid-Open No. 3-120981 is provided with a horizontal enlargement register and a vertical enlargement register in which an enlargement pattern is set in advance, and a shift register capable of loading the value of each register. . The shift register is shifted based on the pixel transfer clock, and if the least significant bit is 1, the original image can be enlarged by setting the address increment to 0 for enlargement.

[0012]

However, in the apparatus disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 3-120981, for example, as described above, 512 × 240 pixels to 332 × 25 pixels are used.
When scaling up or down to 5 pixels, a shift register and an enlargement register of at least 128 bits in the main scanning direction and at least 51 bits in the sub-scanning direction are required.
In addition, it is necessary to prepare in advance scaling registers corresponding to all the scaling patterns. For this reason, the cost for hardware increases.

The present invention has been made in view of the above problems, and has as its object to provide an image enlarging / reducing apparatus capable of enlarging and reducing an image at an arbitrary magnification including a fractional ratio with a simple configuration. It is in.

[0014]

According to a first aspect of the present invention, there is provided an image enlargement / reduction apparatus for storing an image signal displayed on a screen having a main scanning direction and a sub-scanning direction. Every time the read address of the image signal from the image signal advances by a predetermined number in synchronization with the read clock by the address generation unit, the increase of the read address is temporarily stopped for the enlargement in the main scanning direction, and Read address is 1 for enlargement in the scanning direction.
Image enlargement by returning horizontal retrace and inserting an insertion pixel into the image signal to enlarge the image, while reducing the image by increasing the read address increment and skipping the image signal in response to a reduction processing request In the reduction device, a control unit that determines two or more different cycles that are integral multiples of the read clock and that indicates a scaling processing timing, and a timing generation unit that sets the scaling processing timing based on the cycle. It is characterized by having.

According to the above configuration, the enlargement / reduction processing timing is set in two or more different cycles that are integral multiples of the read clock.

At the enlargement / reduction processing timing, a pixel is inserted according to the enlargement processing request, and the image data is skipped from the image memory according to the reduction processing request.

Therefore, it is only necessary to store the cycle indicating the enlargement / reduction processing timing, and it is not necessary to previously store the temporal pattern of all the actual enlargement / reduction timings. Therefore, a large-scale storage device is not required. At the same time, there are two or more cycles. By combining these cycles,
Fine setting of an arbitrary enlargement / reduction ratio becomes possible.

Unlike the apparatus disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 3-120981, when scaling from 512 × 240 pixels to 332 × 255 pixels as described above, at least 128 bits and A shift register and an enlargement register of at least 51 bits in the scanning direction,
There is no need to prepare in advance a scaling register or the like corresponding to all scaling patterns. Therefore, an increase in hardware cost can be suppressed.

Therefore, the image can be enlarged / reduced at an arbitrary magnification / reduction ratio including the fraction ratio with a simple configuration.

According to a second aspect of the present invention, in addition to the configuration of the first aspect, the address generation unit stops increasing the read address as the insertion pixel for enlargement in the main scanning direction. When the readout address is returned by one horizontal retrace, the image signal indicated by the readout address is inserted when the readout address is returned by one horizontal blanking. Features.

According to the above configuration, since the read pixel is read again from the read address when the increase of the read address is stopped, the image signal indicated by the read address read immediately before the insertion is inserted before the insertion. You.

Therefore, a new configuration for generating an insertion pixel is not required.

Thus, in addition to the effect of the configuration of the first aspect, the image can be enlarged / reduced at an arbitrary magnification / reduction ratio including the fractional ratio with a simpler configuration.

According to a third aspect of the present invention, in addition to the configuration of the first aspect, the control unit issues an interpolation instruction indicating whether or not to interpolate the density value of the inserted pixel during the enlargement processing. A line memory for storing density values of a plurality of peripheral pixels located around the inserted pixel on the screen after insertion in response to the enlargement processing request and the interpolation instruction; and When a pixel is inserted, the density values of the peripheral pixels are added together while adding weights in accordance with the interpolation instruction, so that the density value of the peripheral pixel is calculated as the density value of the inserted pixel. A density value setting unit that sets a value exceeding the minimum density value and less than the maximum density value.

According to the above arrangement, when inserting an insertion pixel at the time of enlargement processing, as the density value of the insertion pixel, of the density values of a plurality of peripheral pixels located around the insertion pixel on the screen after insertion, A value exceeding the minimum density value and less than the maximum density value is set.

Therefore, at the pixel insertion position, an enlarged image having an intermediate density value between the dark portion and the light portion in the periphery is obtained.

Thus, in addition to the effect of the first aspect, the gradation change between the pixels of the enlarged image can be smoothed, and the deterioration of the image quality of the enlarged image can be reduced.

[0028]

BEST MODE FOR CARRYING OUT THE INVENTION

[Embodiment 1] An embodiment of the present invention will be described below with reference to FIGS. As shown in FIG. 1, an image scaling device 1 according to the present embodiment includes an image memory 2, an address generation circuit (address generation unit) 3, a timing generation processor (timing generation unit) 4, and a host processor ( A controller 5). An image signal S of an original image digitized by an A / D converter or the like is input to the image memory 2 from the outside. The pixel clock D _CLK , the vertical synchronization signal V _SYNC , and the horizontal synchronization signal H _SYNC are input to the address generation circuit 3 and the timing generation processor 4. On the other hand, the image memory 2 outputs an image signal S 'that has undergone enlargement / reduction processing, and an enlarged or reduced image is formed based on the image signal S'.

The image signal S is a pixel signal S1,
S2,..., Sn,. Hereinafter, this pixel signal is generically referred to as Sn. Further, the image signal S '
Are composed of pixel signals S1 ′, S2 ′,..., Sm ′,. Hereinafter, this pixel signal is generically referred to as Sm '.

The input image signal S is C
Video signals from a solid-state imaging device such as a CD are converted to A /
Not only D-converted data but also digital image data obtained from another video decoder chip or the like can be directly input without going through A / D conversion.

The timing generation processor 4 includes a first x-direction processor 6, a second x-direction processor 7,
A y-direction processor 8 and a second y-direction processor 9 are provided. The first x-direction processor 6 and the second x-direction processor 7 constitute an x-direction processor. The first y-direction processor 8 and the second y-direction processor 9
Constitute a y-direction processor.

The host processor 5 outputs 8-bit enlargement / reduction parameters P1 to P4. These are the first x-direction scaling parameters P
1, a second x-direction scaling parameter P2, a first y-direction scaling parameter P3, and a second y-direction scaling parameter P4. Hereinafter, it is simply referred to as a parameter. Each of the parameters P1, P2, P3, and P4 is the first x
The signals are input to the direction processor 6, the second x-direction processor 7, the first y-direction processor 8, and the second y-direction processor 9.

Each of these parameters is a positive or negative integer. A positive sign indicates that the enlargement process is performed based on the parameter, and a negative sign indicates that the reduction process is performed based on the parameter.
On the other hand, the absolute value of the parameter indicates a cycle of the enlargement processing or the reduction processing, and indicates information on how many read addresses are to be read for duplication for enlargement or skip for reduction.

The first x-direction processor 6, the second x-direction processor 7, the first y-direction processor 8, and the second y-direction processor 9 are provided with registers 6a, 7a, 8a, 9a for storing the above parameters, respectively. ing. The register values of the registers 6a, 7a, 8a, and 9a are R1, R2, R3, and R4, respectively.

The first x-direction processor 6 and the second
x direction processor 7, first y direction processor 8, second y processor
The direction processor 9 has an x-direction counter 6
b, 7b and y-direction counters 8b, 9b are provided. Each x direction counter 6b, 7b, y direction counter 8
b, 9b are counted as K1, K2, K3, and K, respectively.
4 is assumed.

The first x-direction processor 6 generates an enlargement instruction signal x1 or a reduction instruction signal x1 '(not shown) based on the parameter P1, the pixel clock _DCLK , the vertical synchronization signal _VSYNC and the horizontal synchronization signal _HSYNC . The address is input to the address generation circuit 3. The second x-direction processor 7 includes a parameter P2, a pixel clock D
_CLK, based on the vertical synchronization signal V _SYNC and horizontal synchronization signal H _SYNC, and generates a reduced instruction signal x2 'to enlargement instruction signal x2 or not shown, so as to input to the address generating circuit 3.

The first y-direction processor 8 generates an enlargement instruction signal y1 or a reduction instruction signal y1 '(not shown) based on the parameter P3, the pixel clock _DCLK , the vertical synchronization signal _VSYNC, and the horizontal synchronization signal _HSYNC . The address is input to the address generation circuit 3. The second y-direction processor 9 includes a parameter P4, a pixel clock D
_CLK, based on the vertical synchronization signal V _SYNC and horizontal synchronization signal H _SYNC, and generates a reduced instruction signal y2 'to enlargement instruction signal y2 or not shown, so as to input to the address generating circuit 3.

The enlargement instruction signal x1 and the reduction instruction signal x1 'are also input to the second x-direction processor 7. The enlargement instruction signal y1 and the reduction instruction signal y1 'are also input to the second y-direction processor 9.

On the other hand, the address generation circuit 3 increases in synchronization with the pixel clock _DCLK for image reading, and switches the vertical synchronization signal _VSYNC from "High" to "Low", that is, every vertical blanking period. Is provided with an address counter 3a for clearing to zero. Address counter 3
“a” is used to specify a read address in the image memory 2. The count value of the address counter 3a for designating the read address is K.

As will be described later, the address generation circuit 3 performs the above-described enlargement instruction signals x1 and x1 for each pixel in the original image.
2, based on reduction instruction signals x1 ', x2', or
For each line in the original image, the enlargement instruction signal y1,
An operation for holding or thinning out the count value K is performed based on y2 and the reduction instruction signals y1 'and y2'. Then, according to the read address, while the pixel signal is duplicated or skipped from the image memory 2,
An image signal S 'is output. As a result, the image can be enlarged or reduced.

Next, the operation of the image enlargement / reduction device 1 based on the above configuration will be described. First, when the image signal S is input, each pixel signal Sn is stored in the image memory 2.
At this time, no correction or the like is performed on each pixel signal Sn. The address generation circuit 3 advances the write address to the image memory 2 by one. Thus, the image signal S is stored in the image memory 2.

Next, an image signal S 'is generated from the image signal S in the image memory 2 as follows.

Firstly, the case where no scaling is based on a pixel clock D _CLK, reads out the pixel signals Sn stored in the image memory 2 in order. At this time, as shown in FIG. 2, the pixel clock D _CLK , the vertical synchronizing signal V _SYNC and the horizontal synchronizing signal H _SYNC are input. And as mentioned above, repeated cycles of zero clear for each vertical synchronizing signal V _SYNC with increased in synchronization with the count value K of the address generating circuit 3 to the pixel clock D _CLK.

When performing scaling, first, the host processor 5 gives the parameters P1 to P4 to the timing generation processor 4 in accordance with the scaling factor of scaling. Here, a process of expanding in the x direction using the first x-direction processor 6 and not using the second x-direction processor 7 will be described. For example, consider a case where “+5” is given to the first x-direction processor 6 as the parameter P1.

Since the parameter P1 has a positive sign, it means an enlarging process. The parameter P1 is latched by the register 6a, and as shown in FIG. 3, "+5" is stored as the register value R1. That is, R1 = P
1 = 5.

[0046] Similarly in FIG. 2, on the basis of the pixel clock D _CLK, reads out the pixel signals Sn stored in the image memory 2 in order. Then, repeat the cycle is reset to zero for each vertical synchronization signal V _SYNC with increased in synchronization with the count value K of the address generating circuit 3 to the pixel clock D _CLK.

On the other hand, the count value K1 of the x-direction counter 6b of the first x-direction processor 6 is such that the level of the horizontal synchronization signal H _SYNC is changed from "High"("1") to "Low".
Is cleared to zero by comprising a ( "0"), increases in synchronization with the pixel clock D _CLK. Then, in the first x-direction processor 6, the count value K1 and the register value R1 (=
The absolute value of P1) is compared.

When K1 becomes 5 and matches the absolute value of R1, the first x-direction processor 6 changes the level of the enlargement instruction signal x1 from "Low"("0") to "Hig" at this point.
h ”(“ 1 ”), while the level of the enlargement instruction signal x1 is“ High ”, the address generation circuit 3 stops increasing the count value K, that is, the read address. the K1 is two clock to the next pixel clock D _CLK of time consistent with the absolute value of R1 is in a state of being kept in 5.

Therefore, in the next pixel clock _DCLK at the time when K1 matches the absolute value of R1, the pixel signal (S5) read out from the image memory 2 by the immediately preceding pixel clock _DCLK is replaced by the current pixel clock. It is output again at the timing of the clock _DCLK . At the same time, since the count value K1 further increases and exceeds the absolute value (= 5) of the register value R1, the x-direction counter 6b is cleared to zero at that time, and the level of the enlargement instruction signal x1 is set to "High".
("1") is returned to "Low"("0"). And
The above increase and comparison are repeated.

More specifically, when "+5" is given as the parameter P1 as described above, the count value K becomes K = 5, 10, 15,..., 5 + 5. (U−1),... (U is a natural number). At this time, the image signal S ′ output from the image memory 2 at this time is the image signal S
Of the pixel signals Sn (n
= K) are output in duplicate.

In general, if P1 = p (> 0), K is held when K = p + p (u-1).

As a result, in the above example, if the input image signal S has 512 pixels in the x direction, 5
Since the result of dividing 12 by 5 is 512 = 5 × 102 + 2, the number of pixels that increase after enlargement is 102. Therefore, the number of pixels in the x direction after the enlargement is 512 + 102 = 614 (pieces). That is, from 614/512 ≒ 6/5, an image signal S ′ representing an image obtained by enlarging the image represented by the image signal S approximately 6/5 times in the x direction is obtained.

Further, in the case of performing i-fold (i is an integer of 2 or more) enlargement of the count value K is stopped for (i-1) clocks of the pixel clock _DCLK for each count value K. Thereby, all the count values K are output from the address generation circuit 3 i times. Then, each pixel signal Sn is synchronized with the pixel clock _DCLK by i
What is necessary is just to read it every time.

Next, a description will be given of a process of reducing in the x direction using the first x-direction processor 6 and not using the second x-direction processor 7. In this case, the procedure is basically performed in the same procedure as the above-described enlargement processing. In the case of the reduction process, the parameter P1 is given as a negative number. For example, consider a case where “−5” is given to the first x-direction processor 6 as the parameter P1.

Since the parameter P1 has a negative sign, it means a reduction process. The parameter P1 is latched by the register 6a, and as shown in FIG. 4, "-5" is stored as the register value R1. That is, R1 = P
1 = −5.

[0056] Similarly in FIG. 2, on the basis of the pixel clock D _CLK, reads out the pixel signals Sn stored in the image memory 2 in order. Then, repeat the cycle is reset to zero for each vertical synchronization signal V _SYNC with increased in synchronization with the count value K of the address generating circuit 3 to the pixel clock D _CLK.

On the other hand, the count value K1 of the x-direction counter 6b of the first x-direction processor 6 indicates that the level of the horizontal synchronization signal H _SYNC is changed from "High"("1") to "Low".
Is cleared to zero by comprising a ( "0"), increases in synchronization with the pixel clock D _CLK. Then, in the first x-direction processor 6, the count value K1 and the register value R1 (=
The absolute value of P1) is compared.

When K1 becomes 5 and coincides with the absolute value of R1, the level of the reduction instruction signal x1 'is changed to "Lo" at this point.
w ”(“ 0 ”) to“ High ”(“ 1 ”) The level of the reduction instruction signal x1 ′ is changed from“ Low ”to“ High ”
h ”, the address generation circuit 3 normally operates at +1
Is set to +2. As a result, K
The next pixel clock D at the time when 1 matches the absolute value of R1
_{In the case of CLK} , the count value K increases by 2 after 4 to 6, and the pixel signal (S5) corresponding to 5 is skipped and skipped.

Therefore, the pixel signal (S6) read from the read address indicated by the count value K = 6 is output from the image memory 2 at the next pixel clock _DCLK at the time when K1 matches the absolute value of R1. With it,
Since the count value K1 further increases and exceeds the absolute value (= 5) of the register value R1, at that time the x-direction counter 6
b is cleared to zero, and the level of the reduction instruction signal x1 'is returned from "High"("1") to "Low"("0"). Then, the above increase and comparison are repeated.

More specifically, as to the timing of skipping, the parameter P1 is set to "-5" as described above.
Is given, K = 5, 12, 19,..., 5 + 7 (u−1),... (U is a natural number) are thinned out and are not generated. At this time, the image signal S ′ output from the image memory 2 is output by skipping the pixel signal Sn (n = K) corresponding to the count value K in the image signal S.

In general, if P1 = p (<0), K is held when K = (− p) + (− p + 2) (u−1).

As a result, in the above example, when the input image signal S has 512 pixels in the x direction,
Since the result of dividing 512 by 7 (= −P1 + 2) is 512 = 7 × 73 + 1, the number of pixels reduced after reduction is 73. Therefore, the number of pixels in the x direction after reduction is 512-73 = 439 (pieces). That is, from 439/512 ≒ 6/7, an image signal S ′ representing an image obtained by reducing the image represented by the image signal S by approximately 6/7 in the x direction is obtained.

As described above, in the present embodiment, once
The image signal S stored in the image memory 2 is controlled so that the count value K indicating the read address is held or thinned out in accordance with the cycle indicated by the above parameter, thereby performing the enlargement / reduction processing of the image signal S. Like that.

Next, a description will be given of a scaling operation in the x direction having an arbitrary scaling factor including a fraction ratio. In the above description, an example in which only the x-direction processor 6 is used has been described. However, when scaling is performed at an arbitrary scaling factor, the process of reading or skipping each pixel signal Sn redundantly is performed. It is not sufficient to perform the processing for each pixel at equal intervals by the 1x direction processor 6 alone. Assuming that only the first x-direction processor 6 is used for the x-direction,
For example, if the parameter P1 is “+6”, “+7”, “−
In the case of “6” and “−7”, the number of pixels after the enlargement in the x direction is 597, 585, 448, and 456, and an intermediate value of these numerical values cannot be selected. Can not.

Therefore, in the image scaling device 1, a second x-direction processor 7 having substantially the same function as the first x-direction processor 6 is provided in parallel with the first x-direction processor 6.
The second x-direction processor 7 is also configured to hold the count value K and perform a thinning process.

For example, when it is desired to enlarge the pixel from 512 pixels to 600 pixels by approximately 1.17 times, as shown in FIG. 5, the parameters P1 and P2 are “+6”,
Set “+170”. Then, the registers 6a and 7a of the first and second x-direction processors 6 and 7 have the register values R1 and R2 as "+6" and "+170", respectively.
Is stored.

Here, as a common matter in the case of the enlargement processing and the case of the reduction processing, when the enlargement instruction signal x1 or the reduction output signal x1 'of the first x-direction processor 6 changes to "High", the second x The x-direction counter 7b of the direction processor 7 is set so as not to increase at the next pixel clock _DCLK . For example, in the case of the above enlargement processing, FIG.
As shown in FIG. 7, when K1 is 6 and K2 is 6, the enlargement instruction signal x1 is "High". At the next D _CLK , K1 is 0
, But K2 remains at 6.

Similarly, when the enlargement instruction signal x2 and the reduction instruction signal x2 'of the second x-direction processor 7 change to "High", the x-direction counter 6b of the first x-direction processor 6 outputs the next pixel clock D _CLK. Is set to not increase. For example, in the case of the above enlargement processing, as shown in FIG. 5, when K1 is 4 and K2 is 170, the enlargement instruction signal x2 is "High". At the next D _CLK , K2 is 0
, But K1 remains at 4.

It is to be noted that both of the two enlargement instruction signals x1 and x2 or the reduction instruction signals x1 'and x2'
When both are changed to "High", the enlargement and reduction of the pixels are continuously performed as described below. That is, in the example of the above-described enlargement processing, K1
And K2 are: K1 = ..., 5, 6, 0, 0, 1, 2,
3, ... K2 = ..., 169,170,170,0,1,2,
3, ... In this case, first, when K1 becomes 6, the enlargement instruction signal x1 and the reduction instruction signal x1 'become "High", and the first x-direction processor 6 performs the enlargement or reduction processing. Then, in the next pixel clock _DCLK , K2
Remain unchanged, the enlargement instruction signal x2 and the reduction instruction signal x2 'remain "High", and the second x-direction processor 7 performs the enlargement or reduction processing. At this time, K1 has been cleared to zero. In the next pixel clock _DCLK , K1 remains unchanged because it remains unchanged, and K2 is cleared to zero, so that K1 and K2 both become zero. In this way, enlargement and reduction of pixels are performed continuously.

When the above enlargement process is performed in this manner, the number of pixels increased by the first x-direction processor 6 becomes 85 by the calculation of 512 = 6 × 85 + 2. In addition, the number of pixels increased by the second x-direction processor 7 becomes three by the calculation of 512 = 170 × 3 + 2. Therefore, the number of pixels after the enlargement is 512 + 85 + 3 = 600 (pixels), and an image signal S 'representing an image enlarged to approximately 1.17 times and having 600 pixels in the x direction can be obtained.
In other words, with the first x-direction processor 6 alone, 5
97 pixels, which cannot be exactly 600 pixels as desired, but here, since the number of pixels is increased by 3 using the second x-direction processor 7, the desired 6 pixels are obtained.
It can be enlarged to 00 pixels.

In addition, the number of pixels is approximately one, from 512 pixels to 400 pixels.
If you want to reduce by /1.28 times, not shown,
As parameters P1 and P2, "-3" and "-"
49 ". Then, -P1 + 2 is 3+
Since 2,49 + 2, the number of pixels reduced by the first x-direction processor 6 is 102 by the calculation of 512 = (3 + 2) × 102 + 2, and the number of pixels reduced by the second x-direction processor 7 is 512 = (49 + 2) × It becomes 10 by the calculation of 10 + 12. Therefore, the number of pixels after reduction is 512-102-10 = 400 (pixels), and an image signal S ′ representing an image reduced to approximately 1 / 1.28 times having 400 pixels in the x direction can be obtained. it can.

As described above, by providing the two x-direction processors, that is, the first x-direction processor 6 and the second x-direction processor 7, it is possible to obtain an output image of almost a desired size.

By increasing the number of x-direction processors, it is possible to set finer scaling sizes.

Also, the scaling in the y direction is basically the same as that in the x direction.
In the same manner as in the case of the direction, the parameters P3 and P4 are supplied from the host processor 5 to the first and second y-direction processors 8 and 9, so that the scaling operation in the y-direction is performed. However, in the case of the x direction,
Although the count value of each x-direction counter is increased in synchronization with the pixel clock _DCLK , in the case of the y-direction, when the horizontal synchronization signal H _SYNC changes from “Low” to “High”, each y-direction counter is increased. And the vertical synchronization signal V _SYNC signal is used instead of the horizontal synchronization signal H _SYNC .

In the case of the enlargement process, as shown in FIG. 6, if the value of the parameter P3 is, for example, "+3", "+3" is stored as the register value R3 of the register 8a. Enlargement instruction signal y1 of first y-direction processor 8
Is changed from “Low” to “High”, the address generation circuit 3 returns (subtracts) the read address by the number of pixels of one line from the current read address of the image memory 2. As a result, the pixels for one line output immediately before are repeatedly output.

In the case of the reduction processing, the read address is advanced (added) by the number of pixels of one line from the current read address of the image memory 2. Thus, one line of pixels is thinned out and output.

Although not shown, the first y-direction processor 8 and the second y-direction processor 9 can perform enlargement / reduction at an arbitrary enlargement / reduction magnification by the same calculation as in the x direction.

In this manner, enlargement / reduction in the y direction can be realized.

For example, when a video signal typified by NTSC or the like is input, the number of pixels in the horizontal direction is increased by 3/4 or the number of pixels in the vertical direction is increased without using a large-capacity register or the like. By making it 4/3 times, an image without distortion can be obtained.

Embodiment 2 Another embodiment of the present invention will be described below with reference to FIGS. 7 to 10. Note that, for convenience of description, a configuration having the same function as the configuration shown in the drawings of the first embodiment includes:
The same reference numerals are added, and the description is omitted.

As shown in FIG. 7, the image enlargement / reduction device 30 according to the present embodiment has substantially the same configuration as the image enlargement / reduction device 1 according to the first embodiment. However,
The image scaling device 30 according to the present embodiment differs from the image scaling device 1 according to the first embodiment in that a buffer memory 10 is provided on the output side of the image memory 2.

In the present embodiment, an interpolation instruction signal (not shown) is sent to the host processor 5 based on a command from the user.
Are input to the image memory 2, the address generation circuit 3, the timing generation processor 4, and the buffer memory 10. The interpolation instruction signal is a signal indicating whether or not to perform interpolation when performing enlargement processing. It has nothing to do with the reduction process.

When an instruction not to perform interpolation is issued, the same result as in the first embodiment is obtained. That is, as described in the first embodiment, the x-direction / y-direction processor and the address generation circuit 3 perform the overlap reading or the skip reading at the time of output from the image memory 2 to enlarge or reduce. In this case, the buffer memory 10 outputs the input image signal as it is.

On the other hand, when an instruction to perform interpolation is issued, unlike Embodiment 1, the image signal is read from the image memory 2 at the timing of the pixel clock _DCLK without performing the overlapped readout or the skipped readout. Is input to the buffer memory 10 as it is. Then, as described later, the x-direction / y-direction processor and the address generation circuit 3
Thus, at the time of output from the buffer memory 10, enlargement processing is performed while performing interpolation.

Instead of inputting the interpolation instruction signal,
In the present embodiment, it may be set so that interpolation is always performed at the time of enlargement processing.

Next, the internal configuration of the buffer memory 10 will be described. As shown in FIG. 8, the buffer memory 10 includes a line memory 11 having a capacity of at least one horizontal pixel of the original image, flip-flops 12 and 13 for delaying one pixel each, and a coefficient selection processor 14. , An operation logic (density value setting unit) 15.

The operation logic 15 includes multiplexers A, B, C, and D, adders 20a to 20c, and a multiplier 21.
a to 21d.

The basic mechanism of scaling is described in Embodiment 1.
The description is omitted here. Next, an enlargement process involving interpolation will be described. Embodiment 1
In the above, the enlarged image signal S 'is obtained by repeatedly reading the value of the existing pixel signal Sn. On the other hand, in the present embodiment, the density value (gradation) of a pixel (insertion pixel) inserted for enlargement processing is changed to a pixel that is a pixel (peripheral pixel) existing around the insertion pixel. An image signal S ″ after the enlargement process is calculated based on the density values of the pixel signals to obtain the image signal S ″ after the enlarging process. The values are represented using Sn, Sm ', and Sm ", respectively.

First, the image signal S read into the image memory 2 is directly input to the buffer memory 10 as an image signal S '. When interpolation is performed as in the present embodiment, the enlargement processing has not been performed yet at the time of output from the image memory 2 as described above, and the image signal S ′ output from the image memory 2 is Are the same as the image signal S input to

In the buffer memory 10, the image signal S 'from the image memory 2 and the first and second x-direction processors 6,
7. Enlargement instruction signals x1, x2, y1, y2 from the first and second y-direction processors 8, 9 and a filter coefficient signal Q, described later, from the host processor 5 are input.

The image signal S ′ is supplied to the multiplier 21 a in the buffer memory 10 by the line memory 11 and the flip-flop 12.
And given through. The image signal S ′ is supplied to the multiplier 21 b via the line memory 11. Multiplier 2
1c is supplied with the image signal S 'via the flip-flop 13. The image signal S 'is directly supplied to the multiplier 21d. The pixel signals given to the multipliers 21a, 21b, 21c, and 21d in this manner are Sα, Sβ, Sγ, and Sδ, respectively. In the calculation described later, each pixel signal Sα, Sβ, S
The density values of γ and Sδ are represented by Sα and S, respectively.
It is represented using β, Sγ, and Sδ.

The content of the pixel signal Sγ is a pixel signal one pixel ahead of the pixel signal Sδ due to the operation of the flip-flop 13. Further, the pixel signals Sα and Sβ
Are the pixel signals one line ahead of the pixel signals Sγ and Sδ by the operation of the line memory 11 and the flip-flop 12, respectively. FIG. 9 shows how the pixel signals Sα, Sβ, Sγ, and Sδ are represented in association with the positions on the screen before the enlargement processing. Each pixel signal S
α, Sβ, Sγ, and Sδ just represent the pixel signals on the screen shown in FIG.

On the other hand, the filter coefficient signal Q is input from the host processor 5 to the coefficient selection processor 14 based on the above-mentioned interpolation instruction signal. As shown in Table 1, the filter coefficient signal Q is made up of a set of expansion instruction signals x1, x2, y1, and y2 and a combination of coefficient signals KA, KB, KC, and KD output from multiplexers A to D, respectively. ing.

[0094]

[Table 1]

In Table 1, as shown in FIG. 10, one or two pixels in the x direction and the y direction between the pixels with respect to the four pixel signals a _{0 to} d ₀ in the original image, respectively. Is inserted into each of the pixel signals e ₁ to
e ₁₅ . FIG. 10A shows a case where one pixel is inserted in the x direction. FIG. 10B shows a case where one pixel is inserted in the y direction. FIG. 10C shows a case where one pixel is inserted in each of the x direction and the y direction. FIG.
(D) is a case where two pixels are inserted in the x direction. FIG.
0 (e) is a case where two pixels are inserted in the y direction. FIG. 10F shows a case where two pixels are inserted in the x direction and one pixel is inserted in the y direction. FIG. 10G shows a case where one pixel is inserted in the x direction and two pixels are inserted in the y direction. FIG.
(H) is a case where two pixels are inserted in each of the x direction and the y direction.

When two or more pixels are inserted, the values of each row of coefficients described in two or more rows in the coefficient column of Table 1 are used for each inserted pixel described later.

In Table 1, the enlargement instruction signal x1,
When x2, y1, and y2 are all 0, no enlargement or reduction is performed. Therefore, the pixel signal Sm '(= Sn) at that time is directly given as the pixel signal Sm ". At this time, the coefficient KD is 1, and KA, K
B and KC are all 0, and the pixel signal Sm ″ is
1d, that is, the pixel signal Sm ′, that is, the pixel signal Sδ
It is formed only from.

As shown in Table 1, the coefficients KA, K
B, KC, and KD are all equal to or greater than 0 and equal to or less than 1, and are set to be 1 when all four are added. These coefficients represent the magnitude of the weight of each peripheral pixel in the interpolation calculation described later. For example, the pixel signal e ₁₂ of the insertion pixel, the largest KA. That is, the pixel signal Sα
Is the largest. On the other hand, in the pixel signal e ₁₃ of the insertion pixel, the largest KB. That is, the weight of the pixel signal Sβ is the largest.

As shown in FIG. 8, the filter coefficient signal Q is input as described above, and the host processor 5 and the x-direction and y-direction processors send the enlargement instruction signals x1, x2, y1, y2
Are constantly input in synchronization with the pixel clock _DCLK .

Then, the coefficient selection processor 14 detects the levels of the input enlargement instruction signals x1, x2, y1, and y2, and uses the filter coefficient signal Q to determine what line in the coefficient column shown in Table 1 Are the expansion instruction signals x1, x2, y
It is determined whether or not the set corresponds to a set of 1, y2 levels. In addition,
As described above, for example, (x1, x2, y1, y2) =
As in the case of (1,1,0,0), a plurality of rows may be applicable.

After determining the row in Table 1, the coefficient selection processor 14 selects the coefficients KA to KD according to Table 1.
Then, the selected coefficients are used as selection signals T1, T2, T
3 and T4 as multiplexers A, B, C and D, respectively.
Output to As described above, one multiplexer may have two or more coefficients.

The multiplexers A, B, C and D respectively apply the coefficients given as the selection signals T1 to T4 from the coefficient selection processor 14 to the other input terminals of the multipliers 21a, 21b, 21c and 21d by the coefficients KA , KB, K
Output as C and KD. If the coefficient is 2
If there are more than one, they are sequentially output in synchronization with the pixel clock _DCLK .

Each of the multipliers 21a, 21b, 21c, 21d
Performs multiplication, respectively, KA · Sα, KB
Outputs pixel signals having density values of Sβ, KC · Sγ, and KD · Sδ.

These values are added by adders 20a to 20c.

Therefore, each pixel signal S finally obtained is
The density value of m ″ is as follows: Sm ″ = KA · Sα + KB · Sβ + KC · Sγ + KD · Sδ (1)

For example, the first x-direction scaling parameter P
Considering a case where 1 is +5 and all other parameters are 0, as described in the first embodiment, the count value K1 of the first x-direction processor 6 is K1 = 0, 1, 2, 3 , 4, 5, 0, 1, 2, 3,... At this time, the count value K of the address generation circuit 3
Are K = 0, 1, 2, 3, 4, 5, 5, 6, 7, 8,... (See FIG. 3).

In this case, when K = 0 to 4, the level of the enlargement instruction signal x1 is "Low"("0"). Therefore, the pixel signals S0 "to S4" are directly output as the pixel signals Sm "based on the read address indicated by the counter value K.

When one clock period elapses from K = 4 and K = 5, the level of the enlargement instruction signal x1 is "High"("1"). For this reason, as the pixel signal Sm ″, the pixel signal S5 ″ (= based on the current read address (K = 5) is obtained from the second row of Table 1.
Sm) = e ₁ = 0 · Sα + 0 · Sm ″ = e ₁ = 0 · Sα + 0 · Sβ + (1/2) Sγ +
(1/2) Sδ.

When one clock period has elapsed therefrom, K = 5 is still held. The level of the enlargement instruction signal x1 is “Low” (“0”). Therefore, the pixel signal S5 "is output as it is based on the read address (K = 5) indicated by the counter value K as the pixel signal Sm".

As described above, the buffer memory 10 replaces the image signal S 'with the image signal S "obtained by performing the enlargement processing while interpolating by calculation, and outputs it.

Here, as described above, the coefficients KA, KB,
KC and KD are all equal to or greater than 0 and equal to or less than 1, and are set to be 1 when the four are added together. For this reason, the density value Sm ″ of the inserted pixel inserted by the above interpolation is the density value Sα, Sβ, Sγ,
Sδ is equal to or more than the minimum value and equal to or less than the maximum value. In particular, among the density values Sα, Sβ, and Sγ, there is a density value whose corresponding coefficient is not 0 among KA and KC, in other words, a value different from the density value Sδ exists as a density value substantially used for interpolation calculation. In this case, the density value Sm ″ of the insertion pixel
Is a value exceeding the minimum value and less than the maximum value among those density values substantially used in the interpolation calculation including the density value Sδ. As a result, from a peripheral pixel having a small density value to a peripheral pixel having a large density value, it is possible to obtain an enlarged image in which the density value, that is, the gradation, is gradually changing via the insertion pixel.

As described above, in the image enlarging / reducing device 30 according to the present embodiment, the density values of the pixels of the original image are used as they are as the density values of the pixels inserted between the pixels of the original image at the time of enlargement. Instead, an interpolation process is performed in which weights are added to the densities of the pixels of the surrounding original image and then added. This makes it possible to smoothly change the gradation between the pixels of the enlarged image and improve the image quality of the enlarged image.

On the other hand, in the configuration according to the first embodiment, since the buffer memory 10 is not provided, an increase in the manufacturing cost of the apparatus can be suppressed. These two configurations are:
The user may use the method according to which of the manufacturing cost and the image quality is more important.

As shown in Table 1, the pattern at the time of enlargement is limited. That is, based on the combination of the enlargement instruction signals, the weighting of the density value and the pattern of the calculation formula for each of the original pixels serving as the peripheral pixels are uniquely determined. For this reason, it is possible to suppress the processing capacity and the burden on the storage device by performing this calculation.

[0115]

As described above, according to the image enlarging / reducing apparatus according to the first aspect, the read address of the image signal from the image memory for storing the image signal displayed on the screen having the main scanning direction and the sub-scanning direction is provided. Every time the address generation unit advances by a predetermined number in synchronization with the read clock, the increase in the read address is temporarily stopped for the enlargement in the main scanning direction, and The read address is returned by one horizontal blanking, and the image is enlarged by inserting an insertion pixel into the image signal. On the other hand, in response to a reduction processing request, the image is read by increasing the increment of the read address and skipping the image signal. In the image enlargement / reduction device for reducing the size, two or more different cycles which are integral multiples of the read clock and indicate the timing of the enlargement / reduction processing are determined. A control unit for a configuration and a timing generation unit for setting the scaling processing timing based on the cycle.

Therefore, there is an effect that the image can be enlarged / reduced at an arbitrary magnification / reduction ratio including the fraction ratio with a simple configuration.

According to a second aspect of the present invention, in addition to the configuration of the first aspect, the address generation unit stops increasing the read address as the insertion pixel for the enlargement in the main scanning direction. In the configuration, the image signal indicated by the read address when the read address is inserted is inserted, and the image signal indicated by the read address when the read address returns by one horizontal retrace is inserted for enlargement in the sub-scanning direction. is there.

Therefore, there is an effect that the image can be enlarged / reduced at an arbitrary magnification / reduction ratio including the fraction ratio with a simpler configuration.

According to a third aspect of the present invention, in addition to the configuration of the first aspect, the control unit issues an interpolation instruction indicating whether or not to interpolate the density value of the inserted pixel during the enlargement processing. A line memory for storing density values of a plurality of peripheral pixels located around the inserted pixel on the screen after insertion in response to the enlargement processing request and the interpolation instruction; and When a pixel is inserted, the density values of the peripheral pixels are added together while adding weights in accordance with the interpolation instruction, so that the density value of the peripheral pixel is calculated as the density value of the inserted pixel. A density value setting unit for setting a value exceeding the minimum density value and less than the maximum density value.

Therefore, in addition to the effect of the first aspect, it is possible to smoothly change the gradation between the pixels of the enlarged image and to reduce the deterioration of the image quality of the enlarged image. .

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an image scaling device according to an embodiment of the present invention.

FIG. 2 is a timing chart showing addresses of various signals input to the image enlargement / reduction device of FIG. 1 and pixel signals output when no enlargement / reduction is performed.

FIG. 3 is a timing chart showing an operation of the first x-direction processor when “+5” is set in a register of the first x-direction processor.

FIG. 4 is a timing chart showing an operation of the first x-direction processor when “−5” is set in a register of the first x-direction processor.

FIG. 5 shows “+5” in a register of the first x-direction processor.
7 is a timing chart showing the operation of each x-direction processor in the x-direction when "+170" is set in the register of the second x-direction processor.

FIG. 6 is a timing chart showing an operation of the first y-direction processor when “+3” is set in a register of the first y-direction processor.

FIG. 7 is a block diagram showing a configuration of an image scaling device according to another embodiment of the present invention.

8 is a block diagram showing an internal configuration of the buffer memory shown in FIG.

FIG. 9 is an explanatory diagram showing a positional relationship between pixel signals provided to each multiplier shown in FIG. 8;

FIG. 10 is an explanatory diagram showing types of each pixel signal when one or two pixels are inserted between pixels with respect to a pixel signal of an original image.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 image enlargement / reduction device 2 image memory 3 address generation circuit (address generation unit) 4 timing generation processor (timing generation unit) 5 host processor (control unit) 6 first x-direction processor 7 second x-direction processor 8 first y-direction processor 9 2y direction processor 10 buffer memory 11 line memory 12 flip-flop 13 flip-flop 14 coefficient selection processor 15 arithmetic logic (density value setting unit) 20a-20c adder 21a-21d multiplier 30 image enlargement / reduction device A multiplexer B multiplexer C multiplexer D Multiplexer

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code FI H04N 5/66 H04N 5/66 B

Claims (3)

[Claims] 1. A readout address of an image signal from an image memory which stores an image signal displayed on a screen having a main scanning direction and a sub-scanning direction is advanced by a predetermined number by an address generator in synchronization with a read clock. In response to the enlargement processing request, the increase of the read address is temporarily stopped for the enlargement in the main scanning direction, and the read address is returned by one horizontal retrace for the enlargement in the sub-scan direction, and the inserted pixel is added to the image signal. In an image enlargement / reduction apparatus for enlarging an image by inserting it and increasing the read address increment in accordance with a reduction processing request and skipping an image signal to reduce the image, A control unit for determining two or more different cycles that are integral multiples of the read clock; and Image scaling apparatus characterized by and a timing generation unit for setting a processing timing. 2. The image processing apparatus according to claim 1, wherein the address generation unit inserts, as the insertion pixel, an image signal indicated by the read address when the increase of the read address is stopped for enlargement in the main scanning direction. 2. The image enlargement / reduction apparatus according to claim 1, wherein an image signal indicated by the read address when the read address returns by one horizontal retrace is inserted for enlargement in the direction. 3. The control section issues an interpolation instruction indicating whether or not to interpolate the density value of an inserted pixel at the time of enlargement processing, and responds to the enlargement processing request and the interpolation instruction to display on the screen after insertion. And a line memory for storing density values of a plurality of peripheral pixels located around the insertion pixel, and, when inserting the insertion pixel in response to the enlargement processing request, the peripheral pixel By adding the density values having
2. The image processing apparatus according to claim 1, further comprising: a density value setting unit configured to set a value exceeding the minimum density value and less than the maximum density value among the density values of the peripheral pixels as the density value of the insertion pixel. Image scaling device.