JPH032314B2 - - Google Patents

Description

[Detailed description of the invention] 〔table of contents〕 The present invention will be explained in the following order.

A. Summary of the invention B. Field of industrial application C. Prior art (Fig. 7) D. Problem to be solved by the invention E. Means for solving the problem F. Effect (Fig. 1) G. Example (Fig. 1) Figure) Explanation of _G1 multi-window control unit (Figure 3) Explanation of _G2 address window detection circuit (Figure 4)
(Figure) G ₃ Explanation of the relationship of addresses in partial images of the screen image developed on the window buffer (Figure 5) G ₄ Explanation of the address conversion circuit (Figure 6) H Effect of the invention Overview] A multi-window display control device calculates a partial image to be displayed in the window on the display screen from the screen image developed on the window buffer.
The processing speed is increased by reading the data in synchronization with the display timing of the display device and controlling the overlapping of a plurality of windows on the display screen using hardware.

[Industrial application field]

The present invention relates to a multi-window display control device for a display system such as a CRT or a printer that displays dots.

[Conventional technology]

High-performance display devices such as workstations are required to have a multi-window display function that simultaneously displays a plurality of screen images by dividing or superimposing the screens on one display device (for example, a CRT). The conventional method requires a frame buffer for accumulating display screen images on a CRT, which is a multi-window display screen composed of a plurality of screen images, and a window buffer for accumulating a plurality of screen images. Transfer all or part of the multiple screen images developed on the window buffer to the frame buffer, and transfer the display screen image that looks like multiple windows by overlapping the multiple screen images to the frame buffer. Create on the forum. The display screen image on the frame buffer is read out in synchronization with the raster scanning of the CRT, and a multi-window screen is displayed on the CRT. Several methods have been proposed for realizing these functions, depending on the differences in the arrangement of frame buffers and window buffers. However, as mentioned earlier, it has a window buffer that develops multiple screen images as dots and a frame buffer that develops a multi-window display screen image that appears to have multiple windows. Logically, it is possible to create a multi-window display screen image by transferring the whole or part of the screen image developed on the frame buffer to the frame buffer, and then reading out the image in synchronization with the raster scanning of the CRT. can all be considered to be the same method. FIG. 7 is a diagram showing an embodiment of the conventional method, in which 1 is a window buffer 11, 12, 13 for developing a screen image, each screen image, 111, 121, 131 is a partial image of the screen image, 2 is a frame buffer, 112, 122, 132 are partial images 1
A partial display image created by transferring 11, 121, and 131 to the frame buffer 2, 3 is the CRT synchronization signal generation circuit CRTC, 31 is the access control signal line of the frame buffer 2, 32 is the CRT synchronization signal line, 4 is the hardware for transferring the image from the window buffer 1 to the frame buffer 2, and 5 is the hardware for transferring the image from the window buffer 1 to the frame buffer 2.
On CRT, 51 is the CRT display screen, 115, 12
5,135 is a partial display image displayed on the CRT on the frame buffer, which is a window.

Here, the following processing is required to generate a multi-window display screen image based on the screen image developed on the window buffer 1.

In each screen image 11, 12, 13
Partial images 111, 121, 1 as images in the window displayed on the CRT display screen
Define 31.

Specify the position of the window on the display screen corresponding to the partial images 111, 121, 131 and the overlapping state of the windows, transfer the partial images 111, 121, 131 to the frame buffer 2, and display the multi-window display screen. create.

After modifying the screen image, transfer hardware transfers the partial image 121 on the frame buffer to an area of the frame buffer 2 where a partial display image 122 corresponding to the position of the window 125 on the screen is placed. Transfer with 4. Next, the partial image 131 corresponding to the window 135 overlapping the window 125 is transferred to the window buffer 1.
from there to frame buffer 2. Further, the partial image 111 corresponding to the window 115 overlapping the window 135 is transferred to the frame buffer 2. This completes the updating of the display screen image. Alternatively, the shape of the partial display image in which the partial images 111 and 131 appear to overlap on the partial image 121 can be changed to the window 115, 125, 13.
5. Obtain from data that defines the relationship between the position, size, and weight on each display screen. The shape of the obtained partial display image 122 is converted into partial image 12
1 and transferred to the position of the partial display image 122 in the frame buffer 2.

To execute the above operation, it takes the image transfer time _t from frame buffer 1 to frame buffer 2, and the time required to transfer the image from frame buffer 1 to frame buffer 2.
It takes time t _n to manage the position, size, weight relationship, etc. of the partial images in the image. Image transfer time is slow even when performed on hardware.
Approximately 40 to 100mS/screen is required. If one screen image is composed of multiple planes for the purpose of color display, and multiple windows overlap, it will take a very long time to update the display screen. For example, when one screen consists of four planes and 10 windows overlap, the update time of the display screen when rewriting the image of the window located at the lowest position is 1.6 to 4.0 seconds.

In addition, to create a display screen image in which multiple windows overlap, use Window Buffer 1.
Manages information such as the position and size of the screen image expanded on the screen image, the position and size of partial images within the screen image, the position of the partial display image expanded on the frame buffer 2, and the degree of overlap between the partial display images. There is a need to. When updating the display screen, it is necessary to control the transfer of image data from the window buffer to the frame buffer based on the above information. For this reason, workstations and the like are usually equipped with a dedicated processor for controlling the display device in order to avoid deterioration in the performance of other business processes. Further, in order to transfer image data between the window buffer 1 and the frame buffer 2 at high speed, dedicated hardware such as a "bit block transfer" is required.

[Problem that the invention seeks to solve]

As mentioned above, in the conventional method, when updating a multi-window display screen due to the creation or drawing of a new screen, or screen operations such as scrolling, moving, enlarging, or reducing a certain window, it takes a long time. It takes time, and on the other hand, the process becomes complicated because a lot of information accompanying the screen is to be managed. Therefore, there are drawbacks such as the need for a large amount of hardware such as a processor dedicated to display control and hardware for transferring image data between the window buffer and frame buffer.

[Means for solving problems]

The present invention solves the above problems,
In a multi-window display system that has a window buffer that stores multiple screen images expanded into dots in order to simultaneously display multiple screen images on one display device such as a CRT or a printer that displays dots, The partial image to be displayed in the window on the display screen is read out from the screen image developed on the screen in synchronization with the display timing of the display device such as CRT,
To perform overlapping control between a plurality of windows on a display screen by hardware.

[Effect]

To explain the operation of the present invention in comparison with the conventional system, in the conventional system shown in FIG. By sequentially reading the contents of the frame buffer using the frame buffer address (X, Y) generated in synchronization with the raster scan of the CRT.
A screen display is made on the CRT.

On the other hand, in the present invention, as shown in FIG.
Y) is notified to the multi-window control unit MWU6 via the access signal line 31, and the MWU6 converts it into an address on the actual window buffer 1 according to the screen address data, and further converts the address between multiple windows on the display screen. The superimposition control of the images is performed by hardware. Then, the contents of the window buffer specified by the address selected by the hardware are read out and displayed on a CRT or the like.

〔Example〕

FIG. 1 shows an embodiment of the present invention, and 6 is a CRT.
In synchronization with the raster scanning timing corresponding to the area where the window is placed on the display screen, generate the address of the window buffer in which the image to be displayed in the window is stored, and read the contents of the address. , a hardware multi-window control unit MWU that performs overlapping control between multiple windows; 61 is a window buffer access signal line consisting of an address signal line and a control signal line for accessing the window buffer 1 from the MWU; 7 is the output signal line of the wind buffer.

Figure 2 shows an example of a display screen on a CRT.
51 is the display screen of the CRT shown in FIG. 7 and FIG. 1; 52 is each dot composing the display screen;
3 is a window on the display screen, 54 is a dot at the first vertex of the window 53, and its coordinate values are (X ₁ , Y ₁ ), and 55 is a dot at the second vertex, whose coordinate values are (X 1 , Y 1 ). ₂ , _Y2 ).

CRTC3 is the frame buffer access signal.
Generates CRT synchronization signal and signal lines 31 and 32
MWU6 and CRT5 are notified respectively.
The frame buffer access screen is synchronized with the raster scan of the CRT, and the frame buffer address (X,
Y). In the conventional system, dots are arranged on the frame buffer to be sequentially displayed on the display screen 51 in the order of raster scanning on the CRT.
By sequentially reading out the contents of the frame buffer using the generated frame buffer address (X, Y) in synchronization with the CRT's raster scan, the CRT
A screen display appears above. In contrast, in the present invention, the frame buffer is not accessed directly using the frame buffer address (X, Y) generated by CRTC3. The address (X, Y) is notified to the MWU 6 via the access signal line 31.

The following data regarding the screen is set in MWU6.

Data regarding the screen image above the window buffer 1, including the position and size of the screen image within the window buffer 1 Data regarding the partial image cut out within the screen image, including the position of the partial image within the screen image and size Data related to the window that displayed the partial image on the CRT, the position of the window within the display screen (on the CRT) Data that defines the weight relationship between windows on the CRT display screen Screen images 11, 12, 13 The above data related to (hereinafter referred to as screen address data) are set in the MWU6. CRTC3
The frame buffer address (X,
Y) is converted into an address on the actual window buffer 1 in the MWU 6 according to the screen address data. Assuming that the starting position of raster scanning on a CRT is the upper left point of the display screen, in the example shown in Figure 1, there is no partial image to be displayed at the raster scanning starting point at the upper left of the display screen, so a predetermined background pattern is displayed. . As scanning progresses, the frame buffer address (X, Y) corresponding to the position where window 115 should be displayed is received from CRTC3.
MWU6 will be notified. The MWU 6 uses the screen address data to convert the frame buffer address (X, Y) into an address on the window buffer where the partial image 111 of the screen image 11 developed on the window buffer 1 is located. do. Then, the address is notified to the window buffer 1 via the signal line 61. The frame buffer address (X, Y) corresponding to the position where the scan progresses further and windows 115 and 125 overlap
is notified from CRTC3 to MWU6. MWU6
converts the frame buffer address (X, Y) using the screen address data into an address on the window buffer where the partial image 111 in the screen image 11 developed in the window buffer 1 is located. At the same time, conversion is performed to an address on the window buffer where the partial image 121 in the screen image 12 is located.

The MWU 6 uses data representing the weight relationship between windows in the screen address data that has been set, and selects one of the addresses on the two window buffers 1 generated by the simultaneous conversion processing. Select and notify Wind Buffer 1. In the example of FIG. 1, the window 115 overlaps the window 125, so the MWU 6 selects the address on the window buffer 1 where the partial image 111 is located, notifies the window buffer 1, and Read the area data,
Display on CRT.

Thereafter, a plurality of partial images can be displayed on one CRT while displaying the partial images 131 of the screen image 13 and controlling the weight between windows in the same manner.

In the above explanation, for simplicity, the number of screen images is set to three, but even if this number is larger, multi-window display can be performed using the same method. Also, 1
Although an example has been described in which only one partial image is cut out from one screen image, it is also possible to simultaneously cut out a plurality of partial images from one screen image in order to generate a plurality of windows from one screen image.

[Description of multi-window control unit]

Figure 3 shows the multi-window control unit MWU6.
In this specific example, 311 is an x coordinate signal line indicating the coordinate value in the horizontal direction (referred to as the x direction) of the display screen on the CRT, and 312 is the coordinate value in the vertical direction (referred to as the y direction). In the y coordinate signal line shown, 31
3 is the sample timing signal of the display dot.
611, 612, 613, 614 are display clock signal lines for CRTC3 to notify each control circuit.
are two points (X ₁ , Y ₁ ) and (X ₂ ,
Y ₂ ) is set, and signal lines 311 and 312
Two-dimensional coordinates (X, Y) on the current display screen synchronized with the raster scanning of the CRT, represented by (hereinafter referred to as frame buffer address)
621, 622, 623, 62 in the address window detection circuit AWC, which compares the value set previously and detects that the frame buffer address (X, Y) exists within the window on the display screen.
4 is an address conversion circuit that indicates that the frame buffer address (X, Y) exists within the window defined by (X ₁ , Y ₁ ) and (X ₂ , Y ₂ ) set in the circuit AWC. 651, 652, 653,
654 is the window detection signal line 621, 622, 6
23 and 624 respectively, and the address conversion circuit ATC generates the address of the partial image developed on the window buffer.
672, 673, 674 are address conversion circuits
ACT651, 652, 653, 654 are address signal lines that notify the addresses on the window buffer that are output respectively, and 68 is the address signal line 6.
This is a multiplexer circuit that selects one of 71, 672, 673, and 674 depending on the relationship of overlapping windows on the display screen.

To operate this, screen address data is set in each of the circuits described above in advance. Specifically, the position and size of the screen image within the window buffer, and the position and size of the partial image within the screen image are set in the address conversion circuits ATC651, 652, 653, and 654 for each two data screen images. do.

The address window detection circuit AWC611 detects the position of the window within the display screen on the CRT.
612, 613 and 614, respectively.

The overlapping relationship between the windows on the display screen is set in the multiplexer circuit 68.

For example, screen address data regarding screen image 11 is set in address window detection circuit 611 and address conversion circuit 651, and screen address data regarding screen images 12 and 13 is similarly set in address window detection circuit 612, 613 and address conversion circuit 652, 653 respectively.

Further, data defining the overlapping relationship on the display screen of windows displaying the contents of the three screen images is set in the multiplexer circuit 68.

The frame buffer address (X, Y) generated by CRTC3 is synchronized with the raster scan of the CRT.
Addresses of points to the right from the upper left point on the display screen are sequentially displayed. As the raster scan progresses, addresses (X ₁ , Y ₁ ) and (X ₂ ,
When it is detected that the frame buffer address (X, Y) has entered the range of _Y2 ), the window detection signal line 621 is connected to the address conversion circuit ATC6.
51 is activated to perform address translation. The address conversion circuit ATC 651 generates the address of the partial image 111 in the screen image 11 on the window buffer. Data representing the address is notified to multiplexer circuit 68 via address signal line 671. The multiplexer circuit 68 has window detection signal lines 621 and 62.
2, 623, and 624 are connected, it corresponds to the contents of the uppermost window according to the data notified by the signal line and the data that determines the relationship between the overlapping windows on the display screen. A signal line that notifies the address of the partial image to be processed is selected and connected to the signal line 61. The signal line 62 carries data corresponding to the identifier of the partial image selected by the multiplexer circuit 68.

As the raster scan further progresses and the CRTC 3 generates a frame buffer address (X, Y) corresponding to the area where windows 115 and 125 overlap on the display screen and 115 is on top,
Address window detection circuits 611 and 612 detect that the frame buffer address (X, Y) is within both windows 115 and 125 on the display screen. As a result, the window detection signal line 62
1 and 622 activate the address translation circuits 651 and 652, respectively, to perform address translation. Address conversion circuit ATC651 and 652
generates the address of partial image 111 in screen image 11 and the address of partial image 121 in screen image 12, respectively. The two addresses are notified to multiplexer circuit 68 via address signal lines 671 and 672. In the multiplexer circuit, the window 115 is 125
Since the address signal line 671 is selected and connected to the signal line 61, the address signal line 671 is selected.
In addition, the selected partial image is displayed on the signal line 62.
Insert data showing that it is 11.

Thereafter, as the raster scan progresses, the same operations as above are performed to read the partial images on the window buffer at the timing corresponding to the dots on the CRT display screen, while simultaneously controlling the overlapping relationship between the windows. Display multiple windows on the display screen.

In the above explanation, for the sake of simplicity, the number of address window detection circuits, address conversion circuits, and signal lines provided corresponding to the number of these circuits is four.
It is also possible to increase the number as necessary.

[Description of address window detection circuit]

FIG _. 4 shows a specific embodiment of the address window detection circuit 611 _{, 612 , 613} or 614 in FIG. These are the coordinate values of (X ₁ , Y ₁ ) and (X ₂ , Y ₂ ), which correspond to the coordinate values of the two vertices 54 and 55 of the window 53 in FIG. X coordinate value of frame buffer address and X ₁
CMP2 is a comparison circuit that compares the X coordinate value of the frame buffer address with _X2 , CMP3 is a comparison circuit that compares the Y coordinate value of the frame buffer address with _Y1 , and CMP4 is a comparison circuit that compares the Y coordinate value of the frame buffer address with Y coordinate value of the frame buffer address and Y ₂
Q ₁ , Q ₂ , Q ₃ and Q ₄ are the comparison circuits CMP1, CMP2, CMP3, CMP.
Output terminals R1, R2, R3, and R4 are reset terminals of the comparator circuit, and when these terminals are turned on, the output terminals _Q1 , _Q2 , _Q3 , and _Q4 are turned off.
D ₁ and D ₂ are two data input terminals of the comparison circuit,
CLK1, CLK2, CLK3, and CLK4 are clock terminals of the comparison circuit, and the values applied to the two data input terminals _D1 and _D2 are compared at the rising edge of the timing pulse applied to the terminals,
Output the result to the output terminal. 6111,61
13 is AND gate, 6112 is OR gate, FF
1 is a flip-flop, CLK5 is the clock terminal of FF1, and signal lines 6114, 6115, 611
6, 6117, 6118 are address detection circuits
This is an output signal line from the AWC and corresponds to the window detection signal line of each address window detection circuit in FIG.

The comparison circuit is activated by the clock on the display clock signal line 313, and the frame buffer address (X, Y) and the coordinate values ((X ₁ , Y ₁ ) and (X ₂ ) of the two vertices of the window on the display screen are activated. , Y ₂ ).Comparison circuit CMP1 compares X and X ₁ , CMP2 compares X and X ₂ , CMP3 compares Y and Y ₁ , and CMP4 compares Y and
Compare Y ₂ . Specifically, the value of terminal D ₁ and terminal D ₂
When D ₂ ≦D ₁ , output terminals Q ₁ , Q ₂ , Q ₃ or Q ₄ of each comparison circuit are turned on. In FIG. 2, the window 53 has two vertices 54 and 5.
5, the comparator circuits CMP2 and CMP
4 actually compares X and X ₂ +1 and Y and Y ₂ +1, respectively.

In the example of FIG. 4, when the output terminals Q ₁ and Q ₃ of the comparison circuits CMP1 and CMP3 are both on, the frame buffer address (X, Y) represents a dot included in the window 53. Therefore, the condition of AND circuit 6111 is satisfied. As a result, flip-flop FF1 is set and its output terminal Q is turned on. Further, as the CRT raster scan progresses, the frame buffer address (X, Y) generated by CRTC3 changes, and when the address (X, Y) indicates outside the window, the output terminal Q of either CMP2 or CMP4 changes. ₂ or Q ₄
is turned on. As a result, the condition of the OR circuit 6112 is satisfied, the flip-flop FF1 is reset, and the output terminal Q of the flip-flop FF1 changes from on to off. In other words, the ON state of the terminal Q of FF1 indicates that the frame buffer address (X, Y) is within the window 53, and conversely, the ON state of the terminal indicates that the frame buffer address (X, Y) is within the window 53. Each represents something that is not present.

The condition for both Q ₂ of CMP2 and Q ₃ of CMP3 to be on is that the value of X of the frame buffer address (X, Y) is X≧X ₂ +1 and the value of Y is Y ₁ ≦Y≦Y ₂ corresponds to the condition. This condition indicates that the Y coordinate value of the frame buffer address (X, Y) is within the vertical region of the window 53, but the X coordinate value is outside the window in the horizontal direction. The situation is
This corresponds to the ON state of the output signal line 6117 of the AND circuit 6113. The state of the signal line 6117 is transmitted to the address conversion circuit 651, which will be described next, when the frame buffer address (X, Y) again indicates the coordinate value of a dot in the window 53. Used to notify that the previous value of Y has been increased by +1.

The signal line 6114 notifies the address conversion circuit ATC to start the address conversion process, the signal line 6115 notifies the address conversion circuit ATC to stop the address conversion process, and the signal line 6116
notifies the address conversion circuit ATC of the address conversion timing for each display dot, and the signal line 6117 notifies that the Y coordinate value of the frame buffer address will be increased by +1 the next time the address conversion circuit is activated. , the signal line 6118 is connected to the address conversion circuit ATC after the scanning of the window in the Y direction is completed.
When activated, it is notified that the Y coordinate value of the frame buffer address has returned to its initial value.

The results of the operation of the address window detection circuit described above are the output signal lines 6114, 6115,
The address conversion circuit ATC 651 is notified by 6116, 6117 and 6118.

[Explanation of the relationship between addresses in partial images in the screen image developed on the window buffer]

FIG. 5 is a diagram for explaining the generation of the address on the window buffer 1 of the partial image 111 in the screen image 11 expanded on the window buffer 1, where (x _s , y _s ) is the screen image This is the two-dimensional coordinate value of the position which is one of the two vertices of No. 11 and serves as the origin. Now, for the sake of simplicity, it is assumed that the window buffer 1 has one-dimensional continuous addresses, and that the two-dimensional screen image is secured in a continuous address area within the window buffer 1. a _s is the two-dimensional coordinate (x _s ,
y _s ) is the actual one-dimensional address on the wind buffer. Similarly, (x ₀ , y ₀ ) are the two-dimensional coordinates of the first vertex of the partial image 111,
(x _o , y _o ) are the two-dimensional coordinates of the second vertex of the partial image, and x _e , y _e ) are the two-dimensional coordinate values of the second vertex of the screen image 11 .

The frame buffer address (X, Y) generated by CRTC3 is displayed as a dot (X ₁ , Y) on the window 53.
When it matches the dot (X ₂ , Y ₂ ) on the window 53, the address conversion circuit ATC generates the address _{a s} of the window buffer 1. The procedure for converting the coordinate values (X, Y) representing a dot into a one-dimensional address a(x _i , y _i ) of the window buffer 1 will be explained below.

x ₋ x _s = _{d s (} dot ₎ …( ₁ ) The one-dimensional address a(x ₀ , y ₀ ) on the window buffer corresponding to ₀ ) can be expressed by equation (3).

a (x ₀ , y ₀ ) = a _s + d _y × (y ₀ − y _s ) + d _x …(3) Similarly, the two-dimensional coordinates of other points in the line containing (x ₀ , y ₀ ) ( The one-dimensional address a(x _i , y ₀ ) on the window buffer of x _i , y ₀ ) can be expressed by equation (4).

a (x _i , y ₀ ) = a _s + d _y × (y ₀ − y _s ) + d _x + i …(4) Find the number of the line containing the point (x ₀ , y ₀ ) or (x _i , y ₀ ). 0, the address a(x _i , y _j ) on the window buffer of the point (x _i , y _j ) on the j-th line can be expressed by equation (5).

a (x _i , y _j ) = a _s + d _y × (y ₀ + j−y _s ) + d _x + i (5) Equation (5) expresses the window of any dot in the partial image by the transformations i and j. Represents a one-dimensional address on a buffer.

Equation (5) can be expressed as Equation (6) from Equations (1) and (2).

a(x _i , y _j )=a _s +(x _e −x _s +1)×(y ₀ −y _s +
j) + (x ₀ - x _s ) + i = a _s + (x _e - x _s + 1) x (y ₀ - y _s ) + (x _e -
x _s + 1) x j + (x ₀ - x _s ) + i...(6) Here, if the address of window buffer 1 is managed two-dimensionally, the address is given by formula (7),
It can be expressed as (8).

a _x = x ₀ + i (7) a _y = y ₀ + j (8) It is very easy to realize the functions of equations (7) and (8) with hardware.

Equation (6) can also be implemented in hardware relatively easily.

[Description of address conversion circuit]

FIG. 6 shows an example of the hardware configuration for realizing the above formula (6), in which the address conversion circuit ATC65 is used.
1 shows details of the first embodiment. The same applies to other address conversion circuits ATC652, 653 and 654.

80 is a counter that generates the value of variable i in the fifth term on the right side of equation (6), and 81 sets the x coordinate value x ₀ of the two-dimensional coordinate value (x ₀ , y ₀ ) of the first vertex of the partial image 111. 82 is a register for setting the negative value of the x coordinate value x _s of the two-dimensional coordinate value (x _s , y _s ) of the first vertex of the screen image 11 , and 83 is a register for setting the negative value of the x coordinate value x _s of the first vertex of the screen image 11 . A register 84 sets the two-dimensional coordinate value (x _e , y _e ) of the two-dimensional coordinate value (x e , y _e ) of the first vertex of the partial image 111 to x _e +1, which is 1 added to the x coordinate value x e A register 85 is the negative value of the y-coordinate value _{y s} of the two-dimensional coordinate value ( _{x s} , y _{s )} of the first vertex of the screen image 11.
Register to set y _s , 86 is screen image 11
registers for setting the one-dimensional address a _s on the window buffer corresponding to the two-dimensional address (x _s , y _s ) of the first vertex of , 87, 88, 89, 90, 9
4, 95 and 96 are adders, 91 is a multiplier,
92 is a register with a gate function that accumulates the output of the adder 90, and 93 is a timing circuit that generates the timing for changing the variable j in the third term on the right side of equation (6).

In the operation of the address conversion circuit ATC shown in FIG.
The values set in and 86 are constants that are independent of the sample timing of display dots generated by CRTC3. Therefore, when a predetermined constant is set in the register, the adders 87, 88, 89, 94
And the multiplier 91 operates independently with respect to the sample timing of the display dot. The timing circuit 93 is an address window detection circuit shown in FIG.
A timing pulse is generated only when a pulse is applied through the signal line 6117 of the AWC 611, and the output 921 of the register 92 is provided to the adder 90.
The timing pulse is generated based on the address range in the horizontal direction (x direction) of the window on the display screen.
This is the point in time when the frame buffer address (X, Y) at which CRTC3 occurs is out, and the next time the address (X, Y) falls within the window address range, the Y value of the address is incremented by +1. There is.
That is, the third term of equation (6) is realized by the adder 90, the gated register 92, and the timing circuit 93. Since the adder 94 has already calculated the first, second, and fourth terms on the right side of equation (6),
The adder 95 obtains the results of calculations from the first term to the fourth term on the right side of equation (6).

The calculation of equation (6) is completed by adding i, which corresponds to the output value of the counter 80, to the calculation result by the adder 96. Counter 80 is an address window detection circuit
AWC611 signal lines 6114, 6115, 61
16. The counter 80 is connected to the signal line 61
When the signal line 6114 is turned on, it is reset and starts counting when the signal line 6114 is turned on. Counting is done by signal line 6116 (signal 31
This is done by the sample timing signal (pulse) of the display dots applied through the CRTC3 (also known as CRTC3) and generated by the CRTC3.

The address signal a(x _i , y _j ) of the window buffer 1, which is the output of the adder 96, is sent to the multiplexer circuit 68 via the signal line 671. The circuit 6
At step 8, a signal necessary for window buffer access is added to address a(x _i , y _j ), window buffer access is performed, and a predetermined dot is read from the window buffer.

Similarly, when the frame buffer address (X, Y) generated by CRTC3 changes and the windows overlap, control signals from multiple address window detection circuits AWC are transmitted to signal lines 621 and 6.
22, 623 or 624.
This signal is notified to the address conversion circuit ATC.

Each address conversion circuit ATC performs address conversion according to data regarding the placement position of screen images and partial images set in advance.
One-dimensional address a(x _i , y _j ) on the window buffer
occur respectively. The addresses a(x _i , y _j ) are each sent to a multiplexer circuit 68. The circuit selects only the one-dimensional address a(x _i , y _j ) on the window buffer corresponding to the window located at the top according to preset data defining the relationship between the weights of the windows. As described above, a signal necessary for window buffer access is added to the address signal a(x _i , y _j ) and sent to the window buffer, and a predetermined dot is read out.

In the above explanation, for simplicity, the number of address window detection circuits AWC and address conversion circuits ATC is assumed to be four, but since these circuits are small in scale, by implementing LSI, several dozen or more of these circuits can be reduced to one.
It is possible to fit it into one chip.

Further, as for the circuits shown in the embodiments of the address mound detection circuit AWC and the address conversion circuit ATC, it goes without saying that other circuit systems may be used as long as the same functions can be realized.

When the address of window buffer 1 is managed as a two-dimensional address, address conversion is performed using equation (7),
It is expressed as (8), and the hardware that realizes this is simple and does not need to be shown in an example.

〔Effect of the invention〕

As explained above, according to the present invention, one
In a multi-window display system that simultaneously displays multiple partial images that are part of any screen image on a CRT, displays that occur when the display contents change, such as updating, moving, enlarging, changing the overlapping state of partial images, or scrolling. There is no need for image transfer from the window buffer to the frame buffer, management of the state of weights of partial images, etc., which are necessary for screen image reconstruction processing. For this reason,
This eliminates the need for a dedicated control processor or a mechanism for transferring image data between the window buffer and frame buffer required for configuring the display screen image, and has the advantage of speeding up the operation of the display screen. Therefore, by applying the present invention to a device having a high-performance display device such as a workstation, it is expected that the device's performance will be improved and the price will be significantly reduced.

Furthermore, the present invention is not limited to soft copy devices such as CRTs, but is generally applicable to devices that perform raster scanning and display images in dots. For example, by applying it to a printer that displays dots, there is no need to re-edit the dot image developed for each character area, figure area, image area, or value area into a single document image with the layout in mind. , it is possible to speed up the processing.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram of an embodiment of the present invention, and FIG. 2 is a schematic diagram of an embodiment of the present invention.
A diagram showing an example of a display screen on a CRT, FIG. 3 is a block diagram of a specific embodiment of the multi-window control unit, FIG. 4 is a circuit diagram of a specific embodiment of the address window detection circuit, and FIG. 5 is a diagram explaining the relationship between addresses of partial images in a screen image developed on a window buffer, Figure 6 is a circuit diagram of an embodiment of the address conversion circuit ATC, and Figure 7 is a conventional multi-window display control. FIG. 2 is a configuration diagram of an embodiment of the method. 1... Wind buffer, 11, 12, 13...
... Screen image, 111, 121, 131 ... Partial image, 2 ... Frame buffer, 112,
122, 132...partial (display) image, 3...
... Synchronization signal generation circuit CRTC, 31 ... Access control signal line, 32 ... Synchronization signal line, 4 ... Image transfer hardware, 5 ... CRT, 51 ... Display screen, 115, 125, 135 ... Window ,
6...Multi-window control unit MWU, 61
...Wind buffer access signal line, 7...Wind buffer output signal line, 52...Dot, 5
3... Window, 54... First vertex of window 53, 55... Second vertex of window 53, 31
1...x coordinate signal line, 312...y coordinate signal line,
313...Display clock signal line, 611, 61
2,613,614...Address window detection circuit AWC, 621,622,623,624...
Window detection signal line, 651, 652, 653,
654...Address translation circuit ATC, 671,6
72,673,674...Address signal line, 68
...Multiplexer circuit MPX, 62... Window selection signal line, X ₁ , Y ₁ ... x coordinate, y coordinate of the first vertex of the window, X ₂ , Y ₂ ... x coordinate of the second vertex of the window ,y coordinate, CMP1, CMP2,
CMP3, CMP4... Comparison circuit, Q ₁ , Q ₂ , Q ₃ ,
Q ₄ ... Output terminal of comparison circuit, R ₁ , R ₂ , R ₃ , R ₄ ...
... Comparison circuit reset terminal, D ₁ , D ₂ ... Comparison circuit input terminal, CLK1, CLK2, CLK3, CLK
4... Comparison circuit clock terminal, 6111, 61
13...AND gate, 6112...OR gate,
FF1...Flip-flop, CLK5...FF1 clock terminal, 6114, 6115, 6116,
6117, 6118... Output signal line of the window detection circuit, (x _s , y _s )... Two-dimensional coordinate value of the first vertex of the screen image, a _s ... Primary corresponding to (x _s , y _s ) Original address, (x ₀ , y ₀ )...Two-dimensional coordinate value of the first vertex of the partial image, (x _o , y _o )... Two-dimensional coordinate value of the second vertex of the partial image, (x _e , y _e )
...Two-dimensional coordinate value of the second vertex of the screen image,
80...Counter, 81, 82, 83, 84, 8
5, 86...Register, 87, 88, 89, 9
0,94,95...adder, 91...multiplier, 9
2...Register with gate function (R), 93...
Timing circuit, 921... Output signal line of register with gate function, x ₀ , -x _s , x _e +1, y ₀ , -y _s ,
a _s ...Value to be set in the register.

Claims (1)

[Claims] 1. A single display device that performs raster scanning and displays images as dots has a window buffer that stores a plurality of screen images developed into dots in order to display the plurality of screen images simultaneously. A multi-window display system comprising: synchronizing the position of a window displayed on the display screen of the display device with the timing at which a control device of the display device raster-scans the position of the window displayed on the display screen of the display device;
Generates the address on the window buffer where the screen image developed on the window buffer to be displayed in the window is located, or when multiple windows are arranged so as to overlap on the display screen. means for generating multiple addresses on the window buffer of multiple screen images corresponding to multiple applicable windows; means for selecting only the address where the corresponding screen image is arranged; and means for reading out the contents of the window buffer specified by the selected address and displaying it on the display device. A multi-window display control device featuring: 2. The multi-window display control device according to claim 1, wherein the means comprises a synchronization signal generation circuit that generates a raster device timing signal and a frame buffer address for a device that performs raster scanning of the display device. , a plurality of address window detection circuits that set the position of a window on a display screen and detect that the frame buffer address exists within the window on the display screen; - A window detection signal line that notifies that an address is detected to be within the window, and a plurality of address conversion circuits that generate addresses on the window buffer in which dot images to be displayed on the window are developed. A multi-window window comprising: a plurality of address signal lines through which the address conversion circuit notifies a window buffer of an address; and a multiplexer circuit that selects one of the address signal lines. Display control device.