JPS60183764A - ＧａＡｓ論理回路装置 - Google Patents

ＧａＡｓ論理回路装置

Info

Publication number
JPS60183764A
JPS60183764A JP59038754A JP3875484A JPS60183764A JP S60183764 A JPS60183764 A JP S60183764A JP 59038754 A JP59038754 A JP 59038754A JP 3875484 A JP3875484 A JP 3875484A JP S60183764 A JPS60183764 A JP S60183764A
Authority
JP
Japan
Prior art keywords
active region
electrode
pull
fet
fets
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59038754A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0550145B2 (cs
Inventor
Hiroshi Nakamura
浩 中村
Hiroshi Yamaguchi
博 山口
Kotaro Tanaka
幸太郎 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP59038754A priority Critical patent/JPS60183764A/ja
Publication of JPS60183764A publication Critical patent/JPS60183764A/ja
Publication of JPH0550145B2 publication Critical patent/JPH0550145B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/05—Manufacture or treatment characterised by using material-based technologies using Group III-V technology

Landscapes

  • Bipolar Integrated Circuits (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Logic Circuits (AREA)
JP59038754A 1984-03-02 1984-03-02 ＧａＡｓ論理回路装置 Granted JPS60183764A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59038754A JPS60183764A (ja) 1984-03-02 1984-03-02 ＧａＡｓ論理回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59038754A JPS60183764A (ja) 1984-03-02 1984-03-02 ＧａＡｓ論理回路装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP6158388A Division JP2524686B2 (ja) 1994-07-11 1994-07-11 ＧａＡｓ論理回路装置

Publications (2)

Publication Number Publication Date
JPS60183764A true JPS60183764A (ja) 1985-09-19
JPH0550145B2 JPH0550145B2 (cs) 1993-07-28

Family

ID=12534074

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59038754A Granted JPS60183764A (ja) 1984-03-02 1984-03-02 ＧａＡｓ論理回路装置

Country Status (1)

Country Link
JP (1) JPS60183764A (cs)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6276781A (ja) * 1985-09-30 1987-04-08 Matsushita Electric Ind Co Ltd 半導体装置
JPS6279674A (ja) * 1985-10-03 1987-04-13 Matsushita Electric Ind Co Ltd 半導体装置
US5148244A (en) * 1990-02-14 1992-09-15 Kabushiki Kaisha Toshiba Enhancement-fet and depletion-fet with different gate length formed in compound semiconductor substrate
US5177378A (en) * 1990-05-08 1993-01-05 Kabushiki Kaisha Toshiba Source-coupled FET logic circuit
US5471158A (en) * 1991-06-12 1995-11-28 Texas Instruments Incorporated Pre-charge triggering to increase throughput by initiating register output at beginning of pre-charge phase

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
IEEE J. OF SOLID-STATE CIRCUITS=1976 *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6276781A (ja) * 1985-09-30 1987-04-08 Matsushita Electric Ind Co Ltd 半導体装置
JPS6279674A (ja) * 1985-10-03 1987-04-13 Matsushita Electric Ind Co Ltd 半導体装置
US5148244A (en) * 1990-02-14 1992-09-15 Kabushiki Kaisha Toshiba Enhancement-fet and depletion-fet with different gate length formed in compound semiconductor substrate
EP0442413A3 (cs) * 1990-02-14 1994-02-02 Toshiba Kk
US5177378A (en) * 1990-05-08 1993-01-05 Kabushiki Kaisha Toshiba Source-coupled FET logic circuit
US5471158A (en) * 1991-06-12 1995-11-28 Texas Instruments Incorporated Pre-charge triggering to increase throughput by initiating register output at beginning of pre-charge phase

Also Published As

Publication number Publication date
JPH0550145B2 (cs) 1993-07-28

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Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term