JPS60183764A - Gaas logic circuit device - Google Patents

Abstract

PURPOSE:To enable to enhance the output load driving capability of a GaAs logic circuit device without increasing the total gate width by a method wherein the first pull- up FET and the first pull-down FET are formed on the stripped first active region, the second pull-up FET and the second pull-down FET are formed on the stripped second active region, and the width of the secon active region is made larger than that of the first active region. CONSTITUTION:A first active region 41, which is reoughly formed in a 10mum wide strip form and part of which is formed in a widths of 5mum, and a second active region 42, which is 20mum in width, are respectively formed on a semiinsulative GaAs substrate 30, and Schottky electrodes 50-53 are formed in such a way as to cross the two regions 41 and 42. Q10-Q13, which are the FETs of a first system, are formed on the first active region 41, and Q20-Q23, which are the FETs of a second system, are formed on the second active region 42. Five pieces of n<+> type regions have been formed in the second active region 42 and ohmic electrodes 60-64, which respectively make an ohmic contact with each of the five n<+> type regions, have been formed on the second active region 42. A Q30, which is a second pull-up FET, is constituted of these electrodes and the Schottky electrode 50 using the electrode 60 connected to an electrode potential conductor 10 as a drain electrode and using the electrode 61 as a source electrode.

Description

TECHNICAL FIELD The present invention relates to a super-buffer GaAs logic circuit device.

(Technical Background) A soot buffer logic circuit using pairs of pull-up field effect transistors and pairs of solder-down field effect transistors is disclosed in U.S. Pat. No. 3,775,693 BAi.
Although it has been disclosed in various documents including Book A, in particular GaAs metal contact field effect transistor (hereinafter simply F
There are few disclosures using ET as a unit element. suit 4
Buffer logic circuits are characterized by a large driving capacity, but since the driving capacity of the GaAs FET itself is relatively small, further failure is required.

(Object of the Invention) An object of the present invention is to reduce the output page
It is said to increase the driving ability.

(Summary of the Invention) The present invention is based on the fact that the first Plua, ZFET is of an 0-resonance type and can be formed into a small surface, a stack. ;7; Form 1 in the approximately band-shaped first active region, and form the 2nd node 'ET and all the 270th 'II' in the approximately band-shaped second active region. 1)
27'+; 1st episode 1, 2nd life than 1 top area width, i
31 people in the area G
1. Changing the page number, the output page
ri"f, ji (4 dynamic abilities are set to 1. each column.

(Example) An example of non-invention will be explained using Figures 1 to 4.
do.

Figure 1 shows a No. 1t logic circuit, 1oj is the power supply potential line, 2θ is the ground '11', potential line, and Q
,i.

is Desolet, /3-type 1st round I=”E1”
, and its drain electrode is connected to the power supply potential line lθ, and the electrode 1 and the source i (the one whose terminal is connected to point A, Q) 1 to Q 3 are the enhancement non-I terminals, respectively. It is a type 1 sol-down FET, and the
Now, one line electrode of each column is connected to point A-' and each source electrode (one line is connected to the ground potential line 2.theta.).

Q 2 o (Shi Ennohensunon E form 2nd 0 Ruanon 01・'ET is there, 1゛rain electric is to ``city power station, gland Jθ''-1゜tsuri-1・'; tL4ri is A
The source inkstone is further connected to point B, which has an output of 0, and Q 21 ・-Q 23
(-,,L People enhancement type 2nd :,/'Lugun FETs are connected in parallel with each other 71 and people/
Z's 1゛Rain Electric) All go to point B, source senior minister or J to Jigumi 6
'Connected to L line)'.

It is a small thing. Then, the first soldown F'l'
:T and second pull-down FET and Q pair (S pair Qll and Q21.Q12 and Q22, Q13 and Q2゜) (・)n1 &:'f, each input +7111
j children S 1 , S 2 ゜S , 7.

2 and 3 show the configuration of the NOR logic circuit shown in FIG. 1. FIG. 2 is a plan view with the insulating film omitted, and FIG. It is a sectional view along the -1 line.

In Figure 2, 30 is a semi-insulating GaAs substrate, and 4 is 10μ? The first active region 42 is formed in a shape with a width of 21 approximately 11;
The m-wide 27th fi-electrode regions 50 to 53 are Schottky electrodes, respectively, and are formed to cross the self-activated regions 4) and 42, so that QIO to Q3, which are FEi' of the first system, are
'; 1 active, 1', 1 is formed in region 4, and Q2F) to Q23 of the second system are formed in the second active region.

Referring to Figure 3, there are ζ 1 in the 42nd life of the 1st life of the 2nd life.
Five n regions are formed, and ohmic electrodes 60 to 64 are formed to make ohmic contact with them. The connected electrode 6θ is used as a drain electrode, the electrode 6 is used as a source electrode, and these and seven horizontal electrodes are constructed. Similarly, the second pulldown FEi
Q21, which is ', is made by using electrode 6 as the drain electrode, electrode 62 as the source 4u (similarly, and: LL et al.
are electrodes 63, 62 . , U2υThus, Q23 is constituted by 3+64+5J at the electrode. In addition,
In Figure 3, 70 is a sample of Zettaibuta.

Similarly, in the first active region 4), C, Tokiden Eve 50 to 53, and ohmic electrodes (i 0 , 62 , 64
In parallel, ohmic electrodes 81 and 82 are formed to make ohmic contact in the first active region 4), and
The Fl bow T of QIO-QO3 is [74 formed)'.

+f'': o:, In Figure 2, 91 and 92 are upper layer wiring, and wiring 9 is the output terminal O at point B:
It shows the sense line, and the Q 20 source electrician 4 meals...
1jiQ21 drain electrode Ohmi, Riden jy)
467 and Q22. Connect the ohmic electrode 63, which is the drain electrode of Q23, and complete the wiring! / :: (
□ In front of the source electrode of J, Q10, the drain voltage of Qll is connected to the 4 ohmi electrodes 81 and Q)2. Q13 (tsu1
Connect with the ohmic layer 82 which is the rain electrode
J! Q10 7. ? The connection between the kit kit iu pole and the Nance Densho is made outside the section indicated by i5e A.

In FIG. 2, the ohmic electrodes 62, 64 are connected to the ground potential line 2o, and the electrodes 62 are connected to Qll, Q12, .
Q21. serving as the source electrode of Q22, electrode 64 serves as the source electrode of Q13. It can now function as the source electrode of Q23.

As explained above, the second system I'ETO case-1.
Since the width is widened, a correspondingly large load driving capacity can be obtained, and the gate width of the first system F'ET is made small enough to be driven one step further.
It is possible to suppress the increase in Minoζ negative moe from the previous stage, and because the first system and the second system are formed into band-shaped active regions for different people, the overall occupied area is relatively small. There are advantages.

In the above embodiment, the enhancement type is used for the 2:10 ru-down 0FET, but a depletion type can be used, and the active region width is adjusted according to the gate width of that part to match the second ru-down FE'r. to 1
It is desirable to set it to about /4.

In addition, as the second pulla, 7″Ii'ET, there is a
If a Yon type is used, the load and driving capacity can be increased, but the low level output will be somewhat large.

Furthermore, although the above embodiment describes the case where the pull-down FETs are connected in parallel, it can also be applied to NAND logic in which the pull-down FETs are connected in series, and in this case, the first system FET and the second A similar effect can be achieved by forming the FETs in the system into separate strip-shaped active regions, and by making the gate electrodes of the corresponding FET pairs common and cutting both strip-shaped active regions into J (a similar effect can be obtained). .

(Effects of the Invention) As is clear from the above description, according to the present invention, it is possible to increase the output load driving capacity without increasing the total scale as seen from the previous stage, and moreover, it is possible to increase the overall occupied area. It has advantages such as being relatively small/JS.

[Brief explanation of the drawing]

1 to 3 are explanatory diagrams of one embodiment of the present invention, in which FIG. 1 is a circuit diagram, FIG. 2 is a plan view, and FIG. 3 is an i--
FIG. 10... Power supply potential line, 20... Ground potential line, 30...
...GaAs substrate, 41, 42-...band-shaped active region,
50-53... Nyotoki electrode, 60-65... Ohmic electrode, 70... Insulating film, 81.82... Ohmic electrode, 91.92... Upper layer wiring. Q I L)...1st sol anozo FET5Qll~Q
No. 3... 1st pull-down FET, Q 20... 2nd pull-up 0 FET, Q 21-Q 23...
270th Lugun I T1S7-83...Input terminal,
0...Output terminal. 11 yen Applicant Oki Electric Co., Ltd. Figure 1 0 Figure 3

Claims (1)

[Claims] A deplanation type first sol-up FET in which the r-t electrode and the source electrode are connected at point A and the drain electrode is connected to a first potential, and the dirt electrode is connected to the point A and the drain electrode is connected to the first potential. A second pull-up FET whose source electrode is connected to point B and a plurality of enhancement type 17" pull-down FETs are connected in series or parallel to each other, and between the point A and the second potential. and a plurality of enhancement-type second Soldown FETs connected in series or parallel to each other and connected between the point B and the second potential, and corresponding to each other. A GaA device in which the dart electrode of the first pull-down PET and the dart electrode of the second pull-down FET are connected to a common input terminal, and the point B is the output terminal.
s logic circuit device, the first ZOLATSU 7"FET and all the first ZOLDOWN FETs are connected to a continuous approximately strip-shaped first
and a second glue FE formed in the active region of the
T and all the 2F pull-down FETs are formed in a substantially strip-shaped second active region parallel to the active layer, and the width of the second active region is made larger than the width of the first active region. A GaAs logic circuit device characterized by: