JPS58119649A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve the degree of integration as well as to contrive high speed operation of the titled device by a method wherein the working region, located between each gate of the adjoining P channel MOS transistors constituting the logical function elements which are adjoining each other or between N channel MOS transistors, is commonly used and the length of the wiring between the logical function elements of the above-mentioned transistors is shortened. CONSTITUTION:The complementary type MOS transistor for isolation of the former stage inverter and the latter stage one, to be more precise, a P channel MOS transistor consisting of a gate electrode 22 and an N channel MOS transistor cnsisting of a gate electrode 33 are abbreviated. The source region of the complementary type MOS transistor which constitutes the former inverter and the source region of the complementary type MOS transistor which constitutes the latter inverter are utilized as common regions.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor S integrated circuit device, and particularly to a phase h+4 circuit used in a master slice type gate array LSI.
This is related to the Type 8108 culvert circuit device.

Generally, as shown in Figure 1, a gate array is constructed using an LSI external circuit (LSI
an input/output circuit (2) connected to the input/output circuit (d-side circuit); gates connected to this input/output circuit (2) are arranged in an array; It is configured to be interlocked with an internal circuit (3) which is a collection of internal logic functional elements wired using 2N1 aluminum.

The internal circuit (3) has a plurality of complementary M08 transistors that form a pair of a P-channel M08 transistor and an n-channel inter-channel 08 transistor, and configures a plurality of logic functional elements by a desired number of these plurality, and these logic It is a collection of functional elements.

Logic! One example of a functional element is one in which inverters are connected in two stages, as shown in the circuit diagram of FIG. In the figure, (4) is a P-channel MO8 transistor (
5) and an n-channel MO8) transistor (6) form a pair of complementary MO8) transistors, and (7) is a P-channel MO8 transistor (8).
) and an n-channel MO8 transistor (9) form a pair of complementary MOB transistors, and QQ is a positive WIt source line formed by the first aluminum layer formed on the insulating layer. , αυ is the ground wire formed by the first aluminum layer formed on the insulating layer, (2) is the input terminal of the inverter (4) in the previous stage, and αυ is the output terminal of the inverter (7) in the latter stage It is.

A two-stage inverter constructed in this manner can be constructed on a device based on conventional technology, as shown in FIG. 8.

In the eighth layer, O and ~0 are P-type impurity diffusion regions that are formed in the n-type semiconductor layer and become active regions, and (7) to ■ are gates formed between these P-type impurity diffusion regions Q4 to αe. The gate electrode provided on the region, the n-type impurity diffusion region which becomes the active region formed in the P-type semiconductor layer,
0υ~(to) is a gate array provided on the gate region formed between the n-type impurity diffusion regions)~(to). In other words, in Fig. 8, the P-channel MO8) resistor and the N-channel MO8 where the gate turtle←R faces each other.
Complementary type M paired with a transistor (J81 - one with 5 transistors drawn, gate electrode 6!l)
, a P-type M08 transistor composed of a P-type impurity diffusion region 05 (becomes a drain region), and a P-type impurity region αQ (becomes a source region), a gate electrode (to),
The previous stage inverter is composed of complementary M08 transistors that form a pair with an n-type MO8) transistor consisting of an n-type impurity diffusion region (to become a drain region) and an n-type impurity diffusion region @ (source region). And game hh
t=a, P-type impurity diffusion region α (becomes source region)
A P-type M08 transistor consisting of a P-type impurity diffusion region (T) (becomes the drain region), a gate electrode (2), and an n-type impurity diffusion region @ (becomes the source region)
An inverter at the subsequent stage is constructed by forming a pair of complementary MO8 transistors with an n-type MO8 transistor constituted by an n-type impurity diffusion region (which becomes a drain region). - is a contact hole that penetrates the insulating layer and electrically connects the end of the gate with member to the positive power supply line αQ. A non-conductive layer is formed between the gate electrodes (g) and the p-type impurity diffusion regions σ◆ and (to), and the gate electrode (1) separates the p-type impurity diffusion regions σ◆ and (to). (to) is a contact hole that penetrates the insulating layer and electrically connects the end of the gate electrode e1) and the ground wire αυ, and supplies negative power (including ground potential) to the gate electrode el) As a result, a non-conducting layer is formed between the n-type impurity diffusion regions (c) and (e), and the n-type impurity diffusion regions (c) and (to) are separated by the gate electrode CI core. become. @ (to) is a contact hole for electrically connecting the gate electrode (2) and the positive power line αQ, and the gate electrode - and the positive power line ko, and functions in the same way as the above contact hole (to). The P-type impurity diffusion layer 4 and αη are separated by the gate electrode, and the P-type impurity diffusion layer 4 and αη are separated by the gate electrode. Ol- is connected by a contact for electrically connecting the gate electrode and the ground line αυ, and the gate electrode (to) and the ground line αυ, respectively, and the type 11 impurity diffusion region 4 and... are connected by the gate electrode (to). , will be separated from each other. @ is insulation - second layer formed on top
The gate wIt pole of the P-channel inter-channel 08 transistor, which is formed from the second aluminum layer and constitutes the complementary MO8 transistor serving as the previous stage inverter. The input terminal is electrically connected to the gate electrode (2) of the p- and n-channel MO8) transistor through the through hole (b) and the 21111th aluminum layer formed on the insulating layer. At the output terminal of the inverter in the later stage formed by the layer, the P-type impurity diffusion region (toward) (P-channel MO8, which constitutes the inverter in the later stage) is connected via the souffle hole.
When electrically connected to the connection line formed in the first aluminum layer (which becomes the drain region of the transistor) through a contact hole,
The first layer of aluminum is electrically connected to the n-type impurity diffusion region @ (which becomes the drain region of the n-channel MO8 transistor that constitutes the inverter in the subsequent stage) through the contact hole 1η through the through hole ■. It is electrically connected to the connection line formed by the layers. - is an inverter connection line made of the first aluminum layer formed on the insulating layer, which connects the P-channel MO8) transistor which constitutes the complementary MO8) transistor which becomes the previous stage inverter via the contact hole - and ψυ. It is electrically connected to the P-type impurity diffusion layer region αυ of the n-channel MO8 transistor and the n-type impurity diffusion layer region (to) of the n-channel MO8 transistor (each becomes the drain region of the transistor), and is Complementary MO8) n-channel M that constitutes a transistor that becomes the inverter in the subsequent stage
O8) 0 between transistor gate electrode ■ and P channel
It is electrically connected to the gate electrode of the 8 transistor.

-1 is P channel MO8 which constitutes the inverter of the previous stage)
The P-type impurity diffusion layer region (to) of the transistor and the P-type impurity diffusion layer region Q7 of the P-channel MO8 transistor constituting the subsequent inverter (each becomes the source region of the transistor) are electrically connected to the positive electric gap line QIJ. -671 is the n-type impurity diffusion region (2) of the n-channel AlO3) transistor that constitutes the inverter in the previous stage, and the n-type impurity diffusion region (2) of the n-channel M)8 transistor that constitutes the inverter in the latter stage. These are contact holes for electrically connecting the @ (each serving as a source region of a transistor).

In this way, at least a part of the transistors has a plurality of complementary M08 transistors each consisting of a P-channel inter-channel 08 transistor and an n-channel MO8 transistor, and these complementary MO8)
When a two-stage inverter is constructed using two complementary MO8) transistors in which the gate electrodes of the transistors are arranged next to each other, the inverter at the front stage and the inverter at the rear stage have separate logic functions. Because it is a transistor, a complementary MO8) transistor is interposed between the front-stage and rear-stage inverters, and if this complementary MO8 transistor is configured as an isolation transistor, it forms part of the front-stage inverter. P-channel MO8) Source region of transistor, that is, P-type impurity diffusion region α,
P-channel MO8) which forms part of the inverter in the latter stage, the source region of the transistor, that is, the P-type impurity diffusion region αη
are both connected to the positive power supply line OQ, and on the other hand, the source region of the n-channel MO8 transistor that forms part of the inverter in the previous stage, i.e., the n-type impurity diffusion region (a), and the part of the inverter in the latter stage. n-channel MO8) The source region of the transistor, that is, the n-type impurity diffusion region (c), is both connected to the ground line Ql), and is a complementary type MO that constitutes the front-stage inverter and the rear-stage inverter, respectively.
O8) In a transistor, two adjacent source regions of the same potential are arranged side by side, resulting in a large area and a problem in improving the degree of integration.

An n-channel hphantom consisting of a gate electrode constituting an in and a gate electrode. A contact hole for connecting the line 00 is a contact hole that penetrates the insulating layer and connects the n-type impurity diffusion region and the ground line 0υ.

Even with such a structure, in addition to performing the same circuit operation as the two-stage inverter shown in FIG.
The transistor can be omitted, improving the degree of integration, and the length of the aluminum wiring for connecting the output of the inverter at the front stage to the input of the inverter at the rear stage can be shortened, reducing stray capacitance and increasing speed.

In the above embodiment, the logic functional element gate circuit is an inverter, and an inverter circuit consisting of two inverters has been described, but the logic functional element is not limited to an inverter, and in short, one or more complementary MO8 transistors. In such a case, the logic functional elements are configured in multiple units, and the active areas of adjacent P-channel MOS transistors or n-channel transistors of the adjacent logic functional elements are the same potential and constitute the same area. If it is, it will have the same effect.

As described above, the present invention has a plurality of complementary MO8 transistors, each of which is paired with a p-channel MOS transistor, a transistor and an n-channel MOS transistor, and a transistor, in which gate electrodes are arranged in parallel in at least some of the transistors. The present invention has been made in view of the above points, in which a plurality of logical functional elements are arranged in one or more complementary MO8) transistors, and adjacent logical functional elements are arranged in parallel with gate electrodes in at least some of them. Complementary MO8 transistors are paired with P-channel MOS transistors and N-channel MOS transistors, and there are multiple transistors, one or more complementary MO8 transistors are configured with multiple logic functional elements such as inverters, and The purpose is to improve the degree of integration by sharing the active region located between the gate electrodes of mutually adjacent P-channel MOS transistors (P-channel MOS transistors), transistors, or N-channel MOS transistors that constitute matching logical functional elements, respectively. .

Below, a case where an embodiment of the present invention is applied to a two-stage inverter will be explained based on FIG. 4. The same reference numerals as in FIG. The isolation +4A@z1MOOfJ transistor shown in Figure 8 is for separating the front-stage inverter and the rear-stage inverter, that is, it is composed of a P-channel MOS transistor composed of a gate tail (2) and a gate array (toward). The n-channel MOS transistor is omitted, and the source region of the complementary Δ108 transistor that constitutes the front-stage inverter and the complementary MO8 transistor that constitutes the rear-stage inverter are used.
It uses the source region of the transistor as a common region. In the figure, - indicates a P-channel MOS composed of a gate electrode ship p constituting the inverter in the previous stage.
A P-channel MOS consisting of a gate electrode that serves as the source region of the transistor and constitutes the inverter in the later stage), a P-type impurity diffusion region that serves as the source region of the transistor, and a gate electrode that constitutes the inverter in the former stage. The active region is shared between the gates of the adjacent P-channel MOS transistors (or n-channel MOS) transistors, which are the source regions of the n-channel MOS transistors that are constructed, and the gates of the adjacent P-channel MOS transistors (or n-channel MOS transistors) that constitute the respective subsequent stages. Furthermore, the wiring length between both logic function elements can be shortened, and the speed can be increased.

[Brief explanation of the drawing]

Figure 1 is a gate array configuration diagram, and Figure 2 is an inno (-ta 2) diagram.
The series circuit connection diagram of the stages, FIG. 8, is made using conventional technology.
FIG. 4 is a top view of a semiconductor when two stages of inverters are constructed. FIG. 4 shows an embodiment of the present invention and is a top view of a semiconductor when two stages of inverters are constructed. In the diagram, 01 is the positive power supply, (b) is the ground wire, (b)
is an input terminal, (to) is an output terminal, Q4~α and 2 are P-type impurity diffusion regions, 4~(c) are gate electrodes, (c)
. . . and - are n-type impurity diffusion regions, 6υ to (to) are gate electrodes, and tl) I1 is a contact hole. In each figure, the same reference numerals indicate the same or corresponding parts. Agent Makoto Kuzuno - Figure 1 1 Figure 2 Figure 3 Figure 4 Procedural amendment (voluntary) 748 Showa year, month, day 2, title of invention: Semiconductor integrated circuit device 3, consideration for supplementary jF & subject of amendment (1) Full text of the specification (2) Drawing a Contents of amendment (1) The full text of the specification will be corrected as shown in the attached sheet. +2) In the drawings, Figures 8 and 4 will be corrected as shown in the attached sheet. Corrections to the above Description 1, Title of the invention Semiconductor integrated circuit device 2, Claims (1) A plurality of gate electrodes are arranged in parallel on the surface of a semiconductor layer, and an active electrode is provided in the semiconductor layer between each gate electrode. A plurality of P-channel M08 transistors in which a P-type impurity diffusion region is formed, and a plurality of gate electrodes are arranged in parallel on the surface of the semiconductor layer, facing the gate electrode constituting the P-channel lvMO8 transistor. At the same time, an n-type impurity diffusion region serving as an active region is formed in the semiconductor layer between each gate electrode, and a plurality of n+ transistors are formed in pairs with a P-channel MOB transistor whose gate electrodes face each other. In a configuration in which a plurality of logic functional elements are configured by one or more pairs of P-channel MOB transistors and n-channel MOB transistors, adjacent P-channel M transistors of adjacent logic functional elements
O8) Fungistor or n-channel MO8) Sharing the active region located between each gate electrode of Fungistor
A semiconductor integrated circuit device characterized by: (2) Adjacent P channels M of adjacent logic functional elements
8) The semiconductor integrated circuit device according to claim 1, wherein an active region located between gate electrodes of a fungistor or an n-channel MO8) transistor is used as a source region. (3) Adjacent P channels M of adjacent logic functional elements
O8) Transistor or n-channel MOB) The active region located between each gate of the transistor is connected to the positive power supply line for a P-channel MO8 transistor, and to the negative power supply line for an n-channel MO8) transistor. A semiconductor integrated circuit device according to claim 1 or 2, characterized in that: a. Detailed Description of the Invention The present invention relates to a semiconductor integrated circuit device, and in particular to a complementary M circuit used in a master slice type gate array LSI.
This relates to an O8 integrated recess device. Generally, as shown in Figure 1, a gate array includes an input/output circuit (2) connected to the LB circuit (L8 peripheral circuit) around a silicon chip (1), and an input/output circuit (2) connected to the LB circuit (L8 circuit) around the silicon chip (1). ), among which (internal circuit power 3 which is a collection of internal logic functional elements arranged in an array of 111vc gates and wired on the internal gates with the first layer of aluminum and the second layer of aluminum) It is composed of −
Ru. The internal circuit 1B) has a plurality of complementary VO transistors each consisting of a P-channel MOEI transistor and an n-channel MOEI transistor, and a desired number of these transistors constitutes a plurality of logic functional elements. , is an aggregate of these logical functional elements. An example of a logical functional element is a two-stage inverter connected as shown in the circuit diagram in Figure 2. In Figure 0, (4) is a P-channel MO8 transistor (5
) and an n-channel M08) transistor (fl+).
) and an n-channel M08 transistor (9) to form a pair of complementary MO8) transistors. A power line, (Ill is a ground line formed by the first aluminum layer formed on the insulating layer,
Hl is the input terminal of the inverter (4) at the front stage, and Qil is the output terminal of the inverter (7) at the rear stage. A two-stage inverter constructed in this manner can be constructed on a device based on the conventional technology as shown in FIG. 8. In FIG. 8, (141 to 11# are P-type impurity diffusion regions formed in the n-type semiconductor layer and become t active regions, and - to gates formed between these P-type impurity diffusion regions 04 to tII. The gate electrode provided on the region, (c) ~ (
7) is an n-type impurity diffusion region formed in the P-type semiconductor layer and becomes an active region, and 09-(2) is a gate region formed between these n-type impurity diffusion regions (2) and the ring. t
This is an Nt gate electrode. In other words, in FIG. 8, a complementary type M08 is formed by forming a pair of a P-channel MO transistor and an n-channel MO8 transistor whose gate electrodes face each other.
Five transistors are drawn, and the transistor is composed of a gate electrode FM@, a P-type impurity diffusion region 05] (which becomes a drain region), and a P-type impurity region 1111 (which becomes a source region). Type MO8) transistor, gate electrode [(2), n-type impurity diffusion region (e) (becomes drain region) and n-type impurity diffusion region @ (source region)
The complementary MO8) transistor, which is paired with an n-type MO8) transistor, constitutes the inverter at the front stage, and gate voltage Diffusion region 01 (becomes a drain region) P-type MO8) fungistor, gate electrode-1 n-type impurity diffusion region @ (becomes a source region) and n-type impurity diffusion region 1 (becomes a drain region) The inverter at the subsequent stage is constructed by a complementary type MO8) transistor which is paired with an n-type MO transistor. - is a contact hole that penetrates the insulating layer and electrically connects the end of the gate electrode - to the positive power supply line aO.
A non-conducting layer is formed between and (b) A contact hole for electrically connecting the end of the earth wire (Ill) with the negative power supply (including ground potential)
By supplying to the gate electrode Taη, a non-conducting layer is formed between the n-type impurity diffusion regions (2) and (4), and the n-type impurity diffusion regions (2) and (2) are connected to each other by the gate electrode plow. will be separated. @(to) is a contact hole for connecting the gate electrode slope to the positive power line αO and the gate electrode (c) to the positive power line αO to the gold conductor, respectively. The type impurity diffusion layers 01 and 0 are separated by the gate electrode, and the P type impurity diffusion layers Q and 4 are separated by the gate electrode. @(a) is the gate electrode (to) and ground wire 111 respectively
This is a contact hole for electrically connecting 1 and the gate electrode WA- to the ground line (river), and acts in the same way as the contact hole (7) above to connect the n-type impurity diffusion region (material) and (to). ) By the W pole (to), the n-type impurity diffusion regions 4 and (7) are separated by n from each other by the gate electrode (to). Cl2J is the second layer formed on the insulating layer.
A P-channel M is machined into a layered aluminum body and constitutes a complementary MO8) transistor that serves as the front-stage inverter.
O8) Funjista game) [Goku a! 1) ν and n-channel MO8) Input terminal electrically connected to transistor gate via through hole @1Jν, a3 is the second layer formed on the insulating layer At the output terminal of the inverter at the later stage, which is formed on aluminum y, the K contact is connected to the P-type impurity diffusion layer region α barrel (which becomes the drain region of the P-channel M08 transistor that constitutes the inverter 1 at the later stage) via a through hole. Electrically connected via hole @4 -,! n, 6) to the connection line formed of the first aluminum layer), and via the through-hole to the n-type impurity diffusion layer region (n channel forming the inverter in the subsequent stage). MOEI) which becomes the drain region of the transistor) is electrically connected to the connection line (c) formed in the first layer of aluminum, which is electrically connected to the drain region of the transistor through the contact hole. . - is an inverter connection line made of the first aluminum layer formed on the insulating layer, and is connected to the complementary MOEI transistor in the previous stage through the contact hole So and F311. The p-type impurity diffusion layer region a51 and the n-channel MO8) are electrically connected to the n-type impurity diffusion layer region (e) of the fungistor (each becomes the drain region of the transistor), and the contact hole is formed [' Complementary type MO8) which becomes the inverter in the subsequent stage via n-channel MO8) Gate electrode of transistor ■Working P
Channel MO8) The gate of the transistor is electrically connected to the pole. -1 is the P-type impurity diffusion layer region 0 to (1) of the P-channel MOS transistor constituting the inverter in the previous stage and the P-type impurity diffusion layer region 1 of the P-channel MOS transistor constituting
Contact holes for electrically connecting the respective source regions of the transistors to the positive power supply line αO;
8) Electrically connect the n-type impurity diffusion region (material) of the transistor and the n-type impurity diffusion region (each becomes the source region of the transistor) of the subsequent inverter (11-configuring n-channel MO8) transistor. This is a contact hole for In this way, at least a part of the P-channel MO8) transistor and the N-channel MO8) Funjistor are paired? These complementary MOBs have a plurality of complementary M08 transistors.
When a two-stage inverter is configured using two complementary MO8) transistor gates [W-1)E installed next to each other, the front-stage inverter and the rear-stage inverter Finally, a complementary type M is used between the front and rear inverters using the logic function element of the second stage.
In the case where an O8 transistor is interposed and this complementary MO8) transistor is configured as a separation transistor, a P-channel MO8 that forms part of the inverter in the previous stage is used.
) The source region of the transistor, that is, the P-type impurity diffusion region 01, and the P-channel MO forming part of the inverter in the subsequent stage.
8) The source regions of the transistors, that is, the P-type impurity diffusion regions αη, are both connected to the positive power supply line no, while the source regions of the transistors, that is, the n-channel MO transistors made of gold, The source region of the n-channel MO8) transistor, that is, the n-type impurity diffusion region that forms part of the inverter in the subsequent stage, is both connected to the ground line (11). Complementary MO that configures the and the subsequent inverter, respectively.
8) A transistor has a structure in which two adjacent source regions of the same potential are lined up, requiring a large area, which poses a problem in terms of improving the degree of integration. The present invention has been made in view of the above-mentioned points, and includes a P-channel MOS transistor in which gates and poles are arranged in parallel at least in part. Channel MO8) It has a plurality of complementary MOε transistors that form a pair with a transistor, and one or more complementary MOS transistors are configured with a plurality of logical functional elements such as an E-inverter, and all adjacent logical functional elements are mutually configured. Adjacent P channel M
O8) The purpose is to improve the degree of integration by sharing the active region between the gate electrodes of transistors or Vin channel MO transistors. Below is one 51i of this invention! If the example is applied to a two-stage inverter and applied to a tortoise model, based on FIG. 4, the same reference numerals as in FIG. 8 indicate the same or equivalent parts. Complementary MO8 for separation to separate the front-stage inverter and the rear-stage inverter shown in FIG.
Complementary MOEI transistor, that is, a 2F channel MOEI consisting of a gate electrode gradient and an n-channel MOEI consisting of a transistor and a gate voltage mcn (8) transistor, is omitted and constitutes an inverter in the previous stage. The source region of the complementary MOEI transistor constituting the invert I is used as a common region. In the figure, the P channel 7t, M
OE+) A P-channel MQS, which is composed of a gate electrode (c) which serves as the source region of the transistor and forms two subsequent inverter stages. P-type impurity diffused @region, which becomes the source region, (59) (gate which forms the inverter at the front stage) [n-channel MQSI composed of poles] c) N-channel MO composed of Ti sardine 8) An n-type impurity diffusion region which becomes the source region of the lunge star, which in turn penetrates the insulating layer, and connects to the above-mentioned P-type impurity diffusion region and the positive power supply line 10.
Funtact hall, for meeting with! Bl is a hole that penetrates the entire insulating layer and connects the n-type impurity/diffusion region (69) and the ground hole H. 2...jρ ( Tact hole. Even in the case of fLn configured in this way, the 2
In addition to performing the same circuit operation as the inverter in the previous stage, a complementary MO8 for separation is used to separate the inverter in the previous stage and the subsequent stage.
) The transistor can be omitted, increasing the degree of integration, and the length of the aluminum wiring S used to connect the output of the inverter in the previous stage to the input of the inverter in the latter stage can be shortened, reducing floating volume fk and increasing speed. It is. Note that in the above embodiment, the logic function element gate circuit is an inverter, and the inverter circuit consisting of two inverters is described, but the logic function element is not limited to an inverter. Type MQ8)
Example C where a plurality of logic functional elements are configured in a single transistor, and adjacent P-channel MO8 transistors or n-channel MO8 transistors or n-channel MO8 transistors are adjacent to each other; the active regions are at the same potential; If the two IS's constitute the same area, the same effect will be achieved. As mentioned in Uedo, this crystal has a plurality of complementary v□s transistors, each of which is a pair of a P-channel M08 transistor and an n-channel M08 transistor, both of which have gate electrodes of parallel #9. and one or more complementary MQ8) transistors constitute a plurality of logic functional elements t7
, and mutually adjacent P channel transistors or n
By sharing the active region between the gates of the channel M0B transistors, the degree of integration can be improved, and the wiring length between both logic function elements can be shortened, making it possible to increase speed. effective. Brief explanation of the drawings Figure 1 is a gate array configuration diagram, Figure 2 is a series circuit connection diagram of two stages of inverters, and Figure 8 is a top view of a semiconductor when two stages of inverters are configured using conventional technology. FIG. 4 shows an embodiment of the present invention, and is a top view of a semiconductor in which two stages of inverters are configured. In the figure, Q (I is the positive power supply line, (■) is the ground wire, a is the input terminal, 03 is the output terminal, 04 to 0 and 0 are P
type impurity diffusion region, -~■ are gate electrodes, poles, (2)~(
7) and (69) are n-type impurity diffusion regions, (2) to ■
is gate electrode 1,! 811R1 is a contact hole. In each figure, the same reference numerals indicate the same or corresponding parts. Agent Makoto Kuzuno - Figure 3 Figure 4

Claims (1)

[Claims] (A plurality of gate electrodes are arranged in parallel on the surface of the 11 semiconductor 1-, and 11t is provided in the semiconductor layer between each gate electrode.
P of li number in which the P-type impurity diffusion region forming the A region is formed.
A plurality of gate electrodes are arranged in parallel on the surface of the channel MO8) transistor and the semiconductor layer, facing the gate electrodes constituting the P channel MO8) transistor, and the semiconductor layer between each gate electrode becomes an active region. An n-type impurity diffusion region is formed and a plurality of n-channel MO8) transistors are paired with a P-channel M(JS) transistor whose gate electrodes face each other, and one or more P-channel MO8) transistors and an n-channel In a structure in which a plurality of logic functional elements are configured by pairs of MOS transistors, the active region located between the gate electrodes of adjacent P-channel MθB transistors or n-channel O8 transistors of adjacent logic functional elements is shared. Semiconductor integrated circuit device. (2) The semiconductor integrated circuit device according to claim 1, characterized in that both logic functional elements that blink together are inverters. (3) Adjacent P channels M of adjacent logic functional elements
O8) Claim 1 or 2, characterized in that the active region located between each gate electrode of a transistor or an n-channel MOS transistor is used as a source region.
The semiconductor integrated circuit device described in . (4) Adjacent P channels M of adjacent logic functional elements
O8) The active region located between each gate of a transistor or an n-channel MOS transistor is connected to the positive electric gap line for the P-channel MO8) transistor, and to the negative power supply line for the n-channel MOS transistor. A semiconductor integrated circuit device according to any one of claims 1 to 8, characterized in that: