JPS6056292B2 - Complementary MOS integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a complementary MOS integrated circuit device, and particularly to an arrangement structure of unit cells in an integrated circuit device having a portion in which a plurality of unit cells are arranged in a row, such as a transistor array or a gate array. The present invention also relates to improvements in the separation structure between functional elements.

Hereinafter, a description will be given using a gate array as an example. FIG. 1 is a conceptual layout and configuration diagram of a gate array, which is composed of an input/output circuit section 1, an internal wiring section 2, and an internal gate section 3. In the internal gate section 3, cells serving as units are arranged in a row. Generally, a unit cell (hereinafter referred to as a unit cell).

) may be one type or multiple types. A functional element having a logic function is formed of one or more unit cells, or a plurality of functional elements are formed within a unit cell. The plurality of functional elements configured in this manner are connected to each other by internal wiring provided in the internal wiring section 2 shown in the figure, and are further connected to the input/output circuit existing in the input/output circuit section 1 to form a logic circuit. Configure. FIG. 2 is a diagram showing an example of the arrangement of conventional unit cells. The unit cell 30 surrounded by a broken line in the figure is a MOSI transistor (MOST).
) forming gate regions 31a and 31b) forming regions 32a and 32b forming sources or drains), and isolation regions 33 for electrically isolating adjacent unit cells.

A portion 34 surrounded by a dashed line in the figure is a portion having a conductivity type opposite to that of the semiconductor substrate other than this portion, and is generally called a well. Normally, an n-type semiconductor substrate is used, and a p-type impurity is introduced into this portion 34. Therefore, the n-channel M
An OST is configured, and a p-channel MOST is configured on the semiconductor substrate side outside the OST. In the example in Figure 2, unit cell 3
Since three pairs of gate regions 31a and 31b are arranged in 0, a functional gate with a maximum of three inputs can be configured. However, if a functional gate or flip-flop with four or more inputs is to be configured, a plurality of unit cells 30 will be used.

FIG. 3 is a block diagram of a 4-input NOR gate constructed using this conventional example. In the figure, 41 indicates the first layer of aluminum (, Al) wiring, and 42 indicates the second layer of A1 wiring.

A1 wiring 4 in the second layer from the internal wiring area 2 shown in FIG.
2, the four inputs 1N1 to IN4 are connected to the gate electrodes 31a, 31b, 3 of the p-channel and n-channel MOST.
1c and 31d, and the output 0UT is sent to the internal wiring area 2 via the second layer wiring 42 again. This 4
Connection between the MOSTs in the input NOR gate is made by the first layer A1 wiring 41. Reference numeral 51 denotes the first layer N wiring 41 and p-type or n-type source or drain regions 32a, 32b, 32c, 3 formed on the surface of the semiconductor substrate.
2d is shown.

52 is the second layer Al wiring 42 and gate regions 31a, 31
b, 31c, and 31d, and 53 is a connection point between the first layer Al wiring 41 and the second layer Al wiring 42.

In this conventional configuration, an isolation region 33 is provided between each adjacent unit cell 30 to electrically isolate them. For this reason, for example, when configuring a 4-input NOR gate, the Thus, three pairs of gate regions 31a and 31b and one pair of gate regions 31c and 31d are required, and two unit cells 30 must be combined.

That is, the n-channel MOS included in both unit cells 30
T source or drain regions 32a and 32c and p-channel MOST source or drain region 32
Two wires 411 are required to connect b and 32d to electrically equalize the potential.

Moreover, since the area of the source or drain region in this part is larger than the source or drain region in other parts, the stray capacitance between it and the semiconductor substrate or the above-mentioned well increases, which slows down the operating speed of the functional gate. It has drawbacks. The present invention has been made in view of the above points, and by making it possible to configure a unit cell of any size without forming an isolation region, it is possible to integrate complementary MOS with high integration density and high operating speed. It also aims to provide circuit devices.

FIG. 4 is a layout diagram showing one embodiment of this invention. Parts equivalent to those in this example are indicated by the same reference numerals, and their explanation will be omitted.

In this embodiment, the isolation region 33 for separating unit cells in the conventional example is not provided, and the unit cells 30 can be configured as desired. That is, for example, if one wants to configure a unit cell 30 with four pairs of MOSTs as shown in FIG. 31
Same as a and 31b.

] Unit cell 30 can be isolated from adjacent regions by disconnecting the MOSTs corresponding to gate regions 311a and 311b by connecting them to ground potential and positive power supply potential, respectively.

FIG. 5 is a block diagram of a four-input NOR gate constructed using this embodiment. Parts equivalent to those of the conventional example are designated by the same reference numerals, so this construction can be easily understood from the above explanation. . In the above example, a 4-input gate was used, but any inputs (inputs 1 to 7 in the example shown in Fig. 4) can be used.
The gate can be constructed as a single unit cell.

The same applies to cases where a large number of unit gates are required, such as flip-flops. Furthermore, although the case in which the shapes of the gate regions included in the unit cells are all the same is shown, gate regions of different shapes may also be included, and of course, it is also possible to configure multiple types of unit cells in one integrated circuit. It's okay. In the above example, an n-type semiconductor substrate was used, but it goes without saying that a p-type substrate may also be used. As explained above, in the complementary MOS integrated circuit device according to the present invention, a plurality of complementary MOST pairs are arranged in parallel without providing a separation region between each pair, and a required number of the plurality of pairs is arranged in parallel. By configuring a logic functional element using a pair of and supplying a required voltage to each gate electrode of a complementary MOST pair adjacent to the logic functional element to disconnect it. Since it is electrically isolated from the rest of the unit, there is no need for wiring that connects unit cells across the isolation region as in the conventional method, and there is no need for unnecessary isolation regions. can be used effectively, the degree of integration of the device can be improved, and along with this, an improvement in operating speed can be expected.

[Brief explanation of the drawing]

Fig. 1 is a conceptual layout diagram of a gate array, Fig. 2 is a diagram showing an example of a conventional arrangement of unit cells, and Fig. 3 is a diagram illustrating a configuration of a 4-input NOR gate using this conventional example. , FIG. 4 is a layout diagram showing one embodiment of the present invention, and FIG. 5 is a configuration diagram when a four-input NOR gate is constructed using this embodiment. In the figure, 31a, 31b, 31c, and 31d are gate electrodes, 32a, 32b, 32c, and 32d are source or drain regions, 33 is an isolation region, 34 is a p-type region (n-channel MOST forming region), and 41 is a first layer. AI wiring,
31 is the A1 wiring of the second layer.

Claims (1)

[Claims] 1 A plurality of pairs each consisting of a p-channel MOS transistor and an n-channel MOS transistor are arranged so that the p-channel MOS transistor and the n-channel MOS transistor are in phase with each other for the pairs adjacent to each other without providing a separation region between each pair. The p-channel MOS transistors are arranged side by side and constitute a functional element having a logic function using a required number of pairs out of the plurality of pairs, and the p-channel MOS transistors of the pair adjacent to the functional element; The gate electrodes of the n-channel MOS transistors are held at a positive power supply potential and a negative power supply potential, respectively, and the p-channel MOS transistors and n-channel MOS transistors are
A complementary MOS integrated circuit device, characterized in that the functional element is electrically isolated from the rest by cutting off the S transistor.