JPS60196966A - Complementary type semiconductor device - Google Patents

Abstract

PURPOSE:To improve the degree of integration and increase the speed of operation by connecting a second metallic layer and a gate electrode through a contact hole bored to an insulating film in the vicinity of a boundary between a semiconductor substrate and the side end section of a well. CONSTITUTION:A wire is laid into a cell from an Al wiring 41 as an upper layer form the outside of the cell, and connected to a gate electrode 2a through an Al wiring 36b as a lower layer in a contact section B. Since both the Al wiring 41 as the upper layer and Al wirings 36a, 36b as lower layers and both the Al wirings 36a, 36b as the lower layers and gate electrodes 2a, 2b are connected on the same gate electrodes 2a, 2b on a boundary between a substrate 31 and the side end section of a P well 42, the degree of integration is improved. Since the gate electrodes 2a, 2b and the Al wiring 41 are brought into contact on an isolation region between the side end section of the well and the substrate, signals are transmitted over each gate on the P channel side or the N channel side at approximately the same speed and at the shortest distances, and the speed of operation can be increased.

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to a complementary semiconductor device, and particularly to a complementary field effect transistor (hereinafter referred to as 0M) using multilayer metal wiring technology.
related to O8FET).

[Technical background of the invention and its problems]

Conventionally, as a pattern layout of a small-scale circuit (cell) of a two-manufactured NOR gate 0MO8FET with one layer of metal (for example, i2), the one shown in FIG. 1 is known, for example. 1m and lb in the diagram are P-type FET and N-type FET, respectively.
It is. In the regions of both FETs Ja and Jb, gate electrodes 2h and 2b made of polycrystalline silicon, a part of which is used as wiring, and an output wiring #i3 made of polycrystalline silicon are formed, respectively. The gate electrodes 2h, 2
b can be input from either the P channel side or the N channel side of the cell, and the output wiring 3 can similarly output from either direction. A signal input from one channel can be wired through the other side while being used as a gate input to the FET (hereinafter, such a function is also referred to as "through gradient line").

In the P-type FET 1a, 4 and 5 are the source and drain, respectively, 6 is the source (or drain), and the gate electrode J between these sources and drains 4 to 6 is
a, 2b are gate electrodes 1m, 7b for P-type FET Ja
shows. Similarly, in N-type FETZb, 8m
, 8b is a source, 9 is a drain, a gate electrode 2h between the source, drain am, 8b, and 9, and 2b is a gate electrode 10m, 10b for the N-type FET Zb. The drain 5 of the P-type FET Ja and the drain 10 of the N-type FET Jb are connected by an A wire 11. This human wiring 11 is connected via a contact hole 12 to the aforementioned output wiring 3 made of polycrystalline silicon. In addition, in the same figure, 13h and 13b indicate the strings. Further, reference numeral 14 indicates a boundary line between the semiconductor substrate and the side edge of the well, and a well exists below this boundary line 14.

If a cell using an 0MO8FET having such a structure is expressed in logic, it will be as shown in FIG. In addition, 2 in the figure
1 indicates a cell. Further, such cells are usually used in a state in which a plurality of cell rows 22 in which cells 21 are arranged are arranged in parallel as shown in FIG. In addition, 23... in FIG. 3 are wiring areas, and these wiring areas 23... have a plurality of A
l wiring 24... is formed.

However, according to the 0MO8FET having the above-described structure, the gate electrodes 2m and 2b made of polycrystalline silicon are used for input in the cell 21, and the output wiring 3 and the material are made of polycrystalline silicon with high resistance. Because
It has the disadvantage that it is not suitable for high speed.

For this reason, recently, in order to increase the speed, A7i
A multilayer metal wiring technique using 27-layer wires or the like is used.

This technique attempts to form wiring using only two layers of metal (usually AI) in order to avoid the wiring resistance of polycrystalline silicon used for wiring other than gate electrodes.

Here, regarding the 0MO8FET using this technology,
This will be explained with reference to FIGS. 4 and 5.

In addition, Fig. 4 is a pattern layout diagram of the cell of the same transistor, Fig. 5 is an enlarged plan view of the contact part of Fig. 4,
FIG. 6 is a sectional view taken along the line X--X in FIG. 5, and the same members are given the same reference numerals and explanations are omitted. Reference numeral 31 in the figure is, for example, an N-type silicon substrate on which a P-type well (not shown) is formed. Gate electrodes 33a and 33b made of polycrystalline silicon are formed on this substrate 31 via a field oxide film 32, and serve as gate electrodes 7m and 7b for the P-type FET 1m, and gate electrodes 10h and 10h for the N-type FET lb. It is used as 10b. The gate electrode 33a.

On the ssb, a first Sin film 3 having contact holes 34 in parts of the gate electrodes 33m, 33b is formed.
5 are formed in the contact holes 34 . Arrangements a36m and 36b are formed. These A
For A layout @36&, 36b, the corresponding AA layout @36&, 36
A second sio having a 20th contact hole 37.0 in a part of b.

A film 38 is formed, and the second contact hole 37...
* are formed with upper layer A/wirings 39 m , 39 b , 40 connected to the Al wiring 36 *, 36 b. Note that 36c in the figure is the drain 5 on the P channel side and the N
This is the lower layer Ae wiring connected to the drain 9 on the channel side. Also, 36d.

36e is a power supply line consisting of 8Bs in the lower layer.

In the pattern layout shown in Figure 4, contact part A
For example, the input is from outside the cell to the upper A6 layout
39a into the cell, connected to the lower layer Al wiring 36b within the cell, and further arranged in this way p)'! s 6
b is connected to the gate electrode 33a for gate input. Further, the output is connected to the AA green wiring 39h in the upper layer than the first layer AJ wiring 36c connecting the drain 5 on the P channel side and the drain 9 on the N channel side, and is connected to the outside of the cell.

However, according to the pattern layout in Figure 4,
Since the upper layer Al gauze 39a, 39b and the lower layer AAt wiring 36m, 36b are connected at the contact part A, an extra space with a width L is created compared to the pattern layout shown in FIG. The cell area increases and the degree of integration decreases.

Further, gate electrodes 7m and 7b of mainly P-type FET Ja are provided on the silicon substrate 3 via a field oxide film 32.
, gate electrodes 33m, 3 made of polycrystalline silicon used as gate electrodes 10*, 10b of N-type FET 1b.
3b is formed, for example, when an input is made from the N-channel side, the signal is transmitted to the P-channel gate slower than that of the N-channel gate by the resistance of the polycrystalline silicon until it reaches the P-channel region. High-speed operation is hindered. This also applies when input is made from the P channel side.

[Purpose of the invention]

The present invention has been made in view of the above circumstances.

It is an object of the present invention to provide a complementary semiconductor device that can achieve high integration and high speed operation.

[Summary of the Invention] The present invention provides a semiconductor substrate having a well on its surface, a gate electrode, a first metal layer provided on the gate electrode with an insulating film interposed therebetween, and the first metal layer. a second metal layer provided on the layer through an insulating film, and the second metal layer and the gate electrode are opened in the insulating film near the boundary between the semiconductor substrate and the side edge of the well. This is intended to achieve the above-mentioned object by making a connection through a contact hole.

Specifically, the contact between the gate electrode and the group 1 and the second metal layer is made near the boundary between the side edge of the well and the substrate (separation region), which is essential for the formation of the 0MO8 transistor.
By providing a field oxide film on top of the gate electrode, the degree of integration is improved, and polycrystalline silicon is used for the gate electrode.
The main idea is to achieve high-speed operation by limiting the use only to the connection between the gate electrode and the metal layer.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIGS. 7 to 10. Here, Figure 7 shows the 0M of the two-man powered NOR gate.
A pattern layout diagram of a cell using O8FET, FIG. 8 is an enlarged view of the contact part B in FIG. 7, FIG. 9 is a sectional view taken along the Y-Y line in FIG. 8, and FIG. 10 is a logic tire in FIG. 7. gram diagram. Note that the same members as those shown in FIGS. 1 to 6 are given the same reference numerals, and the explanation thereof will be omitted.

Reference numeral 41 in the figure indicates an upper layer AJ wiring as a second metal layer that connects to the lower layer Al wiring 36m, 36b via a contact hole 37. This upper layer AJ wiring 4 and the lower layer AJ wiring 36a.

A contact hole 37 between the substrate 36b and a contact hole 34 between the lower layer AJ wiring 36m, 36b and the gate electrode 2m, 2b is formed between the substrate 3 and the well 4 on the surface of the substrate 31.
They exist on the same gate electrodes 2m and 2b on the boundary with the side end portions of 2.

In an 0MO8FET with such a structure, taking the contact part B as an example, the input is wired from outside the cell into the cell from the upper layer AJ wiring 41, and is connected to the gate electrode 2a at the contact part B via the lower layer An wiring 36b. Ru. Also,
The output is from the AA layer above the lower layer AA wiring 36a connecting the drain 5 on the P channel side and the drain 9 on the N channel side.
It is connected to the wiring 41 and wired outside the cell. Here, the aforementioned 0MO8FET cell 21 is used in a state where a plurality of cell rows 22 are arranged in parallel as shown in FIG.

According to the present invention, the upper layer A/wiring 41, the lower layer AJ wiring 36th, 36b, and the lower layer AJ wiring &:j
6a, 36b and the gate electrode 2a.

2b is connected via the field oxide film 32 on the same gate electrodes 2h and 2b on the boundary between the substrate 3 and the side edge of the P well 42.
Compared to the conventional CMO8FET shown in the figure, the degree of integration can be improved without using extra space.

Further, polycrystalline silicon is used as the gate electrode 7a.

Since the outside of 7b, 10m, and 10b is limited to connection with the upper layer A7 wiring 41, it is used as a through wiring to route the input signal in the cell from the P area to outside the N area or vice versa. In this case, there is no wiring resistance due to polycrystalline silicon, and high-speed operation can be achieved. Furthermore, as mentioned above, since the contact between the gate electrodes 2m and 2b and the upper layer AA wiring 41 is made on the separation region between the side edge of the well and the substrate, the contact between each gate on the P channel side or the N channel side is Signal transmission becomes almost the same speed and the shortest possible time, and high-speed operation can be achieved.

Furthermore, since the wiring area outside the cell is not used for the upper layer AA wiring 4 or the lower layer Ae wiring 36a, 36bl, etc., as shown in FIG. It is possible to extend the gate electrodes 7*, Ib, 10h, 10b, source, drain 4, 5.8m, 8b, 9 to the outside (outside the power supply AJ).

In addition, the CM 08FE-y according to the present invention has a contact hole 34 as shown in FIG.
, 37 may be arranged in a direction perpendicular to the main surface of the substrate 31. In this case, contact hole 3
The coincidence of 4.37 makes it easy to compare the layout with the above embodiment.

Further, in the above embodiment, a case has been described in which the connection between the upper layer and lower layer A wiring and the gate electrode is made on the boundary between the substrate and the side edge of the well, but the present invention is not limited to this. For example, these AA? The wiring and the gate electrode may be connected at some distance from the boundary line between the substrate and the well.

This point will be described in detail below with reference to pattern diagrams shown in FIGS. 14(a) and 14(b). Note that FIG. 5(a) shows the conventional case, and FIG. 6(b) shows the case of the present invention.

In addition, A in the figure indicates the distance from the side edge of the well to the region on the rewell surface (or substrate surface) where the source, drain region, and gate electrode can be formed, and B indicates the distance between the upper layer AJ wiring and the lower layer AJ wiring. A! The width required for wiring and gate electrode connection is
C indicates the distance from the side edge of the well to the edge of the contact hole. That is, if Yl is the sum of the width required for the separation area between the substrate and the well and the width required for the connection between the upper layer, lower layer A/wiring, and gate electrode, then in the conventional case, Y1 AX2 + BX2 2A + 2B ・...(1), and in the case of the present invention, Y2A+C---(2). Here, if ￥*<Y, then 2〇), from (2), C(A+2B) In other words, the distance from the side edge of the well to the end (farthest side) of the contact ball is the side edge of the well. When the distance to the region where the source, drain region, and gate electrode can be formed is smaller than the sum of twice the width required for the tangent to the soil layer, lower layer All wiring, and gate electrode, the integration degree of the cumulonite is The improvement becomes even more remarkable.

Further, in the above embodiment, A6 was used as the material for the first and second metal layers, but the material is not limited to this, and any metal with low resistance may be used.

[Effects of the Invention] As described in detail above, according to the present invention, it is possible to provide a complementary semiconductor device such as an 0MO8FET that can achieve high integration and high speed operation.

[Brief explanation of the drawing]

Figure 1 is a pattern layout diagram of a conventional 0MO8FET cell, Figure 2 is a logic diagram diagram of Figure 1, Figure 3 is a pattern layout diagram of the 0MO8FET cell shown in Figure 1 when it is mounted, and Figure 4 is a conventional 0MO8FET cell pattern layout diagram. A cell pattern layout diagram of A l 2 Jr4 wiring 'dj&'CMO8F'ET, Figure 5 is an enlarged plan view of the contact part of Figure 4,
FIG. 6 is a cross-sectional view taken along the line X-X in FIG. 5, and FIG. 7 is a 0MO8FET with an AJZ layer wiring structure according to an embodiment of the present invention.
Figure 8 is an enlarged plan view of the contact part in Figure 7, Figure 9 is a cross-sectional view along line Y-Y in Figure 8, and Figure 10 is the logic diagram in Figure 7. Diagrams, FIG. I1 is a pattern layout diagram of the 0MO8FET cell in FIG. 7 when it is mounted, FIG. 12 is a pattern layout diagram of the 0MO8FET cell according to another embodiment of the present invention, and FIG. CMO showing a state in which the second contact hole is aligned in a direction perpendicular to the main surface of the substrate
Sectional view of V section =≠=NE, Figure 14 (a) s (b)
are 0MO8 according to the conventional and other embodiments of the present invention, respectively.
It is an explanatory diagram for comparing the degree of integration with PET. 1m, Jb...FET, 4, 8a, 8b...Saw x, 5.
g...Drain, 6...Source (or drain),
7*, 7b, 10a, 10b...-gate electrode, 14.
φ9 boundary line, 21... Cell, 22... Cell row, 23... Wiring region, 3... N type silicon substrate, 32... Field oxide film, 34.37... Contact hole,
86h-36a, 39h. 39b, 40.41...A/wiring, 42...P well. Applicant's agent: Patent Attorney Dozu Hiko, Figure 11, Figure 13, Figure 3] Figure 14 (a) (b)

Claims (1)

[Claims] α) A semiconductor substrate having a well on its surface, a gate electrode, a first metal layer provided on the gate electrode with an insulating film interposed therebetween, and a second metal layer provided through an insulating film, and a contact formed in the insulating film between the second metal layer and the gate electrode near the boundary between the semiconductor substrate and the side edge of the well; A complementary semiconductor device characterized by connection via a hole. e) A first metal layer is interposed between the gate electrode and the second metal layer, thereby establishing a connection between the gate electrode and the second metal layer. Complementary semiconductor device. (3) A contact hole between the gate electrode and the ml metal layer and a contact hole between the first and second metal layers,
3. The complementary semiconductor device according to claim 2, wherein the complementary semiconductor device is provided on the same gate electrode near the boundary between the side edge of the well and the substrate. (4) The contact between the gate electrode and the first metal layer and the contact between the eleventh and second metal layers are made through respective contact holes aligned in a direction perpendicular to the main surface of the substrate. A complementary semiconductor device according to claim 3. G) The distance from the side edge of the well to the edge of the contact hole is equal to the distance from the side edge of the well to the region where the source, drain region, and gate electrode can be formed.
4. The complementary semiconductor device according to claim 1, wherein the value is smaller than the sum of AF;j, v;i and twice the width necessary for connection of the gate electrode. G) AJ! as the material for the first and second metal layers! A complementary semiconductor device according to claim 1, characterized in that the complementary semiconductor device uses: