JPS60183739A - Formation of multilayer interconnection - Google Patents

Abstract

PURPOSE:To enhance evenness of a multilayer interconnection by a method wherein after ions such as As, P, B, Ar, etc. are introduced into the surface of a thin film for wiring formed on a substrate, heat treatment is performed, and after patterning is performed, an interlayer insulating film is formed according to the CVD method, and a thin film for wiring is formed thereon. CONSTITUTION:After a film for wiring of Al-Si(1%) is evaporated wholly on the surface of an Si substrate, boron ions are implanted. The ion implanted Al(1%) film is etched using the etching liquid of phosphoric acid:nitric acid: acetic acid=3:0.17:0.6 to form the prescribed wiring pattern. After then, heat treatment is performed in a nitrogen atmosphere at 450 deg.C for 30min. Then, a silicon oxide interlayer insulating film is formed on the whole surface covering the Al-Si(1%) film, an OCD film is provided thereon at about 1,200Angstrom film thickness, and heat-treated in a nitrogen atmosphere at 400 deg.C. After then, etching is performed to provide a through hole, Al is evaporated wholly on the surface of the OCD film, and etched in the prescribed pattern to form a second layer wiring. Accordingly, a favorable multilayer interconnection can be formed, and reliability can be enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming multilayer thin films, and more particularly to a method for forming multilayer wiring for LSI, preferably MO8FET integrated circuits.

Conventionally, wiring for LSI, etc. is done by forming a thin film of conductive material such as AQ, AQ, -8i, etc. by vapor deposition or sputtering, forming a pattern, and then subjecting it to heat treatment at 400°C to 500°C. However, during heat treatment, hillock
It is known that a phenomenon in which protrusions called ) are formed and the surface smoothness is lost occurs. It has been reported that hillocks occur not only in AI but also in polysilicon and MO. When this hillock occurs, it becomes the root cause of disconnections due to electromigration, electrical short circuits between the first conductor layer and the second conductor layer in multilayer wiring, and further disconnections due to poor cover registration of the interlayer insulating film. Short circuits occur due to such problems, and this is a major obstacle to realizing multilayer wiring. In addition to the cause of hillocks, conventional methods have been unable to form good multilayer interconnections due to the poor flatness of the interlayer insulating film.

The present invention has been made in view of the above points, and it is possible to form a good multilayer wiring with a simple process regardless of the type of thin film forming material, improve its reliability, and create flat interlayer wiring. The purpose of this method is to be able to form a recording layer, thereby forming a WJ and a fine multilayer wiring pattern.

The structure of the present invention will be described below based on a specific example in which multilayer wiring is formed.

81 substrates using magnetron sputtering method
A 1% l-8i wiring film is coated on the entire surface with a thickness of approximately 600 OA. Thereafter, boron ions are implanted into this AQ-3i1%11 by an ion implantation method.

The ion implantation conditions were an acceleration of 50 KeV and an implantation amount per unit area of 1. The ion concentration near the surface, especially within 2000 A from the surface, is 5 x 10 ions/Ca. Particularly preferably 5×10 ion number/cn
? The following is -1-. The maximum value of ion concentration is 1 from the surface.
It is located near 000A. AQ-8 with ion implantation
j 1% membrane in phosphoric acid: nitric acid: acetic acid = 3:0.17:0.
A predetermined wiring pattern is formed by etching using No. 6 etching solution at a temperature of 42 degrees Celsius for about 2.5 minutes. Thereafter, heat treatment is performed at 450° C. for 30 minutes in a nitrogen atmosphere.

Next, cover the Q-8J 1% film formed in a predetermined pattern and apply an interlayer insulating film, silicon oxide, on the entire surface by low pressure CVD.
The film is formed to a thickness of about 8000 Å using the method. The reduced pressure at this time is 0, I Torr.

Next, 0CD (Tokyo Ohka product name) is provided to a thickness of about 120 OA on top of this interlayer insulation. Then, heat treatment is performed at 400° C. in a nitrogen atmosphere.

After this, etching is performed to create through holes.Next, Put-e and NahaQ are deposited on the entire surface of the OC:D and etched into a predetermined pattern to form two-layer [-1 wiring, In order to confirm the effect in this example of forming a film thickness of about 800 OA, SF:M (Sc dinninge1.ecjron
The results observed using a m1 microscope are shown in the attached drawings. Fig. 1(a) shows the metal structure of 41W when ion implantation is not performed at ΔQ-8j, 1%1, and Fig. 1(b) shows the case when I3 is ion-implanted at 1~50KeV, ]Xl0dose. FIG. 2 is a microphotograph showing the metallographic structure of the multilayer wiring when the interlayer insulating film is debossed by low-pressure CVD method. The width of the wiring pattern is 3Pm.
This is a micrograph showing the metallographic structure when
Figure 4 (a) shows the multilayer wiring created by the conventional method, and (b)
) are micrographs showing the respective metallographic structures when multilayer wiring is formed by the method of the present invention. 1st
The hillock on the AQ-3i 1% wiring surface in the figure is (b)
It hasn't happened at all. In Figures 2 and 3, the first
Good coverage of the interlayer insulating film on the interconnection film of the layer is obtained, no breakage occurs, and the surface of the interlayer insulating film is formed evenly. In addition, in FIG. 4(b), a multilayer wiring with a fine pattern without defects and good coverage is formed. As described above, in this example, extremely good multilayer wiring can be achieved by combining ion implantation, wet etching, forming an interlayer insulating film, and flattening the surface under the conditions described. I can do it.

In addition, in this example, AQ-3 was used as the material.
Although i 1% is used, the present invention is not limited to this material, and can also be applied to polysilicon, high melting point metals such as MO, or silicides of these metals. It is considered that the ion implantation conditions in this case may be approximately the same as those in this embodiment. Furthermore, in addition to the 3 ions, ions such as As, 2), and Ar can also be used. In addition, As and Ar are A]
Figures 5(a) and 5(g) show the results of SEM observation of the case where ions were implanted into the wiring. In (d), 50KeV,
], X 10 '' dose and 0.) shows the case where Ar is ion-implanted at 50 KeV, 6 1 Xl membrane g
Although the film thickness is about 6, the film thickness is not limited to this.

Furthermore, although the interlayer insulation 1t9J was formed using the reduced pressure C, V l) method, it can also be formed using the atmospheric pressure CVD method. Also,
Although the ion implantation method was used, it is also possible to use a reverse sputtering method, a plasma treatment, or the like. In addition, although it is preferable to perform the i12 flattening process, it is not absolutely necessary.

As described above, the present invention has the advantage that it is possible to form a good multilayer interconnection of a semiconductor device, improve its reliability, and facilitate implementation.

Further, as an interlayer in multilayer wiring, extremely flatness can be obtained, and fine patterns of multilayer wiring can be formed.

It goes without saying that the method of the present invention can be used not only for manufacturing the semiconductor device described above, but also for forming a thin IVA with excellent smoothness on any structure.

[Brief explanation of the drawing]

FIG. 1(a) is a micrograph showing the metallographic structure of an aluminum wiring without ion implantation, and FIG. 1(b) is a micrograph showing the metallographic structure of an aluminum wiring without ion implantation. FIG. 2 is a microphotograph showing the metallographic structure of aluminum wiring in the case of a multi-layer wiring with L-L glue bonding. FIG. 3 is a micrograph showing the metallographic structure of the interlayer insulating film.
FIG. 4 is a microscopic photograph showing the fully bent structure 41'lj structure when 1 m is coated, and FIG. The micrograph f (Fig. 5(a) and (1)) showing the respective metallographic structures when multilayer wiring is formed is an As
, A1- is a microscopic photograph showing the metallographic structure of aluminum wiring when ion-implanted. Patent applicant Ricoh (α) 4-:. (-b) (α) s121 (9) Procedural amendment dated 1987/71/60 Mr. Manabu Shiga, Director General of the Japan Patent Office■, Indication of the case 1982 Patent Application No. 39432 2, Name of the invention Multilayer wiring formation method 3. Person making the amendment (relationship with 'I) Patent applicant address 143 Tokyo 1111 people 111 ward Nakamagome - = 1
``No. 1143 6 Name (674,) Ricoh Co., Ltd. Attachment 2, Claims ii3 A process for forming a first Izz film made of a selected material on a composite body, and a process for forming a first Izz film made of a selected material on the surface of the thin film. Beg 1 so\also ΔS
, P, -13, Δr, etc., a step of treating the thin film, a step of drying the thin film, and a CVD process on the thin film. A step of forming an interlayer break () by a method, and a second layer consisting of a selected interest.
! i II; 'i;

Claims (1)

[Claims] forming a first thin film of the selected material on the structure; applying energy to the surface of the thin film to form As-P;
A step of introducing ions such as B, Ar, etc., a step of heat treating the thin film, a step of wet etching the thin film, a step of forming an interlayer insulating film on the thin film by CVD method, and a step of forming the selected material. A method for forming a multilayer wiring including a step of forming a second thin film comprising: