JPS60183727A - Contact hole forming method - Google Patents
Contact hole forming methodInfo
- Publication number
- JPS60183727A JPS60183727A JP3955884A JP3955884A JPS60183727A JP S60183727 A JPS60183727 A JP S60183727A JP 3955884 A JP3955884 A JP 3955884A JP 3955884 A JP3955884 A JP 3955884A JP S60183727 A JPS60183727 A JP S60183727A
- Authority
- JP
- Japan
- Prior art keywords
- opening
- insulating film
- film
- contact hole
- photoresist film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 24
- 238000005530 etching Methods 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 abstract description 5
- 239000000758 substrate Substances 0.000 abstract description 4
- 238000001312 dry etching Methods 0.000 abstract description 2
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
発明の技術分野
本発明は、半導体集積回路等の製造工程の一部となるコ
ンタクトホールの形成方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a method for forming contact holes that are part of the manufacturing process of semiconductor integrated circuits and the like.
従来技術と問題点
従来、半導体集積回路等の装造工程においてコンタクト
ホールを形成する場合、第１図の工程図に示すように５
図示しない能動細板が形成された半導体基板１の表−１
ｉｎを絶縁膜２で被扮し１次いでこの絶縁膜２上にコン
タクトホール形成用の開口を有するフォトレジスト膜６
を形成しく同図（、（１） 。Conventional technology and problems Conventionally, when forming contact holes in the manufacturing process of semiconductor integrated circuits, etc., five
Table-1 of semiconductor substrate 1 on which active thin plates (not shown) are formed
A photoresist film 6 is formed by covering the insulator with an insulating film 2, and then forming an opening for forming a contact hole on the insulating film 2.
The same figure (, (1)).
引続きこのフォトレジスト１模３をマスクとして用いエ
ツチングを行なって開口内の絶縁膜２を除去することに
よシ、コンタクトホール４を形成していた（同図ω））
。Subsequently, using this photoresist 1 pattern 3 as a mask, etching was performed to remove the insulating film 2 within the opening, thereby forming a contact hole 4 (ω in the same figure))
.
しかしながら上記従来方法によれば、コンタクトポール
周辺の傾斜が急峻になるため、同図（Ｃ）に示すように
配線層５を形成した場合、その厚み全十分太きくしない
とコンタクトホールの周辺部分において断線が生じ易く
なり、製造の歩留が低下するという問題があった。However, according to the above conventional method, the slope around the contact hole becomes steep, so when the wiring layer 5 is formed as shown in FIG. There was a problem in that wire breakage was likely to occur and the manufacturing yield was reduced.
発明の目的
本発明は、上記従来技術の問題点に鑑みてなされたもの
でちシ、その目的は２周辺部における断線か生じにくい
コンタクトホールの形成方法を提供することにある。OBJECTS OF THE INVENTION The present invention has been made in view of the problems of the prior art described above, and its purpose is to provide a method for forming a contact hole that is less likely to cause disconnection at two peripheral portions.
発明の構成
上記目的を構成する本発明は、絶縁膜上に第１の開口を
有する第１の７オトレジスト膜を形成し。Structure of the Invention In the present invention, which achieves the above object, a first photoresist film having a first opening is formed on an insulating film.
該第１のフォトレジスト膜上に、 ＭｉＩ記第１の開口
よシも大きな開口面積をイｊし該第１の開口を囲む第２
の開口を有する第２の７オトレジスト１換金形成し、該
第１．第２のフォトレジスト膜及び＋１２Ｌ：縁膜を、
第１の開口内の絶縁膜が完全に除去されるまで、エツチ
ングによシ厚み方向に除去しでゆくことにより２周辺部
の段々の傾斜がゆるやかなコンタクトポールを形成する
ように構成されている。An opening area larger than the first opening is formed on the first photoresist film, and a second opening surrounding the first opening is formed on the first photoresist film.
A second 7-hole resist 1 having an opening is formed, and the first . The second photoresist film and +12L: edge film,
By etching the insulating film in the first opening in the thickness direction until it is completely removed, a contact pole is formed with gradual slopes at the second peripheral part. .
以下１本発明の更に詳細を実施例によってｉ発明する。Further details of the present invention will be explained below by way of examples.
発ＢＪＪの実施例
第２図は本発明の一実施例の製造工程を素子壁部断面図
によって敵り」する図である。EMBODIMENT OF BJJ FIG. 2 is a diagram illustrating the manufacturing process of an embodiment of the present invention using a sectional view of an element wall.
まず（Ａ）に示すように、能動領域が形１戊された半シ
Ｒ体基板１の表面をＳｔ’０２もの絶縁ＩＮ！ ２で級
拐したのち、この絶縁膜２上に、フォトリングラフィ技
術を用いて所望の位置に所望の大きさの第１゛のｕｔＪ
口を翁する第１のフォトレジスト膜３−１を形成する。First, as shown in (A), the surface of the semi-circular substrate 1 with the active region cut out is insulated by St'02. 2, a first utJ of a desired size is formed on the insulating film 2 at a desired position using photolithography technology.
A first photoresist film 3-1 covering the mouth is formed.
次に（Ｂ）に示すように、第１のフォトレジスト膜６−
１上に、前記第１の開口よりも大きなυ（１０【ｒ！１
抗を有する第２のフォトレジスト膜６−２を形成する。Next, as shown in (B), the first photoresist film 6-
1, υ(10[r!1
A second photoresist film 6-2 having a resistive surface is formed.
この際、マスク合わせによシ第１．第２の開口の中心が
互いに１杢、なり合い、第２の０１１口が第１の開口を
囲むようにする。壕だ第１．第２のフォトレジスト膜の
相賀は同神であっても異才ｙ１・であってもよい。At this time, please check the mask alignment first. The centers of the second openings are one square inch apart from each other, and the second 011 opening surrounds the first opening. First, it's a trench. The Aiga of the second photoresist film may be the same god or the different talent y1.
次に（（°）に示すように、ンｔ・オンガス等を用いて
ドライエツチングを行ない、第１の開口内の絶縁膜２が
完全に除去されるまで、第１のフォトレジスト膜３−１
．第２のフォトレジスト膜３−２及び絶縁膜２の厚みを
減じてゆく。−例として、第１のフォトレジスト膜３−
１と第２のフォトレジスト膜３−２のに−みをいずれも
１μｍとし、さらに絶縁膜２の厚みを２μｍとし／ヒ場
合、これら三者に幻するエツチング速度がはＩ￥鵠しく
なるようなエツチング条件のもとて約６０分間エツチン
グすると、開口４の周辺部における絶縁膜の段差の厚み
かもとの厚みのｅよは半分であるような、ゆるやがな傾
斜をもった周辺部が形成される。Next, as shown in (°), dry etching is performed using an on gas or the like, and the first photoresist film 3-1 is etched until the insulating film 2 in the first opening is completely removed.
．． The thicknesses of the second photoresist film 3-2 and the insulating film 2 are gradually reduced. - As an example, the first photoresist film 3 -
When the thickness of the photoresist film 1 and the second photoresist film 3-2 is both 1 μm, and the thickness of the insulating film 2 is 2 μm, the etching speed of these three becomes much larger. After etching for about 60 minutes under suitable etching conditions, a gently sloping periphery is formed in which the step thickness of the insulating film at the periphery of the opening 4 is half the original thickness. It is formed.
次いで、エツチング条件によっては絶縁膜５上に残留し
ている第２のフォトレジスト膜６−２を。Next, depending on the etching conditions, the second photoresist film 6-2 remaining on the insulating film 5 is etched.
硫酸等によ）溶角′ｆ除去したのち、（Ｄ）に示すよう
に配線層５を形成する。コンタクトホール周辺部におけ
る配＆！ｆｖ４５の傾斜は上記段差の分だけ緩和され、
それだけ断線が生じにくくなる。After removing the melt angle 'f (using sulfuric acid, etc.), a wiring layer 5 is formed as shown in (D). Distribution &! around the contact hole! The slope of fv45 is eased by the amount of the above step,
This makes disconnection less likely to occur.
発明の効果
本発明は、上述のような（１４成によシコンタフｉ・ホ
ール周辺部の傾斜を緩和できるので配勝層の断線か生じ
に＜＜１歩留りが向上するという効北がある。Effects of the Invention The present invention has the effect of improving the yield by 1% in reducing the occurrence of breakage in the distribution layer because the slope of the periphery of the Sicontough I-hole can be alleviated as described above.
第１図は従来の工程を示す図、第２図は本発明の一実施
例の工程を示す図である。
１・・・半導体基板、２・・・絶に膜、６・・・フォト
レジストＩＬ４・・コンタクトホール、５・・・ｔｓ己
勝ｔｗ。
特許出願人 住友電気工業株式会社
第１０ 第２図FIG. 1 is a diagram showing a conventional process, and FIG. 2 is a diagram showing a process of an embodiment of the present invention. 1...Semiconductor substrate, 2...Absolutely film, 6...Photoresist IL4...Contact hole, 5...ts self-defense tw. Patent applicant Sumitomo Electric Industries, Ltd. No. 10 Figure 2
Claims (1)
を形成し、該第１のフォトレジスト膜上に＋ ｎ’ｊ記
第１の開口よシも大きな開口面積を有し該第１の開口を
囲む第２の開口を有する第２のフォトレジスト膜を形成
し、該第１．第２のフォトレジスト膜及び前記絶縁膜を
、前記第１の庚」口内の絶縁膜が完全に除去される才で
、エツチングによシ厚み方行に除去していくことを特徴
とするコンタクトホールの形成方法。A first photoresist film having a first opening is formed on the absolute R film, and a first photoresist film having a larger opening area than the first opening described above is formed on the first photoresist film. forming a second photoresist film having a second opening surrounding the first opening; A contact hole characterized in that the second photoresist film and the insulating film are removed in the thickness direction by etching so that the insulating film in the first hole is completely removed. How to form.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3955884A JPS60183727A (en) | 1984-03-01 | 1984-03-01 | Contact hole forming method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3955884A JPS60183727A (en) | 1984-03-01 | 1984-03-01 | Contact hole forming method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60183727A true JPS60183727A (en) | 1985-09-19 |
Family
ID=12556398
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3955884A Pending JPS60183727A (en) | 1984-03-01 | 1984-03-01 | Contact hole forming method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60183727A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100414949B1 (en) * | 1996-12-28 | 2004-03-31 | 주식회사 하이닉스반도체 | Method for forming contact hole of semiconductor device |
-
1984
- 1984-03-01 JP JP3955884A patent/JPS60183727A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100414949B1 (en) * | 1996-12-28 | 2004-03-31 | 주식회사 하이닉스반도체 | Method for forming contact hole of semiconductor device |
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