JPS60181939A - トライステ−ト回路の制御方式 - Google Patents
トライステ−ト回路の制御方式Info
- Publication number
- JPS60181939A JPS60181939A JP59037818A JP3781884A JPS60181939A JP S60181939 A JPS60181939 A JP S60181939A JP 59037818 A JP59037818 A JP 59037818A JP 3781884 A JP3781884 A JP 3781884A JP S60181939 A JPS60181939 A JP S60181939A
- Authority
- JP
- Japan
- Prior art keywords
- state
- group
- tri
- circuit
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/263—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59037818A JPS60181939A (ja) | 1984-02-29 | 1984-02-29 | トライステ−ト回路の制御方式 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59037818A JPS60181939A (ja) | 1984-02-29 | 1984-02-29 | トライステ−ト回路の制御方式 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60181939A true JPS60181939A (ja) | 1985-09-17 |
| JPS6363929B2 JPS6363929B2 (enExample) | 1988-12-09 |
Family
ID=12508099
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59037818A Granted JPS60181939A (ja) | 1984-02-29 | 1984-02-29 | トライステ−ト回路の制御方式 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60181939A (enExample) |
-
1984
- 1984-02-29 JP JP59037818A patent/JPS60181939A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6363929B2 (enExample) | 1988-12-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5509019A (en) | Semiconductor integrated circuit device having test control circuit in input/output area | |
| US6861866B2 (en) | System on chip (SOC) and method of testing and/or debugging the system on chip | |
| US5012185A (en) | Semiconductor integrated circuit having I/O terminals allowing independent connection test | |
| JP3565863B2 (ja) | Jtagの高インピーダンス試験モード | |
| US4862068A (en) | LSI logic circuit | |
| US5134314A (en) | Automatic pin circuitry shutoff for an integrated circuit | |
| JP3262033B2 (ja) | 半導体記憶装置 | |
| JPS6068624A (ja) | Lsiの自己検査装置 | |
| JPH05259878A (ja) | トライステート制御回路 | |
| US4335425A (en) | Data processing apparatus having diagnosis function | |
| JPH0394183A (ja) | 半導体集積回路の試験方法及び回路 | |
| JPH06105285B2 (ja) | 半導体集積回路装置 | |
| US4973904A (en) | Test circuit and method | |
| US6990076B1 (en) | Synchronous bi-directional data transfer having increased bandwidth and scan test features | |
| JPS61155874A (ja) | 大規模集積回路の故障検出方法およびそのための装置 | |
| JPS60181939A (ja) | トライステ−ト回路の制御方式 | |
| JP3465351B2 (ja) | スキャンパステスト用フリップフロップ回路 | |
| JP2648001B2 (ja) | 半導体集積回路 | |
| EP0502210B1 (en) | Semiconductor integrated circuit device with testing-controlling circuit provided in input/output region | |
| US6822439B2 (en) | Control of tristate buses during scan test | |
| JP2877505B2 (ja) | Lsi実装ボード及びデータ処理装置 | |
| JPH0766030B2 (ja) | 論理パッケージの診断方法 | |
| JPS6095370A (ja) | 集積回路装置 | |
| JP2001004713A (ja) | 半導体集積回路のテスト回路 | |
| JPH0599980A (ja) | ピンスキヤンイン型lsi論理回路および回路実装基板試験方法 |