JPS60180314A - Delay circuit - Google Patents

Abstract

PURPOSE:To miniaturize the circuit and to set easily the delay time by providing a full band transmission filter comprising inductances connected in series and a capacitor connected in parallel with the midpoint of the inductances between stages of inverting gates consisting of an emitter coupling logical circuit giving a prescribed time of delay to a signal string between the inverting gate stages. CONSTITUTION:The full band transmission filter 11 is provided in place of a coaxial cable and sets an optional delay time of nearly ns (nano sec) to high- speed data inverted by the emitter coupling logical (EOL) circuit. The capacitor 22 is connected in parallel with the midpoint of the inductances L211, L212 connected in series and grounded in the full band transmission filter 11. The filter 11 is characterized in that the amplitude is transmitted as it is over the entire frequency range and only the phase is shifted, allowing to set a prescribed delay time. A desired delay time is obtained by providing the full band transmission filter to the inter-stage of the ECL circuit and setting optionally the constant and it is easy to change the delay time. Since the filter is formed by combining high frequency LC, the circuit is miniaturized.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a small-sized delay circuit provided between an inverting gate constituted by a BOL circuit and capable of easily setting a delay time.

(2) Prior art and problems Conventionally, EOL (emitter-coupled logic) circuits are often used, especially as high-speed data inverting circuits. In this case, a delay circuit is provided between multiple BOL circuits, and a binary signal string Conventionally, a coaxial cable is used when a predetermined delay time is to be provided between the emitter of the output transistor of the EOL circuit 1 and the BOL. A coaxial cable 3 is provided between the base of the input transistor of the circuit 2. However, with this method, when changing the delay time, the coaxial cable had to be replaced and the mounting space was taken up. There were drawbacks such as increased size.

(3) Object of the Invention An object of the present invention is to provide a small-sized delay circuit which is provided between stages of inverting gates constituted by an EOL circuit and whose delay time can be easily set.

(4) Structure of the Invention In order to achieve the above object, the delay circuit of the present invention consists of an inductance connected in series and a capacitor υ connected in parallel to the midpoint of the inductance between the stages of an inverting gate made of an emitter-coupled logic circuit. The present invention is characterized in that an all-pass filter is provided to delay the signal train between the inverting gate stages for a predetermined period of time.

(5) Examples of the invention FIG. 2 is an explanatory diagram of the configuration of an embodiment of the present invention.

As shown in the same figure, in the present invention, the coaxial cable 6 of FIG.
Instead, an all-pass filter 11 as detailed in FIG. 3 is provided, and an arbitrary ns
It is possible to easily set a delay time on the order of (nanoseconds).

FIGS. 3(tz) and 3(b) show a detailed block diagram of the all-pass filter which is the main part of the present invention) and an equivalent circuit (b).

As shown in the figure (α), the all-pass filter 11 has a capacitor 22 connected in parallel to the midpoint of the series-connected inductances (L) 211 and 212 and grounded. The feature of this filter 11 is that it allows the amplitude to pass through the entire frequency range as it is and shifts only the phase, so that a constant delay time can be set. Let the input and output impedances on both sides of the filter be R, and the inductance LIIL
The equivalent circuit when the mutual inductance between the two is M is shown in FIG.

The all-pass filter 1 itself is a known technique, and the result of approximate calculation with L=M for the equivalent circuit is expressed by the following equation.

τ(ω)=zu Tomoe"-((8)〕(1) ωδ1ω2 L=-(2) 2"O 6=jiL(3) 0 here to τ); Delay time ω; Use Frequency ω0; cutoff frequency R; input/output car impedance In the case of a rectangular wave, the rise and fall of the waveform is determined by the third harmonic, so τ is set as three times the frequency used.

First, substitute τ (c) and ω into equation (1) to find ω0, and then calculate ω into equations (2) and (3). , R is substituted and O is substituted.

This will be explained below by giving an example.

Now, if we set (1) = 16.384 [MB2],
Since the sono period is 61 na, if it is delayed by 900, then 7 C→==61 ns x1=15 [ns] Substitute this into equation (1).

From this, ωo = 163.5 (MHz) is obtained (R = 1 (set)). Conversely, an all-pass filter is provided with input and output impedances R and 0, and L, By setting O arbitrarily, a desired delay time τ←) can be obtained.

(6) As described in detail, according to the present invention, a desired delay time can be obtained by providing an all-pass filter between the stages of the EOL circuit and arbitrarily setting this constant. It is also easy to change.

Furthermore, since it is formed using a combination of glue for high frequencies of about MHz, for example, it is possible to form it into an extremely small size.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram of a conventional example, Fig. 2 is an explanatory diagram of the configuration of an embodiment of the present invention, and Figs. 3 (α) and (b) are detailed explanatory diagrams of the main parts of Fig. 2. In the figure, 1 and 2 are EOL circuits, and 11 is an all-pass filter. Patent applicant: Fujitsu Limited, sub-agent patent attorney 1) Yoshishige Saka

Claims (1)

[Claims] An all-pass filter consisting of an inductance connected in series and a capacitor connected in parallel to the midpoint of the inductance is provided between the stages of the inverting gate constituted by the emitter-coupled logic circuit, and the signal train between the stages of the inverting gate is transmitted for a predetermined period of time. A delay circuit characterized by causing a delay.