JP2845439B2 - Integrated circuit having driver circuit for internal clock signal line - Google Patents

Description

The present invention relates to an integrated circuit having an internal clock signal line driver circuit suitable for stable operation of an ultra-high frequency clock. [Prior Art] Conventionally, many integrated circuits have a driver circuit for an internal clock signal line in addition to an external clock input terminal. In recent years, in integrated circuits, due to higher integration and larger chips, the line length of the internal clock signal line and the wiring (wiring) impedance between the external clock input terminal and the internal clock signal line driver circuit have been reduced. Increase,
Further, the clock frequency is also higher. As shown in FIG. 3, when a clock signal line or a general signal line is regarded as a distributed constant line having a resistance per unit length of R, an inductance of L, and a capacitance of C, its voltage V
And the current I has the relationship shown in the following equations (1) and (2). (DV / dx) = − ZI (1) (dI / dv) = − YV (2) where Z = R + jωL, Y = jωC, and ω are angular frequencies. The above equations (1) and (2) are obtained by calculating I = I at the end (x = 1) of the line.
0 and x = 0 and solving by setting V = V ₀ becomes the boundary condition,
The voltage V (x) and the current I (x) at the point x are represented by the following equations (3) and (4). V (x) = {V ₀ / (1 + e ^2γl )} (e ^2γl−γx
+ E ^γx ) (3) I (x) = {γV ₀ / Z (1 + e ^2γl )} × (e
^{2γl-γx -e γx) ... (} 4) ^{where, γ = (ZY) 1/2 =} α + jβ α = ^{[ωC {(R 2 + ω 2} L 2) 1/2 -ωL} / 2 ] ^1/2 beta = {ΩC (R ² + ω ² L ² + ωL) ^1/2 / 2} ^{1/2 From} these equations, the higher the frequency f (= ω / 2π) and the greater the capacitance C and the resistance R, the more It can be seen that α (attenuation constant) increases and β (phase constant) also increases. As a result, when the line length l is large, the high-frequency component at the end of the line has a large phase shift and a large attenuation of the amplitude. FIGS. 4A, 4B and 4C are schematic diagrams showing a clock signal line 8 and its driver circuit 7 in a conventional integrated circuit. The clock signal line 8 in FIG. 4A does not form a loop, and the clock signal lines 8 in FIGS. 4B and 4C both form a loop. The clock signal input to the external clock input terminal 9 is supplied to the clock signal line 8 via the driver circuit 7. It is assumed that the entire length of the clock signal line 8 is the same for all of FIGS. 4 (a), (b) and (C). For example, assuming that the clock signal line 8 is a chip of a square having a side of 12 mm and the clock signal line 8 goes around the periphery of the chip, the total length of the clock signal line 8 is 48 mm. In the case of a loop-shaped signal line, when a signal is injected from one position of the loop, the loop midpoint (where l is the total length of the loop, a point located at l / 2 from the signal injection point)
It is known electromagnetically to behave the same as a signal injection point. Accordingly, the line length l (the length of a line through which a signal is substantially transmitted by one driver circuit) shown in FIG. 3 is 1 = 48 mm in the circuit shown in FIG.
In the circuit shown in FIG. 4B, l = 24 mm (that is, the length to the loop midpoint), and in the circuit shown in FIG. ). FIG. 5 shows that for a square wave with a frequency f of 50 MHz, x = 0
The waveform at the point (solid line) and FIGS. 4 (a), (b),
As shown in (c), when the line length l is 48 mm, 24 mm, and 12 mm, each waveform at the point x = 1 (shown by a two-dot chain line, a one-dot chain line, and a dashed line, respectively) is expressed by the above equation (3). FIG. 5 is a graph showing and obtaining the fifth harmonic component by using FIG.
In FIG. 5, the horizontal axis represents time, and the vertical axis represents voltage (expressed as an exponent). When the end of the clock signal line is released, a standing wave is generated due to interference between the injected signal and the signal reflected at the end. When the clock signal line forms a loop, it can be considered as a signal transmission line in which the end of the line length l is released. Therefore, FIG. 4 (a),
Harmonic components occur in the clock signal lines of (b) and (c). As apparent from FIG. 5, the signal attenuation and phase shift at the line ends (x = 1) of the circuits in FIGS. 4 (a), (b) and (c) have a shorter line length l. It is getting smaller. In particular, when two clock signal line driver circuits 7 are provided as in the circuit shown in FIG. 4C, the attenuation and phase shift of the clock from the original signal are extremely small. As is clear from the relationship between the line length 1 and the attenuation and the phase shift shown in FIG. 5, the attenuation and the phase shift from the original clock signal are further reduced by further increasing the number of drivers for the clock signal line. Can be smaller. [Problems to be Solved by the Invention] However, in a conventional integrated circuit having a clock signal line driver circuit, the number of external clock input terminals is limited to one. However, the distance from the external clock input terminal to each driver circuit cannot always be the same. Therefore, the wiring impedance between them is not the same.
Therefore, in an integrated circuit having a large chip size, the delay and attenuation of the clock from the clock input terminal to each driver circuit are different for each wiring. In particular, when the clock has a high frequency, the difference between the delay and the amount of attenuation between the wirings becomes even more remarkable. As described above, even if a plurality of driver circuits are provided, since there is a phase difference between the input signals of the respective driver circuits, there is a problem that the amplitude attenuation and the phase shift in each part of the clock signal line become large. There is. SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and provides an internal clock signal line driver circuit capable of suppressing a phase shift and attenuation of an internal clock signal line even in a high-frequency integrated circuit having a huge chip size. It is an object to provide an integrated circuit having the same. [Means for Solving the Problems] According to the present invention, the external clock input terminal and the external clock input terminal are arranged at positions where the internal clock signal line is equally divided with respect to the internal clock signal line formed in a loop. A plurality of internal clock signal line driver circuits for supplying an input clock, and a plurality of wirings for connecting the external clock input terminal and the plurality of internal clock signal line driver circuits; The plurality of wirings have substantially the same delay time, and the output of the internal clock signal line driver circuit has the same attenuation and phase shift. [Operation] In the present invention, a clock supplied to an external clock input terminal is input to a plurality of internal clock signal line driver circuits via a plurality of wirings. Since a plurality of wirings have substantially the same wiring impedance between the external clock input terminal and the internal clock signal line driver circuit, the clocks have the same amount of attenuation and the same phase shift, and the It is input to the clock signal line driver circuit. Therefore, the outputs of all the internal clock signal line driver circuits have the same attenuation and phase shift.
In addition, the plurality of internal clock signal line driver circuits are divided at equal positions with respect to the loop-shaped internal clock signal lines (for example, when three driver circuits are provided, the loop-shaped internal clock signal lines are connected to each other). The clock is supplied from the position (divided into three equal parts). The clock supplied from each driver circuit is attenuated and shifted in phase while propagating through the internal clock signal line, but the line length (the length of the line through which a signal is substantially transmitted by one driver circuit) ) Is short,
Clock attenuation and phase shift in each part of the internal clock signal line are reduced. Further, since the clocks supplied from the driver circuits to the internal clock signal line have the same attenuation and the same phase, even if a plurality of clocks are supplied to the internal clock signal line, overlapping of the clocks can be avoided. . Embodiment An embodiment of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a circuit diagram showing a clock signal line and a driver circuit in an integrated circuit having an internal clock signal line driver circuit according to a first embodiment of the present invention.
The clock input to the external clock input terminal 5 is input to the driver circuit 1 provided near the external clock input terminal 5 via the input buffer 4 and the wiring 10, and
The signal is input to the driver circuit 2 disposed far from the external clock input terminal 5 via the input buffer 4 and the wiring 11. The clock signal line 8 is formed in a loop shape, and the output terminals of the driver circuits 1 and 2 are connected to positions where the loop is divided into two. The clock signal line 8 is supplied with a clock from the driver circuits 1 and 2. Wiring 10 is wiring 1
1 has a line length substantially equal to that of the input buffer 4 and the driver circuit 1, and the wiring distance between the input buffer 4 and the driver circuit 2 is shorter than the wiring distance between the input buffer 4 and the driver circuit 2. And the driver circuit 1. Note that the wiring 10 and the wiring 11 have the same width. Next, the operation of the integrated circuit configured as described above will be described. The clock signal input to the external clock input terminal 5 is input to the wiring 10 and the wiring 11 via the input buffer 4. The clock input to the wiring 10 is slightly attenuated before being input to the driver circuit 1 and the phase is shifted. Similarly, the clock input to the wiring 11 is also slightly attenuated, and is input to the driver circuit 2 with a phase shift. In this case, since the line lengths and widths of the wirings 10 and 11 are substantially the same, the clock attenuation and phase shift by the wiring 10 and the clock attenuation and phase shift by the wiring 11 are the same. Therefore, the waveforms and phases of the outputs of the driver circuits 1 and 2 are the same. Clock signal line 8
Since the clock is supplied from the position where the loop is divided into two by such two driver circuits, the attenuation and the phase shift of the clock in each part of the clock signal line 8 are extremely small. FIG. 2 is a circuit diagram showing a clock signal line and a driver circuit in an integrated circuit having an internal clock signal line driver circuit according to a second embodiment of the present invention. In FIG. 2, the same components as those in FIG. The clock input from the external clock input terminal 5 is input to the driver circuit 3 disposed near the external clock input terminal 5 via the input buffer 14 and the wiring 4. The clock input to the input terminal 5 is input to the driver circuit 1 via the input buffer 4 and the wiring 12, and is also input to the driver circuit 2 via the input buffer 4 and the wiring 13. The clock signal line 8 is formed in a loop shape, and the output terminals of the driver circuits 1, 2, and 3 are connected to positions where the loop is equally divided into three. The clock signal line 8 is supplied with a clock by the driver circuits 1, 2, and 3. The capacitor component to the wiring 14 is C _L capacitor 6
Are added so as to be distributed over the entire length of the wiring 14. The length and width of the wiring 12 and 13 are both formed respectively l ₀ and w _0. The length of the wiring 14 is l ₁ and the width is w ₀ . Now, let the capacitance per unit length of the wirings 12 and 13 be C ₀ ,
When the capacitance per unit length of the wiring 14 and C _1, as the following equation (5) is satisfied, it is possible to determine the value of the capacitance C _L. l ₀ (C ₀ ) ^1/2 = l ₁ (C ₁ + C _L ) ^1/2 (5) As described above, the capacitance C _L of the capacitor 6 added to the wiring 14 is calculated by the above equation (5). By setting so as to satisfy, the external clock input terminal 5 can be connected to each driver circuit 12,3.
The wiring impedances of the wirings 12 to 14 are substantially the same, and the clock attenuation and the phase shift in the wirings 12 to 14 are the same. Further, in the circuit of the present embodiment, the number of driver circuits is increased by one compared with the circuit of the first embodiment, so that the clock attenuation and the phase shift in each part of the clock signal line 8 are further reduced. [Effects of the Invention] As described above, according to the present invention, the wiring impedance from the external clock input terminal to the internal clock signal line driver circuit is substantially the same for all the wirings. Clocks with the same attenuation and phase shift are input to the line driver circuit. Therefore, in the loop-shaped internal clock signal lines to which the clocks are supplied from the plurality of internal clock signal line driver circuits, the phase shift and the attenuation are extremely small. Therefore, it is possible to operate stably even if the clock of the integrated circuit has a very high frequency.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing a clock signal line and a driver circuit in an integrated circuit according to a first embodiment of the present invention, and FIG. 2 is a clock according to a second embodiment of the present invention. FIG. 3 is a schematic diagram showing a distributed constant line, FIGS. 4 (a) to (c) are schematic diagrams showing a clock signal line and a driver circuit, and FIG. 5 is a frequency f. FIG. 11 is a graph showing a waveform obtained by taking into account the attenuation and phase shift of a square wave of = 50 MHz up to the fifth harmonic component. 1, 2, 3, 7; driver circuit, 4; input buffer, 5, 9; external clock input terminal, 6; capacitor, 8; clock signal line, 10 to
14; wiring

Claims (1)

(57) [Claims] An external clock input terminal and a plurality of internal clock signal lines for supplying a clock input from the external clock input terminal at a position where the internal clock signal line is equally divided with respect to the internal clock signal line formed in a loop shape Driver circuit, and a plurality of wirings for connecting the external clock input terminal and the plurality of internal clock signal line driver circuits, wherein the plurality of wirings have delay times substantially equal to each other. An integrated circuit having an internal clock signal line driver circuit, wherein the output of the internal clock signal line driver circuit has the same attenuation and phase shift.