JPS60180206A - High frequency signal processor - Google Patents
High frequency signal processorInfo
- Publication number
- JPS60180206A JPS60180206A JP59036429A JP3642984A JPS60180206A JP S60180206 A JPS60180206 A JP S60180206A JP 59036429 A JP59036429 A JP 59036429A JP 3642984 A JP3642984 A JP 3642984A JP S60180206 A JPS60180206 A JP S60180206A
- Authority
- JP
- Japan
- Prior art keywords
- mixer
- terminal
- output
- circuit
- high frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/14—Balanced arrangements
- H03D7/1425—Balanced arrangements with transistors
- H03D7/1433—Balanced arrangements with transistors using bipolar transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/14—Balanced arrangements
- H03D7/1425—Balanced arrangements with transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/14—Balanced arrangements
- H03D7/1425—Balanced arrangements with transistors
- H03D7/1458—Double balanced arrangements, i.e. where both input signals are differential
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D2200/00—Indexing scheme relating to details of demodulation or transference of modulation from one carrier to another covered by H03D
- H03D2200/0001—Circuit elements of demodulators
- H03D2200/0025—Gain control circuits
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Superheterodyne Receivers (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明ｉ′ｉ、チューナーやコンバータに使用されるミ
キサー及びそれに続く中間周波増幅器を集積回路で構成
する場合の高周波信号処理装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention i'i relates to a high frequency signal processing device in which a mixer used in a tuner or a converter and an intermediate frequency amplifier following the mixer are constructed from an integrated circuit.
従来例の構成とその問題点
まず第１図に高周波信号の処理に関する部分のブロック
図を示す。第１図において、１は局部発振器、２はＲＦ
倍信号増幅する部分で、局部発振器１、高周波増幅器２
の信号は３のミキサー（混合器）により混合され、高周
波増幅器２のＲＦ倍信号局部発振器１と高周波増幅器２
の差の周波数（中間周波数）に変換され、中間周波増幅
器（以下ＩＦアンプと略称する）４によシ増幅され出力
される。Configuration of a conventional example and its problems First, FIG. 1 shows a block diagram of a portion related to high frequency signal processing. In Figure 1, 1 is a local oscillator, 2 is an RF
In the part that doubles the signal, local oscillator 1, high frequency amplifier 2
The signals are mixed by a mixer (mixer) 3, and the RF multiplied signal of the high frequency amplifier 2 is sent to the local oscillator 1 and the high frequency amplifier 2.
It is converted into a frequency (intermediate frequency) that is the difference between
最近では、デバイス技術の向上により、このようなチュ
ーナ回路のＩＣ化が一般的に行われるようになってきて
おり、その中でミキサーとＩＦ７７７部のＩＣ化の従来
例を第２図に示す。第２図において、トランジスタＱ１
〜Ｑ６によりダブルバランス型ミキサーを構成し、図中
端子■゛、■より局部発振信号を人力し、端子■、■よ
りＲＦ倍信号印加し、そのミキサー出力はトランジスタ
Ｑ、 、Ｑ３及びトランジスタＱ２．Ｑ４のコレクタよ
りバランス出力として取出され、次段のＩＦアンプＱ、
、 Ｑ６のベースに印加される。ＩＦアンプＱ２．Ｑ
ｅのコレクタはＩＣの外部だタンク回路６を通し差動出
力として取り出される１本従来例においては、Ｑ、〜Ｑ
４のミキサー出力が直接Ｑ、 、 Ｑ６のＩＦアンプに
接続されているため、ミキサーの利得は固定化され、ま
たミキサー。Recently, with the improvement of device technology, it has become common to integrate such tuner circuits into ICs, and FIG. 2 shows a conventional example of IC integration of a mixer and an IF 777 section. In FIG. 2, transistor Q1
~Q6 constitutes a double-balanced mixer, in which a local oscillation signal is manually input from terminals ■゛ and ■ in the figure, and an RF multiplied signal is applied from terminals ■ and ■, and the output of the mixer is transmitted to transistors Q, , Q3, and transistors Q2. It is taken out as a balanced output from the collector of Q4 and sent to the next stage IF amplifier Q,
, applied to the base of Q6. IF amplifier Q2. Q
The collector of e is external to the IC and is taken out as a differential output through a tank circuit 6. In the conventional example, Q, ~Q
Since the mixer outputs of 4 are directly connected to the IF amplifiers of Q, , and Q6, the gain of the mixer is fixed, and the mixer output is also fixed.
ＩＦ段の間にフィルタを挿入したい場合にも設計的な自
由度がないという不都合がある。Even when it is desired to insert a filter between the IF stages, there is a disadvantage that there is no freedom in design.
発明の目的
本発明は、このようなミキサーからＩＦアンプに至るＩ
Ｃ化された高周波信号処理回路において、その設計的自
由度を与えるように構成することを目的とするものであ
る。Purpose of the Invention The present invention provides an I/O system ranging from such a mixer to an IF amplifier.
The purpose of this invention is to configure a C-based high frequency signal processing circuit so as to provide a degree of freedom in its design.
発明の構成
本発明による高周波信号出力装置は、ダブルノ・ランス
型ミキサーと、このミキサーの出力」］［に接続される
ところのエミッタホロア回路とを集積回路にて構成し、
上記ミキサーの差動出力の２つの共通コレクタの一方の
みを集積回路の外部に引出す端子、およびこの端子より
外部回路を経て上記エミッタホロア回路に入力するため
の端子をそれぞれ上記集積回路に設けるようにしたもの
であり、ミキサーの利得の調整が行なえ、またフィルタ
等の挿入も可能となり、設計の自由度が増すという利点
を有する。Structure of the Invention The high-frequency signal output device according to the present invention comprises a double-no-Lance type mixer and an emitter follower circuit connected to the output of this mixer using an integrated circuit,
The integrated circuit is provided with a terminal for drawing out only one of the two common collectors of the differential output of the mixer to the outside of the integrated circuit, and a terminal for inputting from this terminal to the emitter follower circuit via an external circuit. This has the advantage that the gain of the mixer can be adjusted and filters etc. can be inserted, increasing the degree of freedom in design.
実施例の説明
第３図に本発明の一実施例を示す。第３図において、Ｑ
１〜Ｑ６は第２図と同じくダブルバランス型のミキサー
であるが、ミキサー出力はシングル出力即ち、トランジ
スタＱ２〜Ｑ４の共通コレクタのみをＩＣｉの外部端子
のに取出している。又、その出力は外部回路（図示せず
）を通じて外部端子■に接続し、この端子■よりＩＣ内
部に構成されｆｃｘミノタホロアトランジスタＱ７のベ
ースに接続されるように構成している。DESCRIPTION OF EMBODIMENTS FIG. 3 shows an embodiment of the present invention. In Figure 3, Q
1 to Q6 are double-balanced mixers as in FIG. 2, but the mixer outputs are single outputs, that is, only the common collector of transistors Q2 to Q4 is taken out to the external terminal of ICi. Further, the output thereof is connected to an external terminal (2) through an external circuit (not shown), and is connected from this terminal (2) to the base of an fcx minotaph loa transistor Q7 configured inside the IC.
上記の如くの構成において、ＩＣの外部に設けた端子（
如７■に接続する外部回路例を第４図に示す。In the above configuration, the terminal (
FIG. 4 shows an example of the external circuit connected to 7.
第４図のａは端子の、０間を結合コンデンサ６で接続す
る最も簡単な例である。ｂは端子の、０間に複同調回路
７を挿入したもので、中間周波数に対し、フィルタ特性
をもたすものである。Ｃは端子の、０間に抵抗８を挿入
することにより、工Ｃ内のコレクタ負荷抵抗Ｒ１にこの
抵抗８が並列に入ることになり、ミキサ一段のゲイン調
整を行なうことができる。A in FIG. 4 is the simplest example in which a coupling capacitor 6 is used to connect terminals 0 to 0. b has a double-tuned circuit 7 inserted between the terminals 0, and has filter characteristics for intermediate frequencies. By inserting a resistor 8 between the terminals C and 0, this resistor 8 is connected in parallel to the collector load resistor R1 in the circuit C, and the gain of one stage of the mixer can be adjusted.
発明の効果
上記の如く、本発明によれば、ダブルノくランスミキサ
ーの出力をシングル出力としてＩＣの外部端子に取出す
こと、又、次段に続くエミッタホロアのベース入力の端
子をＩＣの外部端子として設けることにより、
（１） シングル出力であるので外部へは１端子出すだ
けで済む。Effects of the Invention As described above, according to the present invention, the output of the double lance mixer is taken out as a single output to the external terminal of the IC, and the base input terminal of the emitter follower in the next stage is provided as the external terminal of the IC. (1) Since it is a single output, only one terminal needs to be output to the outside.
（２） 端子［相］−の間に任意のフィルりを構成でき
る。(2) Any fill can be configured between the terminals [phase] and -.
即チ、端子■の出力インピーダンス、端子■の入力イン
ピーダンスが共に高い為、高い選択度を有するフィルタ
を構成しやすい。従って局部発振信号の漏えい防止やイ
メージ除去の為のフィルタ、又、中間周波帯の複同調フ
４）レタ等を容易に構成できる。That is, since both the output impedance of terminal (1) and the input impedance of terminal (2) are high, it is easy to construct a filter with high selectivity. Therefore, filters for preventing leakage of local oscillation signals and image removal, double tuning filters for intermediate frequency bands, etc. can be easily constructed.
（３１１Ｃの外部端子０．（ｇ）間に抵抗を入れること
により、ミキサーのゲインを調節できる。これによりシ
ステムトータルのゲイン調整や、後段の歪性能に応じて
ゲイン調節することが可能になる。といった効果が得ら
れる。(By inserting a resistor between the external terminals 0.(g) of 311C, the gain of the mixer can be adjusted. This makes it possible to adjust the gain of the total system and the gain according to the distortion performance of the subsequent stage. This effect can be obtained.
第１図は高周波信号増幅装置に関する周辺回路のブロッ
ク図、第２図はそのミキサー及びＩＦアンプの従来例の
回路図、第３図は本発明の一実施例における高周波信号
処理装置の回路図、第４図ａ、ｂ、ｃは第３図の外部端
子に接続する回路例を示す回路図である。
Ｑ、〜Ｑ６・・・・タプルバランス型ミキサー、Ｑ７・
・ ・・エミッタフォロアトランジスタ、の、■・・・
外部端子、６，７．８・・・・・外部回路。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第１
図
ノ＼イアス
第３図FIG. 1 is a block diagram of a peripheral circuit related to a high frequency signal amplification device, FIG. 2 is a circuit diagram of a conventional example of its mixer and IF amplifier, and FIG. 3 is a circuit diagram of a high frequency signal processing device in an embodiment of the present invention. 4a, b, and c are circuit diagrams showing examples of circuits connected to the external terminals of FIG. 3. FIG. Q, ~Q6...tuple balance mixer, Q7...
・ ...Emitter follower transistor, ■...
External terminal, 6, 7.8...external circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person 1st
Figure ＼Ias Figure 3
Claims (1)
されるエミッタホロア回路を集積回路にて構成し、上記
ミキサーの差動トランジスタの２つの共通コレクタの一
方のみを集積回路の外部に引出す端子と、外部回路を経
て上記エミッタホロア回路に入力するだめの別の入力端
子を設けてなる高周波信号処理装置。A double-balanced mixer and an emitter follower circuit connected to the next stage of this mixer are configured using an integrated circuit, and a terminal for drawing out only one of the two common collectors of the differential transistors of the mixer to the outside of the integrated circuit, and an external circuit. A high frequency signal processing device further comprising another input terminal for inputting to the emitter follower circuit through the emitter follower circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59036429A JPS60180206A (en) | 1984-02-27 | 1984-02-27 | High frequency signal processor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59036429A JPS60180206A (en) | 1984-02-27 | 1984-02-27 | High frequency signal processor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60180206A true JPS60180206A (en) | 1985-09-14 |
| JPH0220165B2 JPH0220165B2 (en) | 1990-05-08 |
Family
ID=12469568
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59036429A Granted JPS60180206A (en) | 1984-02-27 | 1984-02-27 | High frequency signal processor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60180206A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01276907A (en) * | 1988-04-28 | 1989-11-07 | Matsushita Electric Ind Co Ltd | Double balance mixer |
| WO2004023650A1 (en) * | 2002-09-09 | 2004-03-18 | Nec Corporation | Push-pull amplifier and frequency conversion circuit |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5511687A (en) * | 1978-07-12 | 1980-01-26 | Matsushita Electric Ind Co Ltd | Frequency conversion circuit |
-
1984
- 1984-02-27 JP JP59036429A patent/JPS60180206A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5511687A (en) * | 1978-07-12 | 1980-01-26 | Matsushita Electric Ind Co Ltd | Frequency conversion circuit |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01276907A (en) * | 1988-04-28 | 1989-11-07 | Matsushita Electric Ind Co Ltd | Double balance mixer |
| WO2004023650A1 (en) * | 2002-09-09 | 2004-03-18 | Nec Corporation | Push-pull amplifier and frequency conversion circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0220165B2 (en) | 1990-05-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0166626A2 (en) | Frequency conversion apparatus | |
| US6819913B2 (en) | Low-noise frequency converter with strong rejection of image frequency | |
| US7760014B2 (en) | Lowpass biquad VGA filter | |
| JPS60180206A (en) | High frequency signal processor | |
| JP4215304B2 (en) | Mixer circuit | |
| JP2000349677A (en) | Signal frequency conversion circuit | |
| JPH0567928A (en) | Amplifier | |
| JP2003017951A (en) | Amplifier for fm antenna | |
| JPH03230605A (en) | Differential oscillation circuit and frequency conversion circuit | |
| KR20080075522A (en) | Enhanced mixer device | |
| JPH073929B2 (en) | AM detection circuit | |
| JPH03125507A (en) | Frequency conversion circuit | |
| JPS6057730A (en) | Tv tuner | |
| JP2579794Y2 (en) | Spectrum analyzer | |
| JPS60194811A (en) | High frequency signal processor | |
| JPS61192131A (en) | Tuner | |
| JPH02195705A (en) | Semiconductor integrated circuit for television tuner | |
| JP2000188516A (en) | Mixer circuit | |
| JPH0955677A (en) | Electronic tuner circuit | |
| JP2548353B2 (en) | Differential amplifier circuit | |
| KR100204597B1 (en) | Frequency mixer structure | |
| JPS60194812A (en) | High frequency signal processor | |
| JPH0365808A (en) | Mixing circuit | |
| JP3984845B2 (en) | High frequency receiver circuit | |
| JPH02168733A (en) | Front end circuit |