JPS61192131A - Tuner - Google Patents
TunerInfo
- Publication number
- JPS61192131A JPS61192131A JP3207485A JP3207485A JPS61192131A JP S61192131 A JPS61192131 A JP S61192131A JP 3207485 A JP3207485 A JP 3207485A JP 3207485 A JP3207485 A JP 3207485A JP S61192131 A JPS61192131 A JP S61192131A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- balanced
- intermediate frequency
- mixer
- diodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Superheterodyne Receivers (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明はシングル・スーパー方式のテレビジョン用のチ
ューナに関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a tuner for single-super television.
従来の技術
第10図に従来のチューナの基本機能ブロック図を示し
ており、図において1はアンテナ入力端子、2は分配器
、3.4はVHF帯、UHF帯用0入力同調回路、5.
6は同じ(RF増幅器で、RF入力端子5a、6aを有
している。7,8は同じく段間複同調回路、9は混合回
路、10は発振回路、11は中間周波通過P波器、12
は信号切換回路、13は混合回路(IF増幅回路)、1
4は発振回路、16は出力同調回路、16は中間周波出
力端子である。BACKGROUND ART FIG. 10 shows a basic functional block diagram of a conventional tuner. In the figure, 1 is an antenna input terminal, 2 is a distributor, 3.4 is a 0-input tuning circuit for VHF and UHF bands, and 5.
6 is the same RF amplifier and has RF input terminals 5a and 6a. 7 and 8 are also interstage double-tuned circuits, 9 is a mixing circuit, 10 is an oscillation circuit, 11 is an intermediate frequency passing P-wave device, 12
is a signal switching circuit, 13 is a mixing circuit (IF amplifier circuit), 1
4 is an oscillation circuit, 16 is an output tuning circuit, and 16 is an intermediate frequency output terminal.
発明が解決しようとする問題点
この問題点を特に妨害排除能力の観点から説明すると、
第一にVHFの混合器においては、従来バイポーラトラ
ンジスタやMOSFET、更にはモノリシックIC化乗
算器などが用いられてきたが、これらはいずれも隣接混
変調妨害や混合器の2次歪−による2次相互変調妨害(
IM2)、3次の歪による3次相互変調妨害()Ms)
に対して、十分な性能を得ることができなかった。Problems to be Solved by the Invention To explain this problem particularly from the perspective of interference rejection ability, firstly, VHF mixers have conventionally used bipolar transistors, MOSFETs, and even monolithic IC multipliers. However, these are all caused by adjacent intermodulation interference and second-order intermodulation interference due to mixer second-order distortion.
IM2), third-order intermodulation interference due to third-order distortion ()Ms)
However, sufficient performance could not be obtained.
第二にUHFの混合器においては、従来バイポーラトラ
ンジスタやダイオードなどが用いられてきたが、これら
も前記VHFの混合器と同じような性能問題をもってい
た。Second, bipolar transistors, diodes, and the like have been conventionally used in UHF mixers, but these also have the same performance problems as the VHF mixers.
第三にRF増幅器についてみると、UHF、VHFとも
共通に、特にIMsの歪特性の改善が必要であった。Thirdly, regarding RF amplifiers, both UHF and VHF require improvement in distortion characteristics, especially IMs.
近年上記妨害に対するチューナの性能改善を求める市場
の要望は高まる一方であって、酉独における新FTZ規
格に代表されるように法律化されてきている背景もあり
、チューナの歪特性の改善による高妨害排除能力を有す
るチューナの開発が待たれていた。In recent years, the market demand for improved performance of tuners against the above interference has been increasing, and with the background of laws being enacted as exemplified by the new FTZ standard in Germany, it is possible to The development of a tuner with the ability to eliminate interference has been awaited.
本発明は、上記事情を鑑みなされたものである。The present invention has been made in view of the above circumstances.
問題点を解決するための手段
上記問題点を解決するために本発明は、シングルス−/
く一方式のテレビ用電子チューナであって、UHF部の
混合器に4つのダイオードよりなる二重平衡型混合回路
を用い、UHF部の混合器に2つのダイオードからなる
一重平衡型混合器を用いたものである。Means for Solving the Problems In order to solve the above problems, the present invention provides a singles-/
This is a double-balanced type electronic tuner for television that uses a double-balanced mixing circuit consisting of four diodes for the mixer in the UHF section, and a single-balanced mixer consisting of two diodes for the mixer in the UHF section. It was there.
また、前記2つの混合回路の出力にそれぞれ独立の中間
周波通過F波器を設けるとともに、それぞれのろ波器出
力信号を1回路2接点の信号切換回路を通した後、共通
の中間周波増幅回路に結合させ、さらに前記2つの混合
回路それぞれのRF信号入力端子の前段にそれぞれ独立
したエミッタホロクー回路を設けたものである0
さらに、同じく混合回路の局部発振信号入力端子の前段
にそれぞれ独立した局部発振出力増幅器を設けている。In addition, independent intermediate frequency passing F wave filters are provided at the outputs of the two mixing circuits, and after passing the output signals of each filter through a signal switching circuit with one circuit and two contacts, a common intermediate frequency amplifier circuit is provided. In addition, independent emitter holocou circuits are provided in front of the RF signal input terminals of the two mixing circuits. A local oscillation output amplifier is provided.
また、前記一重平衡型混合回路の出力中間周波F波器と
前記信号切換回路との間に、中間周波増幅器を設けてい
る。また、PINダイオードよりなる利得制御回路をア
ンテナ入力端子の初段に設けた後、UHF/VHF分配
回路に結合するように構成している。Further, an intermediate frequency amplifier is provided between the output intermediate frequency F-wave generator of the single-balanced mixing circuit and the signal switching circuit. Further, a gain control circuit made of a PIN diode is provided at the first stage of the antenna input terminal, and then connected to the UHF/VHF distribution circuit.
作 用
この構成により、隣接混変調やIM2 、IMs妨害に
対して高い排除能力を持たせることができることとなる
〇
実施例
以下、本発明の実施例を図面とともに説明する。Function: This configuration provides high rejection capability against adjacent cross-modulation, IM2, and IMs interference.Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.
なお、第10図と同一部分については同一番号を付して
いる。Note that the same parts as in FIG. 10 are given the same numbers.
第1図の実施例は、VHFの混合器に、4つのダイオー
ドよりなる二重平衡型混合回路17を用い、UHF部の
混合器に2つのダイオードからなる一重平衡型混合器回
路を用いるとともに、前記2つの混合回路の出力にそれ
ぞれ独立した中間周波通過F波器11.19を設け、そ
れぞれのろ波器出力信号を1回路2接点の信号切換回路
12を通した後、共通の中間周波増幅器20に結合させ
た実施例である。なお、21は発振回路である◎第2図
の実施例は、前記二重平衡型混合回路17と、一重平衡
型混合回路18それぞれのRF信号入力端子の前段にそ
れぞれ独立したエミッタホロクー回路22.23を設け
たものである◇第3図に示す実施例は、前記二重平衡型
混合回路17と、一重平衡製混合回路18それぞれの局
部発振信号入力端子の前段に、それぞれ独立した増幅器
24.25を設けた実施例である。The embodiment shown in FIG. 1 uses a double-balanced mixer circuit 17 consisting of four diodes for the VHF mixer, and a single-balanced mixer circuit 17 consisting of two diodes for the UHF mixer. Independent intermediate frequency passing F-wave filters 11 and 19 are provided at the outputs of the two mixing circuits, and after passing the respective filter output signals through a signal switching circuit 12 with one circuit and two contacts, a common intermediate frequency amplifier is provided. This is an example in which it is combined with 20. 21 is an oscillation circuit. In the embodiment shown in FIG. 2, independent emitter hollow circuits 22 are provided in front of the RF signal input terminals of the double-balanced mixing circuit 17 and the single-balanced mixing circuit 18, respectively. In the embodiment shown in FIG. 3, independent amplifiers 24 are provided in front of the local oscillation signal input terminals of the double balanced mixing circuit 17 and the single balanced mixing circuit 18. This is an example in which .25 is provided.
第4図の実施例は、前記一重平衡型混合回路18の中間
周波p波器11と前記信号切換回路12との間に中間周
波増幅器26を設けた実施例である。The embodiment shown in FIG. 4 is an embodiment in which an intermediate frequency amplifier 26 is provided between the intermediate frequency p-wave generator 11 of the single-balanced mixing circuit 18 and the signal switching circuit 12.
第5図の実施例は、PINダイオードよりなる利得制御
回路27をアンテナ入力端子1の初段に設けた後、UH
F/VHFの分配器2に結合するようにした実施例であ
るO
第6図〜第9図に要部の具体回路を示しており、第6図
は4つのダイオード28よりなる二重平衡型混合回路を
示しここで29,30はパランである031はRF信号
入力端子、32は局部発振入力端子、33は中間周波出
力端子であるO第7図は、2つのダイオード34よりな
る一重平衡型混合回路を示し、36は接地用コンデンサ
ー、36はバランである。In the embodiment shown in FIG. 5, after providing a gain control circuit 27 made of a PIN diode at the first stage of the antenna input terminal 1,
6 to 9 show specific circuits of main parts, and FIG. 6 shows a double-balanced type circuit consisting of four diodes 28. 031 is an RF signal input terminal, 32 is a local oscillation input terminal, and 33 is an intermediate frequency output terminal. Figure 7 shows a single-balanced type circuit consisting of two diodes 34. A mixing circuit is shown, where 36 is a grounding capacitor and 36 is a balun.
第8図はVHF部の前記エミッタホロワ−回路22の実
施例を示し、37はVHF用電源端子である。FIG. 8 shows an embodiment of the emitter follower circuit 22 of the VHF section, and 37 is a VHF power supply terminal.
第9図はUHF部の前記エミッタホロワ−回路23、中
間周波通過F波器11の実施例を示している。FIG. 9 shows an embodiment of the emitter follower circuit 23 and the intermediate frequency passing F wave device 11 in the UHF section.
以上のように、VHF/lJ)!Fそれぞれの混合器に
平衡混合回路を用いることによシ、従来問題となってい
た前記隣接混変調やIM2 、IM3妨害に対し十分な
性能をもった混合回路が実現でき、しかもUHF/VH
F共通の中間周波増幅器を具備することにより、中間周
波増幅器として、最適の高妨害排除能力の回路設計が実
現できる。As mentioned above, VHF/lJ)! By using a balanced mixing circuit for each F mixer, it is possible to realize a mixing circuit that has sufficient performance against the adjacent cross modulation and IM2 and IM3 interference, which have been problems in the past.
By providing a common intermediate frequency amplifier for F, it is possible to realize a circuit design with an optimal high interference rejection ability as an intermediate frequency amplifier.
また、前記エミッタホロワ−回路を設けることにより、
前記平衡型混合回路の低いRF入カインピーダンスを高
く変換し、段間選択度の向上を図り、イメージ妨害に対
しても従来と同等以上の性能を確保することができ、前
記局部発振増幅器を設けることにより、ダイオード平衡
型混合回路に不可欠な高い注入レベルを確保することに
より、高妨害排除能力の混合回路を維持することが可能
で、さらに、前記UHF−HF貴重平衡回路の出力F波
器と前記信号切換回路との間に中間周波増幅器を設ける
ことにより、UHF部の利得不足(約5dB )を補
正すルコトカテき、UHF/VHF同一の利得をもった
チューナを実現できる。Furthermore, by providing the emitter follower circuit,
The low RF input impedance of the balanced mixing circuit can be converted to a high level, the selectivity between stages can be improved, and the performance against image interference can be secured to be equal to or higher than that of the conventional one, and the local oscillation amplifier is provided. By ensuring a high injection level essential for a diode balanced mixed circuit, it is possible to maintain a mixed circuit with high interference rejection ability, and furthermore, the output By providing an intermediate frequency amplifier between the signal switching circuit and the signal switching circuit, it is possible to correct the lack of gain (approximately 5 dB) in the UHF section, and to realize a tuner having the same gain for UHF and VHF.
さらに、PINダイオードからなる利得制御回路をアン
テナ入力端子の初段に設けることにより、RF増幅器で
問題であったIM3の歪特性の改善が達成され、結果と
して妨害排除能力の優れたテレビチューナを実現するこ
とができる。Furthermore, by providing a gain control circuit consisting of a PIN diode at the first stage of the antenna input terminal, the distortion characteristics of IM3, which was a problem with RF amplifiers, have been improved, resulting in a TV tuner with excellent interference rejection ability. be able to.
発明の効果
以上のように本発明によれば、隣接混変調やIM2 、
IM3妨害に対して十分な性能を持たせ・ ることか
できる0Effects of the Invention As described above, according to the present invention, adjacent cross modulation, IM2,
It is possible to provide sufficient performance against IM3 interference.
第1図〜第6図はそれぞれ本発明の実施例によるチュー
ナの構成を示すブロック図、第6図は同ブロックのダイ
オード二重平衡型混合回路の回路図、第7図は同じくダ
イオード一重平衡型混合回路の回路図、第8図は同じ(
VHF側のエミッタホロワ−回路の回路図、第9図は同
じ(UHF側のエミッタホロワ−回路の回路図、第10
図は従来のチューナのブロック図である。
1・・・・・・アンテナ入力端子、2・・・・・・分配
器、6゜6・・・・・・RF増幅回路、11.19・・
・・・・中間周波通過F波器、12・・・・・・信号切
換回路、17・・・・・・二重平衡型混合回路、18・
・・・・・一重平衡型混合回路、20・・・・・・中間
周波増幅器、22.23・・・・・・エミッタホロワ−
回路、24.25・・・・・・増幅器、26・・・・・
・中間周波増幅器、2〕・・・・・・利得制御回路。
代理人の氏名 弁理士 中 尾 敏 男 ほか1名第6
図
、31
第7図
i8図
第9図1 to 6 are block diagrams showing the configuration of a tuner according to an embodiment of the present invention, FIG. 6 is a circuit diagram of a diode double-balanced mixed circuit of the same block, and FIG. 7 is a diode single-balanced mixed circuit of the same block. The circuit diagram of the mixed circuit, Figure 8, is the same (
The circuit diagram of the emitter follower circuit on the VHF side, Figure 9, is the same (the circuit diagram of the emitter follower circuit on the UHF side, Figure 10)
The figure is a block diagram of a conventional tuner. 1...Antenna input terminal, 2...Distributor, 6゜6...RF amplifier circuit, 11.19...
...Intermediate frequency passing F wave device, 12... Signal switching circuit, 17... Double balanced mixing circuit, 18.
...Single balanced mixing circuit, 20...Intermediate frequency amplifier, 22.23...Emitter follower
Circuit, 24.25...Amplifier, 26...
・Intermediate frequency amplifier, 2]...Gain control circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 6
Fig. 31 Fig. 7 i8 Fig. 9
Claims (6)
合器に4つのダイオードよりなる二重平衡型混合器を用
い、UHF部の混合器に2つのダイオードからなる一重
平衡型混合器を用いたチューナ。(1) A single super system, in which a double-balanced mixer consisting of four diodes was used as the mixer in the VHF section, and a single-balanced mixer consisting of two diodes was used in the mixer in the UHF section. tuner.
通過ろ波器を設けるとともに、それぞれのろ波器出力信
号を1回路2接点の信号切換回路を通した後、共通の中
間周波増幅器に結合させた特許請求の範囲第1項に記載
のチューナ。(2) In addition to providing independent intermediate frequency pass filters for the outputs of the two mixing circuits, the output signals of each filter are passed through a signal switching circuit with one circuit and two contacts, and then sent to a common intermediate frequency amplifier. A tuner according to claim 1, as combined.
ぞれのRF信号入力端子の前段にそれぞれ独立したエミ
ッタホロワー回路を設けた特許請求の範囲第1項に記載
のチューナ。(3) The tuner according to claim 1, wherein independent emitter follower circuits are provided in front of the RF signal input terminals of each of the double balanced mixing circuit and the single balanced mixing circuit.
ぞれの局部発振信号入力端子の前段に、それぞれ独立し
た増幅器を設けた特許請求の範囲第1項に記載のチュー
ナ。(4) The tuner according to claim 1, wherein independent amplifiers are provided in front of the local oscillation signal input terminals of each of the double-balanced mixing circuit and the single-balanced mixing circuit.
信号切換回路との間に、中間周波増幅器を設けた特許請
求の範囲第1項に記載のチューナ。(5) The tuner according to claim 1, wherein an intermediate frequency amplifier is provided between the output intermediate frequency filter of the single-balanced mixing circuit and the signal switching circuit.
ナ入力端子の初段に設けた後、UHF/VHFの分配器
に結合するようにした特許請求の範囲第1項に記載のチ
ューナ。(6) The tuner according to claim 1, wherein a gain control circuit made of a PIN diode is provided at the first stage of the antenna input terminal and then coupled to the UHF/VHF divider.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3207485A JPS61192131A (en) | 1985-02-20 | 1985-02-20 | Tuner |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3207485A JPS61192131A (en) | 1985-02-20 | 1985-02-20 | Tuner |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61192131A true JPS61192131A (en) | 1986-08-26 |
Family
ID=12348728
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3207485A Pending JPS61192131A (en) | 1985-02-20 | 1985-02-20 | Tuner |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61192131A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02295230A (en) * | 1989-04-13 | 1990-12-06 | Thomson Consumer Electron Inc | High frequency signal processor |
EP1750140A2 (en) * | 2005-07-28 | 2007-02-07 | TDK Corporation | Pulse radar system |
US7538718B2 (en) | 2007-01-30 | 2009-05-26 | Tdk Corporation | Radar system |
-
1985
- 1985-02-20 JP JP3207485A patent/JPS61192131A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02295230A (en) * | 1989-04-13 | 1990-12-06 | Thomson Consumer Electron Inc | High frequency signal processor |
EP1750140A2 (en) * | 2005-07-28 | 2007-02-07 | TDK Corporation | Pulse radar system |
EP1750140A3 (en) * | 2005-07-28 | 2008-07-30 | TDK Corporation | Pulse radar system |
US7498975B2 (en) | 2005-07-28 | 2009-03-03 | Tdk Corporation | Pulse radar system |
US7538718B2 (en) | 2007-01-30 | 2009-05-26 | Tdk Corporation | Radar system |
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