JPH1117455A - Frequency converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high frequency mixer having the characteristics of low distortion, low unrequired radiation power and high gain. SOLUTION: This frequency converter is composed of four FETs(field effect transistors) 1-4 respectively provided with a source terminal, a drain terminal and a gate terminal for which the respective characteristics are matched, the source terminals and drain terminals of a first FET and a second FET and the source terminals and drain terminals of a third FET and a forth FET are connected with each other and the gate terminals of the first FET and the forth FET and the gate terminals of the second FET and the third FET are connected with each other. The four FETs 1-4 perform action similar to an anti-parallel diode, first signals (local oscillation frequency) are differentially inputted from the gate terminal of the first FET and the gate terminal of the second FET; second signals (high frequency signals) are differentially inputted from the source terminal of the first FET and the source terminal of the third FET and third signals (base band signals) are differentially outputted from the drain terminal of the first FET an the drain terminal of the third FET.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency converter, and more particularly, to a high frequency mixer having characteristics of low distortion, low unnecessary radiation power, and high gain.

[0002]

2. Description of the Related Art When an intermediate frequency is smaller than a receiving frequency bandwidth, there is a receiver using an image rejection method to prevent image interference. There is also a direct conversion type receiver that uses frequency conversion directly to baseband without using an intermediate frequency. In the case of the above-mentioned image rejection type receiver, the intermediate frequency is a considerably low frequency, and is hereinafter referred to as a baseband frequency together with the direct conversion type in this specification. In these types of receivers, the baseband frequency interfering wave is generated by the secondary intermodulation distortion of the signal in the reception band generated inside the mixer. Therefore, the receiver removes the interference due to the secondary intermodulation distortion. There is a need to. Also, since the local oscillation frequency is set within the reception frequency band, it is necessary to prevent unnecessary radiation to the reception frequency band due to leakage of the local oscillation signal from the receiver. In such a small-sized receiving device, it is increasingly difficult to prevent unnecessary radiation from a local oscillator operating with relatively large power.

For the above reasons, a harmonic mixer using an anti-parallel diode as shown in FIG. 7 has been proposed (TECHNICAL REPORT OF IECE ED95-162, MW95-14).
7, p67-72 Detection characteristics of even harmonic direct converter; Japanese Patent Application Laid-Open No. 8-250936 (mixer circuit).
In FIG. 7, reference numeral 30 denotes an anti-parallel diode mixer, 31 denotes a local oscillation frequency filter, 32 denotes an RF filter, and 33 denotes a baseband filter. In a mixer using the anti-parallel diode 30, a conventional local oscillation frequency is reduced by virtual local oscillation. Frequency, and a frequency corresponding to a half thereof can be used as an actual local oscillation frequency,
Unwanted radiation to the reception band can be prevented. Also,
Since the second-order intermodulation distortion cancels out in the anti-parallel diode 30, the anti-parallel diode 30 also has excellent characteristics in removing interference due to the second-order intermodulation distortion of a signal in the reception band.

[0004]

As described above, a mixer using a conventional anti-parallel diode has excellent characteristics as described above, but has no power gain and large third-order intermodulation distortion. There was a problem. As for the linearity of the mixer, third-order intermodulation distortion is also important in addition to the above-mentioned second-order intermodulation distortion. In particular, the reception band is large as in recent mobile communication, and the number of channels in the reception band is large. In many cases, the interfering wave generated by the third-order intermodulation distortion is also very important.

[0005]

According to a first aspect of the present invention, there are provided four FETs (field effect transistors) each having a source terminal, a drain terminal, and a gate terminal and having the same characteristics. The source and drain terminals of the first and second FETs, and the third FET
And the source terminal and the drain terminal of the fourth FET are connected to each other, and the gate terminal of the first FET and the fourth FET are connected to each other, and the gate terminal of the second FET and the third FET are connected to each other. And the second FE
A differential input of a first signal from the gate terminal of T
The second from the source terminal of the FET and the source terminal of the third FET
Is differentially input, and a third signal is differentially output from the drain terminal of the first FET and the drain terminal of the third FET.

According to a second aspect of the present invention, each F
Instead of ET, a bipolar transistor is used, and the emitter terminal of the bipolar transistor is connected to the source terminal of the FET, the base terminal is connected to the gate terminal, and the collector terminal is connected to the drain terminal. is there.

According to a third aspect of the present invention, in the first or second aspect of the present invention, the gate (or base) bias is set such that the ON time of each of the transistors is a time corresponding to a quarter cycle of the local oscillation frequency. It is characterized by doing.

According to a fourth aspect of the present invention, there is provided a first group of FETs (a first group of four FETs each having a source terminal, a drain terminal, and a gate terminal and having the same characteristics).
To 4) and a second group of FETs (fifth to eighth) composed of four FETs having the same characteristics, and the first FE
Between the drain terminal of T and the source terminal of the fifth FET,
The drain terminal of the FET and the source terminal of the sixth FET,
The drain terminal of the third FET is connected to the source terminal of the seventh FET, the drain terminal of the fourth FET is connected to the source terminal of the eighth FET, the source terminals of the first FET and the second FET are connected, and the sources of the third FET and the fourth FET are connected. The terminals are connected to each other, the drain terminals of the fifth FET and the sixth FET are connected, and the drain terminals of the seventh FET and the eighth FET are connected to each other. The gate terminals of the first FET, the fourth FET, the sixth FET, the seventh FET, and the 2FET and 3rd
The gate terminals of the FET, the fifth FET, and the eighth FET are connected to each other, the first signal is differentially input from the gate terminal of the first FET and the gate terminal of the third FET, and the first signal is input from the source terminal of the first FET and the source terminal of the fourth FET. 2 is differentially input, and the third signal is differentially output from the drain terminal of the fourth FET and the drain terminal of the seventh FET.

According to a fifth aspect of the present invention, in the fourth aspect of the present invention, the gate bias is set so that the ON time of each of the transistors is a time corresponding to a 3/4 cycle in the local oscillation frequency. Things.

According to a sixth aspect of the present invention, there is provided a first group of FETs (a first group of four FETs each having a source terminal, a drain terminal, and a gate terminal and having the same characteristics).
To 4), a second group of FETs (fifth to eighth) composed of four FETs having the same characteristics, and a third group of FETs (fourth to eighth) having the same characteristics. 9th to 12th)
And the drain terminal of the fifth FET and the source terminal of the ninth FET, and the drain terminal of the sixth FET and the
The source terminal of the ET, the drain terminal of the seventh FET and the source terminal of the eleventh FET, the drain terminal of the eighth FET and the source terminal of the twelfth FET are connected, and the first FET, the second FET, the fifth FET, and the sixth FET are connected.
Source terminals of the third FET, the fourth FET, and the seventh FE
T and the source terminal of the eighth FET, the third FET and the fourth F
ET and the drain terminals of the ninth FET and the tenth FET,
1st FET, 2nd FET, 11th FET and 12th FET
Drain terminals of the fifth FET, the eighth FET and the tenth FET
The gate terminals of the FET and the eleventh FET, the gate terminals of the sixth FET, the seventh FET, the ninth FET and the twelfth FET, the gate terminals of the first FET and the fourth FET, and
The gate terminals of the second and third FETs are connected to each other, the first signal is input in phase from the gate terminal of the first FET and the gate terminal of the fifth FET, and the gate terminal of the second FET is connected to the sixth terminal.
The first signal is transmitted from the gate terminal of the FET to the first F
The first signal input from the gate terminal of the ET and the gate terminal of the fifth FET is input in reverse phase, the second signal is differentially input from the source terminal of the first FET and the source terminal of the third FET, and the drain of the first FET is input. A third signal is differentially output from the terminal and the drain terminal of the third FET.

According to a seventh aspect of the present invention, the bias is set so that the ON time of each of the first to fourth FETs is a time corresponding to a quarter cycle of the local oscillation frequency, and The bias is set so that each FET ON time becomes a time corresponding to 3/4 cycle in the local oscillation frequency.

According to an eighth aspect of the present invention, in any one of the first to seventh aspects, a filter for suppressing an in-phase signal is provided at the source terminal for differentially inputting a high-frequency signal. .

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION

(Embodiment 1) FIG. 1 is a block diagram for explaining an embodiment of the present invention. In FIG.
T (field effect transistor), 13 is a local oscillation signal source,
14 is a high-frequency signal source, 15 is a baseband signal output terminal, 16 to 18 are baluns, and 19 is a gate bias power supply. First, an explanation will be given of why the four FETs perform the same function as the anti-parallel diode. The local oscillation signal from 13 and the high-frequency signal from 14 become differential signals at baluns 16 and 17, respectively.
It is supplied to the gate terminal and the source terminal. Here, since the local oscillation signal from 13 is input in the opposite phase to the first FET 1 and the second FET 2, the first FET 1 and the second FET 2
The fundamental wave component of the local oscillation signal and the odd-order high-frequency component are in opposite phases, and the even-order harmonic components are in-phase between the FETs 2. Therefore, the result of mixing the fundamental component of the local oscillation signal, the odd-order harmonic component, and the high-frequency signal is the first FE
The phases are opposite between T1 and the second FET2, and are canceled by the connected drain terminal and are not output to the outside.

On the other hand, the result of mixing the second harmonic component of the local oscillation signal from 13 and the higher harmonic signal is the first FET 1
And the second FET 2 have the same phase, are combined at the connected drain terminal, and output to the outside. Therefore, a circuit in which the first FET 1 and the second FET 2 are combined exhibits the characteristics of a harmonic mixer that outputs the even harmonic component of the local oscillation signal and the result of mixing the harmonic signal. Next, the third FET 3 and the fourth FET 4 are connected to the first FET
And the second FET 2. The difference is that harmonic components are input in opposite phases, and that they are combined and output in opposite phases. If the FETs 1 and 2 and the FETs 3 and 4 are considered as one mixer, respectively, in each mixer, the fundamental component of the harmonic component and the odd harmonic component are in opposite phases, and the even harmonic component is It is in phase. As a result, the result of mixing the second harmonic component and the high-frequency signal becomes opposite in phase, and the signals are combined in opposite phases by the balun 18, and are output to the baseband signal output terminal 15.

On the other hand, the even-order harmonic components of the high-frequency signal have the same phase, and the signals are combined by the balun 18 in the opposite phase.
Not output to the baseband signal output terminal. Here, the second-order intermodulation distortion component of the mixer is one of the even-order harmonic components, which means that it is not output to the baseband signal output terminal 15. Therefore, as the whole circuit, similarly to the circuit using the anti-parallel diode described with reference to FIG. 7, it is possible to use a local oscillation signal having half the frequency of the local oscillation signal in the case of a normal mixer. Intermodulation distortion can be suppressed. Further, unlike the circuit using the anti-parallel diode described in FIG. 7, unlike the diode, an active element having a negative resistance is used as the mixing element, so that the mixer has a conversion gain, and as a result, the base Third-order intermodulation distortion can be relatively reduced with respect to the band signal output. In the circuit of FIG. 1, when a Gm100 mS element having a gate width of 400 μm is used as the FET, the conversion gain is 3 dB, and the third-order intermodulation distortion is IIP.
3 gave a good result of 6 dBm.

Here, reference numeral 19 denotes a gate bias power supply, and the FET is turned on and off by a local oscillation signal from 13.
If the voltage for FF is set, the above-described operation is performed. More preferably, the conversion gain can be increased by setting the bias so that the ON time becomes 1/4 cycle. Second-order intermodulation distortion can be relatively reduced. This is probably because when the FETs 1 and 2 and the FETs 3 and 4 are viewed as one unit, the ON and OFF times of the circuit are halved, and the frequency component twice as large as the local oscillation frequency is maximized.

In FIG. 1, the circuit corresponding to the anti-parallel diode circuit is constituted by FETs. However, other bipolar transistors may be used. The terminals of the source, gate and drain are connected to the emitter, base and The same effect can be obtained by replacing it with a collector. But F
Since ET is originally an element having better linearity, it is more suitable for the purpose of the present invention. In FIG. 1, 1
Each of the baluns 6 to 18 may be another conversion circuit as long as it performs parallel-to-parallel conversion.

(Embodiment 2) FIG. 2 is a view for explaining another embodiment of the present invention. In the figure, 5 to 12 are FETs having the same characteristics, and 5 to 8 are first group FETs. , 9 to 12 constitute a second group of FETs. 13 to 18 are shown in FIG.
Are the same as the corresponding devices in the embodiment shown in FIG. 1, and reference numeral 20 denotes a gate bias power supply. Next, FIG.
The operation of why the FETs 5 to 12 shown in FIG.
The local oscillation signal from 13 and the high-frequency signal from 14 become differential signals at baluns 16 and 17, respectively, and are supplied to the gate terminal and source terminal of the FET as in the first embodiment. The 19 gate bias power supply is a local oscillation signal and each FE
The bias is set so that T is turned on and off. Here, since the FETs 5 and 9 are connected in series, one of them is O
In the case of FF, it is OFF as a whole. Here, FET5
Since the local oscillation signal from 13 is input in the opposite phase to the gates of the FETs 9 and 9, the phases at which the FETs 5 and 9 are turned off are shifted by almost 180 degrees. ON and OFF are performed at twice the frequency of the signal. In this state, since a high-frequency signal is input from the source terminal, a mixed result of the high-frequency signal and an even-order harmonic component, mainly the second-order local oscillation signal, is output.

However, in practice, the phase in which the FETs 5 and 9 are turned off deviates from 180 degrees, so that a fundamental component and an odd-order harmonic component are also generated, and the efficiency of the target baseband signal is reduced. Therefore, the FETs 5 and 9 are canceled by providing the FETs 6 and 10 connected in reverse to the local oscillation signal. Therefore, FET5
And 9 and the FETs 6 and 10 show the characteristics of a harmonic mixer that outputs the even harmonic component of the local oscillation signal and the result of the kinking of the high-frequency signal.

Next, the FETs 7, 11, 8, and 12 are
T5 and 9 and FETs 6 and 10 are paired, and the even-order intermodulation distortion component mainly including the second-order intermodulation distortion component of the high-frequency signal output in phase is passed through the balun 18 so that 15 baseband signals are obtained. It is the same as in the first embodiment that the output is not output to the output terminal. Further, similarly to the first embodiment,
Since an active element having a negative resistance is used as the mixing element, it has a conversion gain and can have good third-order intermodulation distortion characteristics. In the circuit of FIG.
When an element having a gate width of 1000 μm and a Gm of 240 mS was used as the ET, a good result of 5 dBm was obtained with IIP3 as the conversion gain of 5 dB and third-order intermodulation distortion.

In FIG. 2, reference numeral 20 denotes a gate bias power supply.
If the voltage is set to N or OFF, the above operation is performed. More preferably, the ON time is set to 3 hours.
By setting the bias to be / 4 cycle,
The conversion gain can be increased, and the third-order intermodulation distortion can be relatively reduced. This is FET5 and 9, FET6 and 10,
When the FETs 7 and 11 and the FETs 8 and 12 are viewed as one unit, respectively, as in the first embodiment, the ON,
It is considered that the OFF time becomes half and the frequency component twice as large as the local oscillation frequency becomes the largest.

In FIG. 2, the FETs 5 to 8 and the FE
Each of T9 to 12 must have the same characteristics,
It is not necessary that the two groups have the same characteristics. However, the use of elements having the same pinch-off voltage requires only one bias power supply, and the conversion efficiency is better when the saturation current is substantially the same. In this case, almost the same characteristics can be obtained when the saturation current is about 0.3 to 3 times.
Also, the optimal point in terms of characteristics is not when the saturation current is the same,
Deviation within the above range. Further, FETs 5 and 9 and F
As is generally known, the series configuration of the ETs 6 and 10, the FETs 7 and 11, and the FETs 8 and 12 can be replaced with a single dual-gate FET.

(Embodiment 3) FIG. 3 is a diagram for explaining another embodiment of the present invention. In the figure, reference numerals 1 to 4 denote FETs having the same characteristics. FETs 5 to 12 also have the same characteristics as each other, but the saturation current is 1 /
Two of them are used. The FETs 13 to 18 are exactly the same as the corresponding devices in the first embodiment shown in FIG. 19 and 20 are gate bias power supplies. Also,
FETs 1 to 12 and gate bias power supplies 19 and 20 are denoted by the same reference numerals as those corresponding to the first and second embodiments. A circuit composed of FETs 1 to 4;
In the circuit including the FETs 5 to 12, the connection of the output from the drain terminal is a cross connection to the connection of the high frequency signal to the source terminal.

Next, an explanation will be given of the operation why the FETs 1 to 12 shown in FIG. 3 function similarly to the anti-parallel diode. Local oscillation signal from 13, 14
Is the same as in the first and second embodiments, and the high-frequency signal from the first and second baluns 16 and 17 becomes a differential signal and is supplied to the gate terminal and the source terminal of the FET. The local oscillation signals that have become differential signals are separately biased by 19 and 20 gate bias power supplies, respectively, and supplied to circuits combining the FETs used in the first and second embodiments, respectively. It works as a harmonic mixer in the same way as 2.

Here, a circuit in which the FETs 1 and 2 are combined,
Comparing the circuits in which the FETs 5 and 9 are combined, both show that the FETs 1 and 2 have one FE at the timing centered on the point where the local oscillation signal voltage has a maximum and a minimum.
When T turns on, the circuit turns on. In FETs 5 and 9, when one FET is turned off, the circuit is turned off. That is, it can be seen that the phase of the ON timing of the circuits of the FETs 1 and 2 is the same as the phase of the OFF timing of the circuits of the FETs 5 and 9, and the phase of the ON timing of the FETs 5 and 9 is opposite to that. This is the same even when the circuit of the FETs 1 to 4 and the circuit of the FETs 5 to 12 are considered. The phases in which both are turned on are opposite, and the cycle is the local oscillation frequency as shown in the first and second embodiments. It is twice as large as

Therefore, the result obtained by mixing the input high-frequency signal and the frequency component twice as high as the local oscillation frequency is output as the opposite phase. In FIG. 3, the drain terminals are cross-connected. In-phase synthesis. Since the even-order intermodulation distortion component mainly including the second-order intermodulation distortion component of the high-frequency signal is output in phase, it is not output to the baseband signal output terminal 15 via the balun 18 according to the first embodiment. Same as Example 2. Further, since an active element having a negative resistance is used as a mixing element as in the first and second embodiments, the third embodiment also has a good conversion gain and a good third-order intermodulation distortion characteristic. have.

In the circuit shown in FIG.
Gm = 55 mS, 200 μm gate width, FET5
In the case of using an element having a gate width of 100 μm and Gm = 28 mS, good results of 7 dBm in IIP3 were obtained as conversion gain of 2 dB and third-order intermodulation distortion. Here, the gate bias power supplies of 19 and 20 are the same as in the first and second embodiments, respectively.
By setting the bias so that the N time is 1/4, 3/4 cycle, the conversion gain can be increased and the third-order intermodulation distortion can be relatively reduced.

Here, the circuits of FETs 1 to 4 and FET 5
Since the circuits Nos. To 12 operate at twice the frequency of the local oscillation frequency, the frequency is output from each terminal, and when the unnecessary radiation is radiated to the outside, it is used in the same frequency band. In the first and second embodiments, an unnecessary wave having a frequency twice as high as the local oscillation frequency generated from the source terminals of the FETs 1 and 2 and the FETs 3 and 4 is an in-phase signal. Therefore, the output is not output to the terminal 14 because of the presence of the balun 17. However, in general, the balance of the balun is not perfect, and in particular, the balun for high frequency is difficult to balance. Therefore, unnecessary waves are output to the terminal 14 as much as the balance is lost.

In this embodiment, the circuit of FETs 1 to 4 and F
Since the phases of the frequency components twice as large as the local oscillation frequency of the circuits ET5 to ET12 are opposite, unnecessary waves are canceled at the connection point, and even if the balance of the balun 17 is lost, the output of the terminal 14 is lost. It is possible to suppress unnecessary waves.

Here, the circuits of FETs 1-4 and FETs 5
The fact that the phase of the frequency component twice as large as the local oscillation frequency of the circuit 12 is opposite, as described above, since the output intensities are not necessarily the same, so that the parameters of the FETs are set to be the same in both circuits. The simplest way to change the gate width is to change the gate width of the FET. In this embodiment, the ratio is set to 1: 2. This value depends on the FET used.
It is necessary to adjust and change according to The FETs 5 to 8 and the FETs 9 to 12 are the same as the second embodiment in that they do not need to have the same characteristics, and can be replaced with dual gate FETs.

(Embodiment 4) FIG. 4 is a view for explaining another embodiment of the present invention. In FIG. 4, reference numeral 21 denotes FETs 1 to 12 of Embodiments 1, 2 and 3 and their biases. 1 shows a circuit, and 22 shows an in-phase signal suppression filter. 1
Reference numerals 3 to 18 are exactly the same as those of the corresponding symbols in the first, second and third embodiments. In the first and second embodiments, as described in the third embodiment, there is a possibility that a frequency twice the local oscillation frequency is radiated to the outside as unnecessary radiation. In the third embodiment, this point is improved. Strictly speaking, the phase of the frequency component twice as large as the local oscillation frequency does not completely reverse due to the capacitance component of the FET. Is not completely suppressed.

In this embodiment, at the terminals 25 and 26,
Unnecessary output at twice the local oscillation frequency is an in-phase signal, and since the required high-frequency signal is out of phase, it is designed to suppress the in-phase signal and pass the out-of-phase signal. This problem is improved by using a common-mode signal suppression filter. As an example of the in-phase suppression filter 22, several circuits can be easily considered as shown in FIGS. 5A to 5C, assuming that the frequency is f, the capacitance and the inductance are expressed by the equations (a) to (c) corresponding to the respective circuits (FIGS. 5A to 5C). Can be adjusted while satisfying the conditions, and a design can be made so that a required frequency band can be obtained. Also,
Examples 1, 2, 3 when the balance of the balun 17 is lost
In this case, a problem arises in that the balance of the high-frequency signal converted into the differential signal by the balun 17 is lost. As a result, the even-numbered intermodulation distortion component of the high-frequency signal output in the in-phase from the drain terminal is mainly used. The modulation distortion component also becomes unbalanced, and is output to the baseband signal output terminal 15 through the balun 18.

[0033]

(Equation 1)

In the fourth embodiment, since the common-mode component remaining in the high-frequency signal converted into the differential signal is removed by the common-mode suppression filter, the above-mentioned even-order intermodulation distortion component has no imbalance, and It is possible to prevent an even-order intermodulation distortion component from being output to the band signal output terminal. Here, even when the balance of the balun 18 is lost, even-order intermodulation distortion components are output to the baseband signal output terminal. However, since the baseband signal has a low frequency, the balance is easily different from that of the balun 17. Accuracy can be raised and no problem. Note that the capacitances and inductances indicated by the same symbols in FIG. 5 are preferably exactly the same, and it is desirable to use elements having good pairing properties simultaneously formed on the same substrate. Further, in the common-mode suppression filter, in an actual circuit, a resonance circuit can be formed using peripheral elements such as the inductance 23 shown in FIG.

(Embodiment 5) FIG. 6 is a view for explaining another embodiment of the present invention. In FIG. 6, reference numeral 21 denotes FETs 1 to 12 and the bias circuit thereof in Embodiments 1, 2, and 3. Is shown. Reference numerals 13 to 18 are exactly the same as those of the corresponding symbols in the first, second and third embodiments. In this embodiment, as described in the first, second, third, and fourth embodiments, the identity of the characteristics of the FET and the identity of the elements of the common-mode suppression filter are important in terms of circuit balance. IC enclosed by 28
As an example, these are fabricated on the same substrate. By doing so, the line length used for connection between the elements can be made the same in addition to the element characteristics, and the characteristics can be improved.

Here, in Examples 1, 2, 3, and 4, the FE
T, other than the element of the common mode suppression filter, the inductance 2
The identity of 3 is also important for circuit balance. However, for example, when the high-frequency frequency is 800 MHz, the inductance 23 needs to have a value of at least about 10 nH. In order to create a spiral inductance in the IC 28 using GaAs FETs used in this frequency band, 10 nH is required. 2 large inductance elements
Creating individual devices on a chip requires a large occupied area and is costly. In this embodiment, as a circuit combined with an in-phase suppression filter, only the pair of L6 in FIG.
An example is shown in which only the above is created. In this circuit format, for example, at 800 MHz, L6 = 3nH is 2
C6 = 7 pF, C7 = 27 pF, L7 = 27
The circuit configuration can be realized by mounting nH outside the chip, and is economically practical.

[0037]

Since the present invention is configured as described above, a harmonic mixer having characteristics of low distortion, low unnecessary radiation power and high gain can be obtained.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a harmonic mixer according to Embodiment 1 of the present invention.

FIG. 2 is a configuration diagram of a harmonic mixer according to Embodiment 2 of the present invention.

FIG. 3 is a configuration diagram of a harmonic mixer according to Embodiment 3 of the present invention.

FIG. 4 is a configuration diagram of a harmonic mixer according to Embodiment 4 of the present invention.

FIG. 5 shows a common-mode rejection filter used in Embodiment 4 of the present invention.

FIG. 6 is a configuration diagram of a harmonic mixer according to Embodiment 5 of the present invention.

FIG. 7 is a configuration diagram of a mixer using a conventional antiparallel diode.

[Explanation of symbols]

1-4: FETs having the same characteristics (first group of FETs), 5-8
... FETs with the same characteristics (second group of FETs), 9 to 12. FETs with the same characteristics (third group of FETs), 13... Local oscillation signal source, 14... High-frequency signal source, 15. ~ 18 ... Balun, 19,20 ... Bias power supply,
Reference numeral 21: bias circuit, 22: filter for suppressing an in-phase signal, 23: peripheral inductance, 27: power supply, 28 ...
IC circuit.

Claims (8)

[Claims] 1. A first FE comprising four FETs (field-effect transistors) each having a source terminal, a drain terminal, and a gate terminal and having the same characteristics.
T is connected between the source terminal and the drain terminal of the second FET, and between the source terminal and the drain terminal of the third FET and the fourth FET, and is connected to the first FET and the fourth FET.
The gate terminals of the FETs, and the second FET and the third FE
The first FET is differentially input from the gate terminal of the first FET and the gate terminal of the second FET, and the source terminal of the first FET is connected to the third FET.
Differential input of the second signal from the source terminal of the first F
A frequency converter characterized in that a third signal is differentially output from a drain terminal of an ET and a drain terminal of a third FET. 2. A bipolar transistor in place of each FET in claim 1, wherein an emitter terminal of the bipolar transistor corresponds to a source terminal of the FET, a base terminal corresponds to a gate terminal, and a collector terminal corresponds to a drain terminal. A frequency converter, characterized in that the frequency converter is connected by connecting. 3. The frequency according to claim 1, wherein a gate (or base) bias is set such that an ON time of each transistor is a time corresponding to a quarter cycle of a local oscillation frequency. converter. 4. A first group of FETs (first to fourth) comprising four FETs each having a source terminal, a drain terminal, and a gate terminal and having the same characteristics, and It comprises a second group of FETs (fifth to eighth) composed of four FETs having the same characteristics, the drain terminal of the first FET and the source terminal of the fifth FET, the drain terminal of the second FET and the source of the sixth FET. The terminals, the drain terminal of the third FET and the source terminal of the seventh FET, the drain terminal of the fourth FET and the source terminal of the eighth FET are connected, and the source terminals of the first and second FETs are connected.
And the source terminals of the third and fourth FETs are connected, the drain terminals of the fifth and sixth FETs are connected, and the drain terminals of the seventh and eighth FETs are connected, and the first, fourth, sixth and sixth FETs are connected. 7FET
And the gate terminals of the second FET, the third FET, the fifth FET, and the eighth FET are connected to each other,
The first from the gate terminal of the FET and the gate terminal of the third FET
Is differentially input, and the source terminal of the first FET and the fourth F
The second signal is differentially input from the source terminal of the ET, and the fifth signal
A frequency converter characterized in that a third signal is differentially output from a drain terminal of an ET and a drain terminal of a seventh FET. 5. The gate bias is set such that the ON time of each transistor is a time corresponding to a ３ cycle at a local oscillation frequency.
The frequency converter according to claim 1. 6. A first group of FETs (first to fourth) each including a source terminal, a drain terminal, and a gate terminal, each of which includes four FETs having the same characteristics, and The second group of FETs consisting of four FETs with the same characteristics
(Fifth to eighth) and a third group of FETs (ninth to twelfth) composed of four FETs having the same characteristics, the drain terminal of the fifth FET and the source terminal of the ninth FET, The drain terminal of the sixth FET is connected to the source terminal of the tenth FET, the drain terminal of the seventh FET is connected to the source terminal of the eleventh FET, the drain terminal of the eighth FET is connected to the source terminal of the twelfth FET, and the first FE is connected.
T, the second FET, the fifth FET, and the source terminal of the sixth FET, the third FET, the fourth FET, the seventh FET, and the eighth FE.
T source terminals, third FET, fourth FET and ninth F
ET and the drain terminal of the tenth FET, the first FET, the second FET, the drain terminal of the eleventh FET and the twelfth FET, the fifth FET, the eighth FET, the tenth FET, and the first
The gate terminals of the first FET, the sixth FET, the seventh FET, the ninth FET, the twelfth FET, the first FE
T and the gate terminals of the fourth and fourth FETs, and the gate terminals of the second and third FETs are connected, and a first signal is input in phase from the gate terminals of the first and fifth FETs, and the gate terminal of the second FET is connected. The first signal is inputted from the gate terminal of the sixth FET, and the first signal inputted from the gate terminal of the first FET and the first signal inputted from the gate terminal of the fifth FET are inputted in the opposite phases, and the source terminal of the first FET and the third FET are inputted.
Differential input of the second signal from the source terminal of the first FET
A differential signal is output from the drain terminal of the third FET and the drain terminal of the third FET. 7. A bias is set such that an ON time of each of the first to fourth FETs is a time corresponding to a quarter cycle of a local oscillation frequency, and an ON time of each of the fifth to twelfth FETs is set. 7. The frequency converter according to claim 6, wherein the bias is set so that the time becomes a time corresponding to a 3/4 cycle in the local oscillation frequency. 8. The frequency converter according to claim 1, further comprising a filter for suppressing an in-phase signal at the source terminal for differentially inputting a high-frequency signal.