JPH0365808A - Mixing circuit - Google Patents
Mixing circuitInfo
- Publication number
- JPH0365808A JPH0365808A JP20173989A JP20173989A JPH0365808A JP H0365808 A JPH0365808 A JP H0365808A JP 20173989 A JP20173989 A JP 20173989A JP 20173989 A JP20173989 A JP 20173989A JP H0365808 A JPH0365808 A JP H0365808A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- transistor
- circuit
- collector
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000003990 capacitor Substances 0.000 claims abstract description 9
- 238000006243 chemical reaction Methods 0.000 abstract description 3
- 230000010355 oscillation Effects 0.000 abstract description 3
- 101100535994 Caenorhabditis elegans tars-1 gene Proteins 0.000 abstract 2
- 230000003321 amplification Effects 0.000 abstract 1
- 238000003199 nucleic acid amplification method Methods 0.000 abstract 1
- 230000009977 dual effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
Landscapes
- Superheterodyne Receivers (AREA)
- Transceivers (AREA)
- Amplifiers (AREA)
Abstract
Description
【発明の詳細な説明】
く本発明の目的〉
[産業上の利用分野]
本発明は、無線機における送信部や受信部において、周
波数変換する混合回路に関する。DETAILED DESCRIPTION OF THE INVENTION OBJECTS OF THE INVENTION [Field of Industrial Application] The present invention relates to a mixing circuit that performs frequency conversion in a transmitting section or a receiving section of a radio device.
【従来の技術]
無線機の周波数変換回路として混合回路は重要な部分で
ある。従来の混合回路の多くはトランジスタやFETの
ベースやゲートで2つの信号を合わせ、トランジスタや
FETで増幅し、出力にタンク回路を設けて、和または
差の周波数を取り出していた。従来の回路としては、ト
ランジスタのベースに2つの信号を注入して増幅しなが
ら混合する回路が多く使われているが、入力のインピー
ダンスの変化によって影響を与え易いし、消費電流も多
い。他にバランスドミキサー回路やデュアルゲートFE
Tを用いた回路が利用されている。[Prior Art] A mixing circuit is an important part of a frequency conversion circuit of a radio device. In most conventional mixing circuits, two signals are combined at the base or gate of a transistor or FET, amplified by the transistor or FET, and a tank circuit is provided at the output to extract the sum or difference frequency. Conventional circuits often use a circuit that injects two signals into the base of a transistor and mixes them while amplifying them, but this is easily affected by changes in input impedance and consumes a large amount of current. In addition, balanced mixer circuit and dual gate FE
A circuit using T is used.
しかしバランスドミキサー回路は、回路が煩雑となり、
またデュアルゲートFETでは雑音が多い等の欠点があ
った。However, the balanced mixer circuit has a complicated circuit.
Further, the dual gate FET has drawbacks such as high noise.
[発明が解決しようとする課題1
しかし最近の回路では自動車電話、携帯電話等で、より
小型化、省消費電力化し、特性の優れた混合回路を必要
としている。[Problem to be Solved by the Invention 1] However, recent circuits such as car phones and mobile phones require hybrid circuits that are smaller, consume less power, and have excellent characteristics.
【本発明の目的1
本発明の目的は、小型化し、消費電流の小さい混合回路
を提供することにある。[Objective 1 of the present invention] An object of the present invention is to provide a miniaturized mixing circuit with low current consumption.
く本発明の構成〉
[課題を解決する手段]
そこで課題を解決するため、2個のトランジスタを直列
に接続し、それぞれのトランジスタのベースから局発信
号や変換すべき信号を入力し、コレクタより出力してい
る。Structure of the present invention> [Means for solving the problem] In order to solve the problem, two transistors are connected in series, a local oscillation signal or a signal to be converted is input from the base of each transistor, and a signal to be converted is input from the collector. It is outputting.
[作用及び実施例1 第1図は、本発明の実施例を示す回路図である。[Effect and Example 1 FIG. 1 is a circuit diagram showing an embodiment of the present invention.
第1トランジスタ1のベース側よりコンデンサ2を介し
て局発信号を入れる。第1トランジスタlのコレクタに
は抵抗3を介して第2トランジスタ4のエミッタが接続
されており、第1トランジスタlのコレクタから第2ト
ランジスタ4のベースに信号を伝達するためのコンデン
サ5が、第2トランジスタ3のエミッタからはコンデン
サ6を介して局発信号または受信信号等周波数変換すべ
き信号が入力され、第2トランジスタ3のコレクタには
タンク回路7を設け、必要な周波数に同調させ、出力し
ている。抵抗8.9,10,11は、バイアス用抵抗で
ある。A local signal is input from the base side of the first transistor 1 via a capacitor 2. The emitter of a second transistor 4 is connected to the collector of the first transistor l via a resistor 3, and a capacitor 5 for transmitting a signal from the collector of the first transistor l to the base of the second transistor 4 is connected to the collector of the first transistor l. A signal to be frequency-converted, such as a local signal or a received signal, is input from the emitter of the second transistor 3 via a capacitor 6, and a tank circuit 7 is provided at the collector of the second transistor 3 to tune it to the required frequency and output it. are doing. Resistors 8.9, 10, and 11 are bias resistors.
信号の流れとしては、直流的には、トランジスタは直列
になるが、高周波的には端子20から入った信号は第1
トランジスタlで増幅され、コレクタから出力し、コン
デンサ5を経て第2トランジスタ4に入力する。一方端
子21からの信号は、第2トランジスタ4に入力される
。混合された信号は第2トランジスタで増幅され、タン
ク回路により選択され、端子22より出力される。端子
23は電源入力である。In terms of signal flow, in terms of direct current, the transistors are connected in series, but in terms of high frequency, the signal input from terminal 20 is connected to the first
It is amplified by the transistor l, outputted from the collector, and inputted to the second transistor 4 via the capacitor 5. On the other hand, a signal from the terminal 21 is input to the second transistor 4. The mixed signal is amplified by the second transistor, selected by the tank circuit, and output from the terminal 22. Terminal 23 is a power input.
このようにトランジスタを2個直列に接続させ、各トラ
ンジスタのベースに信号を注入し、第2トランジスタの
コレクタから出力することにより増幅しながら周波数混
合させられる。消費電流は、トランジスタを直列にした
ことによって従来の回路より少なくなった。In this way, by connecting two transistors in series, injecting a signal into the base of each transistor, and outputting it from the collector of the second transistor, the signal is amplified and mixed in frequency. Current consumption is lower than in conventional circuits because the transistors are connected in series.
そして本発明によって、他の混合回路、例えばデュアル
ゲートに比べ雑音が少なく、またバランスドミキサー回
路に比べ回路構成が簡単になった。According to the present invention, the noise is lower than that of other mixing circuits, such as dual gates, and the circuit configuration is simpler than that of a balanced mixer circuit.
く本発明の効果〉
本発明は、トランジスタを直列に接続し、それぞれのト
ランジスタのベースから信号を入力することにより、従
来の回路に比べ消費電流が小さくなり、回路の省消費電
力化が実現した。また回路部品が少ないことから小型化
し、自動車電話や携帯電話のようにより小型化、省消費
電力が必要なところには大変有効である。Effects of the Invention The present invention reduces current consumption compared to conventional circuits by connecting transistors in series and inputting signals from the base of each transistor, resulting in reduced power consumption of the circuit. . In addition, because there are fewer circuit parts, it can be miniaturized, making it very effective for applications that require smaller size and lower power consumption, such as car phones and mobile phones.
第1図は、本発明の実施例を示す回路図である。
l・・・・・・・・・第1トランジスタ、2・・・・・
・・・・第2トランジスタ、5・・・・・・・・・コン
デンサFIG. 1 is a circuit diagram showing an embodiment of the present invention. l......First transistor, 2...
...Second transistor, 5...Capacitor
Claims (1)
2の信号を第2トランジスタのベースに入力する混合回
路において、第1トランジスタのコレクタと第2トラン
ジスタのエミッタが接続され、該第1トランジスタのコ
レクタと該第2トランジスタのベースとの間にコンデン
サを接続し、第2トランジスタのコレクタから出力した
ことを特徴とする混合回路。In a mixing circuit that inputs a first signal to the base of the first transistor and inputs the second signal to the base of the second transistor, the collector of the first transistor and the emitter of the second transistor are connected, and the collector of the first transistor is connected to the emitter of the second transistor. A mixing circuit characterized in that a capacitor is connected between the collector of the second transistor and the base of the second transistor, and the output is output from the collector of the second transistor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20173989A JPH0767049B2 (en) | 1989-08-03 | 1989-08-03 | Mixed circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20173989A JPH0767049B2 (en) | 1989-08-03 | 1989-08-03 | Mixed circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0365808A true JPH0365808A (en) | 1991-03-20 |
JPH0767049B2 JPH0767049B2 (en) | 1995-07-19 |
Family
ID=16446137
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP20173989A Expired - Fee Related JPH0767049B2 (en) | 1989-08-03 | 1989-08-03 | Mixed circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0767049B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012024467A (en) * | 2010-07-27 | 2012-02-09 | Keiko Nagayoshi | Wheelchair |
-
1989
- 1989-08-03 JP JP20173989A patent/JPH0767049B2/en not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012024467A (en) * | 2010-07-27 | 2012-02-09 | Keiko Nagayoshi | Wheelchair |
Also Published As
Publication number | Publication date |
---|---|
JPH0767049B2 (en) | 1995-07-19 |
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