JPH0767049B2 - Mixed circuit - Google Patents
Mixed circuitInfo
- Publication number
- JPH0767049B2 JPH0767049B2 JP20173989A JP20173989A JPH0767049B2 JP H0767049 B2 JPH0767049 B2 JP H0767049B2 JP 20173989 A JP20173989 A JP 20173989A JP 20173989 A JP20173989 A JP 20173989A JP H0767049 B2 JPH0767049 B2 JP H0767049B2
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- circuit
- signal
- collector
- capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Superheterodyne Receivers (AREA)
- Transceivers (AREA)
- Amplifiers (AREA)
Description
【発明の詳細な説明】 ＜本発明の目的＞ ［産業上の利用分野］ 本発明は、無線機における送信部や受信部において、周
波数変換する混合回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] [Industrial field of application] The present invention relates to a mixing circuit for frequency conversion in a transmitter and a receiver of a radio device.
［従来の技術］ 無線機の周波数変換回路として混合回路は重要な部分で
ある。従来の混合回路は多くはトランジスタやFETのベ
ースやゲートで２つの信号を合わせ、トランジスタやFE
Tで増幅し、出力にタンク回路を設けて、和または差の
周波数を取り出していた。従来の回路としては、トラン
ジスタのベースに２つの信号を注入して増幅しながら混
合する回路が多く使われているが、入力のインピーダン
スの変化によって影響を与え易いし、消費電流も多い。
他にバランスドミキサー回路やデュアルゲートFETを用
いた回路が利用されている。しかしバランスドミキサー
回路は、回路が煩雑となり、またデュアルゲートFETで
は雑音が多い等の欠点があった。[Prior Art] A mixing circuit is an important part of a frequency conversion circuit of a wireless device. Most conventional mixing circuits combine two signals at the base or gate of a transistor or FET,
It was amplified by T, and a tank circuit was installed at the output to take out the sum or difference frequency. As a conventional circuit, a circuit in which two signals are injected into the base of a transistor and mixed while being amplified is often used, but it is easily affected by a change in input impedance and consumes a large amount of current.
In addition, circuits using balanced mixer circuits and dual gate FETs are used. However, the balanced mixer circuit has a drawback that the circuit becomes complicated and that the dual gate FET is noisy.
［発明が解決しようとする課題］ しかし最近の回路では自動車電話、携帯電話等で、より
小型化、省消費電力化し、特性の優れた混合回路を必要
としている。[Problems to be Solved by the Invention] However, in recent circuits, there is a need for a mixed circuit which is smaller in size, consumes less power, and has excellent characteristics in automobile phones, mobile phones, and the like.
［発明の目的］ 本発明の目的は、小型化し、消費電力の小さい混合回路
を提供することにある。[Object of the Invention] An object of the present invention is to provide a miniaturized and low power consumption mixing circuit.
＜本発明の構成＞ ［課題を解決する手段］ ここで課題を解決するため、２個のトランジスタを直列
に接続し、それぞれのトランジスタのベースから局発信
号や変換すべき信号を入力し、コレクタより出力してい
る。<Structure of the Present Invention> [Means for Solving the Problems] In order to solve the problems, two transistors are connected in series, and a local signal or a signal to be converted is input from the bases of the respective transistors, and a collector is connected. More output.
［作用及び実施例］ 第１図は、本発明の実施例を示す回路図である。第１ト
ランジスタ１のベース側よりコンデンサ２を介して局発
信号を入れる。第１トランジスタ１のコレクタには抵抗
３を介して第２トランジスタ４のエミッタが接続されて
おり、第１トランジスタ１のコレクタから第２トランジ
スタ４のベースに信号を伝達するためのコンデンサ５
が、第２トランジスタ４のエミッタからはコンデンサ６
を介して局発信号または受信信号等周波数変換すべき信
号が入力され、第２トランジスタ４のコレクタにはフィ
ルタ回路７を設け、必要は周波数に同調させ、出力して
いる。抵抗8,9,10,11は、バイアス用抵抗である。又、
第２トランジスタ４のエミッタと接地間に接続されてい
るコンデンサは、バイパス用コンデンサである。[Operation and Embodiment] FIG. 1 is a circuit diagram showing an embodiment of the present invention. A local signal is input from the base side of the first transistor 1 via the capacitor 2. The collector of the first transistor 1 is connected to the emitter of the second transistor 4 via the resistor 3, and the capacitor 5 for transmitting a signal from the collector of the first transistor 1 to the base of the second transistor 4 is connected.
However, from the emitter of the second transistor 4, the capacitor 6
A signal to be frequency-converted, such as a local oscillation signal or a reception signal, is input via, and a filter circuit 7 is provided in the collector of the second transistor 4, and if necessary, is tuned to the frequency and output. The resistors 8, 9, 10 and 11 are bias resistors. or,
The capacitor connected between the emitter of the second transistor 4 and the ground is a bypass capacitor.
信号の流れとしては、直流的には、トランジスタは直列
になるが、高周波的には端子20から入った信号は第１ト
ランジスタ１で増幅され、コレクタから出力し、コンデ
ンサ５を経て第２トランジスタ４に入力する。一方端子
21からの信号は、第２トランジスタ４に入力される。混
合された信号は第２トランジスタで増幅され、フィルタ
回路により選択され、端子22より出力される。端子23は
電源入力である。As for the signal flow, the transistors are serially connected in terms of direct current, but in terms of high frequency, the signal input from the terminal 20 is amplified by the first transistor 1, output from the collector, and passed through the capacitor 5 to the second transistor 4 To enter. One terminal
The signal from 21 is input to the second transistor 4. The mixed signal is amplified by the second transistor, selected by the filter circuit, and output from the terminal 22. Terminal 23 is a power input.
このようにトランジスタを２個直列に接続させ、各トラ
ンジスタのベースに信号を注入し、第２トランジスタの
コレクタから出力することにより増幅しながら周波数混
合させられる。消費電流は、トランジスタを直列にした
ことによって従来の回路より少なくなった。In this way, two transistors are connected in series, a signal is injected into the base of each transistor, and the signal is output from the collector of the second transistor, whereby the frequencies are mixed while being amplified. The current consumption is lower than that of the conventional circuit because the transistors are connected in series.
そして本発明によって、他の混合回路、例えばデュアル
ゲートに比べ雑音が少なく、またバランスドミキサー回
路に比べ回路構成が簡単になった。The present invention has less noise than other mixing circuits, for example, dual gates, and has a simpler circuit configuration than the balanced mixer circuit.
＜本発明の効果＞ 本発明は、トランジスタを直列に接続し、それぞれのト
ランジスタのベースから信号を入力することにより、従
来の回路に比べ消費電流が小さくなり、回路の省消費電
力化が実現した。また回路部品が少ないことから小型化
し、自動車電話や携帯電話のようにより小型化、省消費
電力が必要なところには大変有効である。<Effects of the Present Invention> According to the present invention, by connecting transistors in series and inputting a signal from the base of each transistor, current consumption becomes smaller than that of a conventional circuit, and power consumption of the circuit is reduced. . In addition, it is very effective in places where miniaturization is required due to the small number of circuit components, and miniaturization and power saving are required, such as in automobiles and mobile phones.
第１図は、本発明の実施例を示す回路図である。 １……第１トランジスタ、 ４……第２トランジスタ、 ５……コンデンサ FIG. 1 is a circuit diagram showing an embodiment of the present invention. 1 ... First transistor, 4 ... Second transistor, 5 ... Capacitor
Claims (1)
入力し、第２の信号を第２トランジスタのベースに入力
する混合回路において、第１トランジスタのコレクタと
第２トランジスタのエミッタが抵抗を介して接続され、
該第２トランジスタのエミッタがコンデンサを介して接
地されており、該第１トランジスタのコレクタと該第２
トランジスタのベースとの間にコンデンサを接続し、第
２トランジスタのコレクタから出力したことを特徴とす
る混合回路。1. In a mixing circuit for inputting a first signal to the base of a first transistor and inputting a second signal to the base of a second transistor, the collector of the first transistor and the emitter of the second transistor are resistors. Connected through
The emitter of the second transistor is grounded via a capacitor, and the collector of the first transistor and the second transistor
A mixing circuit characterized in that a capacitor is connected between the base of the transistor and the output of the collector of the second transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20173989A JPH0767049B2 (en) | 1989-08-03 | 1989-08-03 | Mixed circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20173989A JPH0767049B2 (en) | 1989-08-03 | 1989-08-03 | Mixed circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0365808A JPH0365808A (en) | 1991-03-20 |
| JPH0767049B2 true JPH0767049B2 (en) | 1995-07-19 |
Family
ID=16446137
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20173989A Expired - Fee Related JPH0767049B2 (en) | 1989-08-03 | 1989-08-03 | Mixed circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0767049B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4730859B1 (en) * | 2010-07-27 | 2011-07-20 | 惠子 永吉 | wheelchair |
-
1989
- 1989-08-03 JP JP20173989A patent/JPH0767049B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0365808A (en) | 1991-03-20 |
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Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
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| LAPS | Cancellation because of no payment of annual fees |