JPH0955677A - Electronic tuner circuit - Google Patents

Electronic tuner circuit

Info

Publication number
JPH0955677A
JPH0955677A JP7208698A JP20869895A JPH0955677A JP H0955677 A JPH0955677 A JP H0955677A JP 7208698 A JP7208698 A JP 7208698A JP 20869895 A JP20869895 A JP 20869895A JP H0955677 A JPH0955677 A JP H0955677A
Authority
JP
Japan
Prior art keywords
circuit
intermediate frequency
capacitor
balanced
resistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP7208698A
Other languages
Japanese (ja)
Inventor
Takeshi Okubo
健 大久保
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP7208698A priority Critical patent/JPH0955677A/en
Publication of JPH0955677A publication Critical patent/JPH0955677A/en
Withdrawn legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To obtain stably a selectivity characteristic and a power gain and to obtain a high inter-modulation performance without being affected by an impedance of a post-stage intermediate frequency amplifier circuit. SOLUTION: An output terminal O1 of a balanced output of a balanced output form U/V integrated circuit (U/VIC) 15 is connected to a parallel resonance circuit 32 consisting of a capacitor CO5 and a coil L02 being a single tuning circuit via a series circuit 31 consisting of a resistor R3 and a capacitor CO1. An intermediate frequency signal extracted by the parallel resonance circuit 32 is outputted from an output terminal 20 via a buffer circuit 33 consisting of a transistor(TR) QO2 of common emitter. On the other hand, the other signal of balanced outputs of the U/VIC 15 is connected to ground by a series circuit 30 consisting of a resistor R4 and a capacitor CO2.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、テレビジョン信号受信
回路に用いて好適な電子同調チューナ回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic tuning tuner circuit suitable for use in a television signal receiving circuit.

【0002】[0002]

【従来の技術】図3は従来のUHF・VHF一体化した
電子同調チューナ回路の構成を示すブロック図である。
この図において、入力端子10に供給されたUHF及び
VHF信号のうち、UHFのチャンネル信号は単同調回
路11で選択され、VHFのチャンネル信号は単同調回
路12で選択される。単同調回路11で選択されたUH
Fのチャンネルの信号は高周波増幅回路13で増幅され
て複同調回路14を経た後、U/V集積回路(以下U/
VICという)15に入力される。他方、単同調回路1
2で選択されたVHFのチャンネルの信号は高周波増幅
回路16で増幅されて複同調回路17を経た後、U/V
IC15に入力される。このU/VIC15はUHF、
VHFそれぞれ専用の局部発振回路及び混合回路を有し
た集積回路であり、入力信号を中間周波信号に変換して
平衡出力する。U/VIC15の出力側にはU/VIC
15の平衡出力を不平衡出力に変換する平衡/不平衡変
換回路18が接続され、更にこの平衡/不平衡変換回路
18の出力側に単同調回路19が接続される。この単同
調回路19からの中間周波信号が出力端子20を介して
図示せぬ次段の中間周波増幅回路に入力される。
2. Description of the Related Art FIG. 3 is a block diagram showing the structure of a conventional UHF / VHF integrated electronic tuning tuner circuit.
In the figure, of the UHF and VHF signals supplied to the input terminal 10, the UHF channel signal is selected by the single tuning circuit 11, and the VHF channel signal is selected by the single tuning circuit 12. UH selected by single tuning circuit 11
The signal of the F channel is amplified by the high-frequency amplifier circuit 13, passes through the double tuning circuit 14, and then the U / V integrated circuit (hereinafter referred to as U / V).
VIC) 15. On the other hand, single tuning circuit 1
The signal of the VHF channel selected in 2 is amplified by the high frequency amplifier circuit 16 and passes through the double tuning circuit 17, and then the U / V
Input to IC15. This U / VIC15 is UHF,
It is an integrated circuit having a local oscillation circuit and a mixing circuit dedicated to each VHF, and converts an input signal into an intermediate frequency signal and outputs it in a balanced manner. U / VIC on the output side of U / VIC15
A balanced / unbalanced conversion circuit 18 for converting the balanced output of 15 into an unbalanced output is connected, and a single tuning circuit 19 is connected to the output side of the balanced / unbalanced conversion circuit 18. The intermediate frequency signal from the single tuning circuit 19 is input to the next stage intermediate frequency amplifier circuit (not shown) via the output terminal 20.

【0003】図4はU/VIC15の出力側に設けられ
た平衡/不平衡変換回路18及び単同調回路19の詳細
な構成を示す図であり、この図に示すように巻数比が
N:1の変換トランスTo1の一次側巻線の一端が結合
コンデンサCo1を介してU/VIC15の一方の出力
端O1に接続され、一次側巻線の他端が結合コンデンサ
Co2を介してU/VIC15の他方の出力端O2に接
続されている。他方、変換トランスTo1の二次側巻線
の一端が中間周波数共振コイルLo1、コンデンサCo
3を介して出力端子20に接続され、二次側巻線の他端
が接地されている。コンデンサCo3と出力端子20と
の間と接地との間にコンデンサCo4が接続されてい
る。変換トランスTo1によりU/VIC15の平衡出
力が不平衡出力に変換され、またこの変換トランスTo
1の巻数比(N:1)によりインピーダンスの変換が行
なわれる。また変換トランスTo1、中間周波数共振コ
イルLo1及び共振コンデンサCo3、Co4が中間周
波に共振する直列共振回路を構成し、出力端20に中間
周波信号を取り出す。
FIG. 4 is a diagram showing a detailed configuration of the balanced / unbalanced conversion circuit 18 and the single tuning circuit 19 provided on the output side of the U / VIC 15. As shown in FIG. 4, the winding ratio is N: 1. One end of the primary winding of the conversion transformer To1 is connected to one output end O1 of the U / VIC 15 via the coupling capacitor Co1, and the other end of the primary winding is connected to the other end of the U / VIC 15 via the coupling capacitor Co2. Is connected to the output terminal O2. On the other hand, one end of the secondary winding of the conversion transformer To1 has an intermediate frequency resonance coil Lo1 and a capacitor Co.
It is connected to the output terminal 20 via 3 and the other end of the secondary winding is grounded. The capacitor Co4 is connected between the capacitor Co3 and the output terminal 20 and the ground. The conversion transformer To1 converts the balanced output of the U / VIC 15 into an unbalanced output.
Impedance conversion is performed by a turn ratio of 1 (N: 1). Further, the conversion transformer To1, the intermediate frequency resonance coil Lo1, and the resonance capacitors Co3 and Co4 form a series resonance circuit that resonates at an intermediate frequency, and the intermediate frequency signal is taken out at the output end 20.

【0004】[0004]

【発明が解決しようとする課題】ところで、上述した従
来の電子同調チューナ回路にあっては、U/VIC15
の出力を変換トランスTo1と中間周波数共振コイルL
o1及び共振コンデンサCo3、Co4により後段の中
間周波増幅回路に供給するようにしているが、この構成
では後段の中間周波増幅回路の入力インピーダンスの影
響を受け易いので、選択度特性や電力利得が不安定にな
り、また混変調性能が低下するという問題点があった。
なお、混変調性能は変換トランスTo1の仕様により左
右されるが、この変換トランスTo1では平衡性能が充
分に得られない。また、直列共振回路の特性である選択
度特性はインピーダンスが変ることにより変化してしま
う。
By the way, in the conventional electronic tuning tuner circuit described above, the U / VIC 15 is used.
Output of the conversion transformer To1 and intermediate frequency resonance coil L
o1 and the resonance capacitors Co3 and Co4 are supplied to the intermediate frequency amplifier circuit in the subsequent stage, but this configuration is easily affected by the input impedance of the intermediate frequency amplifier circuit in the subsequent stage, so that the selectivity characteristic and the power gain are unsatisfactory. There is a problem that it becomes stable and intermodulation performance is deteriorated.
The cross-modulation performance depends on the specifications of the conversion transformer To1, but the conversion transformer To1 cannot obtain sufficient balance performance. Further, the selectivity characteristic, which is the characteristic of the series resonant circuit, changes due to the change in impedance.

【0005】そこで本発明は、後段の中間周波増幅回路
の入力インピーダンスの影響を受けることがなく、選択
度特性や電力利得が安定して得られると共に高い混変調
性能が得られる電子同調チューナ回路を提供することを
目的としている。
Therefore, the present invention provides an electronic tuning tuner circuit which is not affected by the input impedance of the intermediate frequency amplifier circuit in the subsequent stage, and which can stably obtain the selectivity characteristic and the power gain and can obtain the high intermodulation performance. It is intended to be provided.

【0006】[0006]

【課題を解決するための手段】請求項1の発明は、UH
F、VHFそれぞれ専用の局部発振回路及び混合回路か
ら成り、入力信号を変換して得た中間周波信号を平衡出
力するU/V集積回路を備えた電子同調チューナ回路に
おいて;前記U/V集積回路の平衡出力端の一方に接続
される抵抗とコンデンサとから成る第1の直列回路と;
この第1の直列回路に接続され、中間周波信号を取り出
すための同調回路と;この同調回路により取り出された
中間周波信号を出力するバッファ回路と;前記U/V集
積回路の平衡出力端の他方を接地する抵抗とコンデンサ
とから成る第2の直列回路と;を具備している。
The invention according to claim 1 is UH
An electronic tuning tuner circuit comprising a U / V integrated circuit which comprises a local oscillation circuit and a mixing circuit dedicated to F and VHF, respectively, and which balance-outputs an intermediate frequency signal obtained by converting an input signal; said U / V integrated circuit A first series circuit consisting of a resistor and a capacitor connected to one of the balanced output terminals of
A tuning circuit connected to the first series circuit for extracting the intermediate frequency signal; a buffer circuit for outputting the intermediate frequency signal extracted by the tuning circuit; the other of the balanced output terminals of the U / V integrated circuit A second series circuit composed of a resistor and a capacitor for grounding.

【0007】[0007]

【発明の実施の形態】以下、本発明の実施の形態につい
て図面を参照して説明する。図1は実施例の電子同調チ
ューナ回路のU/V集積回路の後段の回路構成を示す図
である。なお、この図において前述した図4と共通する
部分には同一の符号を付ける。この図において、U/V
IC15の他方の出力端O2が抵抗R4とコンデンサC
o2とから成る直列回路30により接地され、一方の出
力端O1が抵抗R3とコンデンサCo1とから成る直列
回路31を介して単同調回路であるコンデンサCo5と
コイルLo2とから成る並列共振回路32に接続されて
いる。抵抗R3及びR4は200Ω以上の同じ抵抗値の
ものが使用され、並列共振回路32のコンデンサCo5
とコイルLo2は中間周波数が同調する値のものが使用
されている。並列共振回路32にて取り出された中間周
波信号はエミッタ接地したトランジスタQo2からなる
バッファ回路33を介して出力端20から出力される。
このバッファ回路33のトランジスタQo2のコレクタ
には抵抗R8を介して電圧Vccが印加される。
BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing the circuit configuration of the latter stage of the U / V integrated circuit of the electronic tuning tuner circuit of the embodiment. In this figure, the same parts as those in FIG. 4 described above are designated by the same reference numerals. In this figure, U / V
The other output terminal O2 of the IC15 has a resistor R4 and a capacitor C.
It is grounded by a series circuit 30 composed of o2 and one output terminal O1 is connected to a parallel resonance circuit 32 composed of a capacitor Co5 and a coil Lo2, which is a single tuning circuit, via a series circuit 31 composed of a resistor R3 and a capacitor Co1. Has been done. The resistors R3 and R4 having the same resistance value of 200Ω or more are used, and the capacitor Co5 of the parallel resonance circuit 32 is used.
The coil Lo2 having a value with which the intermediate frequency is tuned is used. The intermediate frequency signal extracted by the parallel resonance circuit 32 is output from the output terminal 20 via the buffer circuit 33 including the transistor Qo2 whose emitter is grounded.
The voltage Vcc is applied to the collector of the transistor Qo2 of the buffer circuit 33 via the resistor R8.

【0008】U/VIC15が平衡出力であることか
ら、負荷を平衡にすることと高インピーダンスで平衡出
力信号を引き出す必要があるが、直列回路30、31を
平衡出力端に接続することで平衡負荷と同等になり、U
/VIC15の内部の高周波電流が少なく、かつ平衡と
なることで打ち消し合う。この結果、一方の高周波電流
から他方の高周波電流に対して変調が殆どかからないの
で、高い混変調性能が得られる。またバッファ回路33
を設けることで負荷インピーダンスが高くとれる。この
場合、U/VIC15に要求される一般的な負荷インピ
ーダンスは図2に示すように300Ω以上であるが、従
来の変換トランスTo1では必ずしもこの値を満たすこ
とができず、充分な平衡特性が得られなかった。しか
し、このバッファ回路33を設けることでU/VIC1
5の負荷インピーダンスが充分に高くなり、これによっ
て次段の中間周波増幅回路の入力インピーダンスの影響
が少なくなり、選択度特性及び電力利得が安定化する。
Since the U / VIC 15 has a balanced output, it is necessary to balance the load and extract a balanced output signal with high impedance. However, by connecting the series circuits 30 and 31 to the balanced output terminal, the balanced load can be obtained. Becomes equivalent to U
The high-frequency currents inside the / VIC 15 are small and balanced, and they cancel each other out. As a result, modulation is hardly applied from one high-frequency current to the other high-frequency current, so that high intermodulation performance can be obtained. In addition, the buffer circuit 33
The load impedance can be made high by providing. In this case, the general load impedance required for the U / VIC 15 is 300Ω or more as shown in FIG. 2, but the conventional conversion transformer To1 cannot always satisfy this value, and sufficient balance characteristics are obtained. I couldn't do it. However, by providing this buffer circuit 33, the U / VIC1
The load impedance of No. 5 becomes sufficiently high, so that the influence of the input impedance of the intermediate frequency amplifier circuit of the next stage is reduced, and the selectivity characteristic and the power gain are stabilized.

【0009】このように、平衡出力形式のU/VIC1
5の平衡出力の一方を抵抗R3とコンデンサCo1とか
ら成る直列回路31により取り出して単同調回路32に
供給し、単同調回路32で同調した中間周波信号をバッ
ファ回路33を介して出力端子20から出力する一方、
U/VIC15の平衡出力の他方を抵抗R4とコンデン
サCo2とから成る直列回路30により接地する。これ
により、U/VIC15の内部の高周波電流が少なくな
ると共に打ち消し合うので、一方の高周波電流から他方
の高周波電流に対して変調が殆どかからず、高い混変調
性能が得られる。またバッファ回路33を設けることで
U/VIC15の負荷インピーダンスが充分に高くなる
ので、選択度特性及び電力利得が安定化する。
In this way, the balanced output type U / VIC1 is used.
One of the balanced outputs of 5 is taken out by a series circuit 31 composed of a resistor R3 and a capacitor Co1 and supplied to a single tuning circuit 32, and an intermediate frequency signal tuned by the single tuning circuit 32 is output from an output terminal 20 via a buffer circuit 33. While outputting
The other balanced output of the U / VIC 15 is grounded by the series circuit 30 including the resistor R4 and the capacitor Co2. As a result, the high-frequency current inside the U / VIC 15 decreases and cancels each other, so that one high-frequency current hardly modulates the other high-frequency current, and high intermodulation performance can be obtained. Further, since the load impedance of the U / VIC 15 is sufficiently increased by providing the buffer circuit 33, the selectivity characteristic and the power gain are stabilized.

【0010】[0010]

【発明の効果】請求項1の発明によれば、平衡出力形式
のU/V集積回路の平衡出力の一方を抵抗とコンデンサ
とから成る直列回路により取り出して並列共振回路に供
給し、この並列共振回路で同調した中間周波信号をバッ
ファ回路から出力する一方、U/V集積回路の平衡出力
の他方を抵抗とコンデンサとから成る直列回路により接
地するので、高い混変調性能が得られると共に選択度特
性及び電力利得が安定した電子同調チューナが実現でき
る。
According to the invention of claim 1, one of the balanced outputs of the U / V integrated circuit of the balanced output type is taken out by a series circuit composed of a resistor and a capacitor and supplied to a parallel resonant circuit, and the parallel resonant circuit is provided. While the intermediate frequency signal tuned by the circuit is output from the buffer circuit, the other of the balanced outputs of the U / V integrated circuit is grounded by the series circuit including the resistor and the capacitor, so that high intermodulation performance can be obtained and selectivity characteristics can be obtained. Also, an electronic tuning tuner with a stable power gain can be realized.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施の形態である電子同調チューナ回
路のU/V集積回路の後段の回路構成を示す図である。
FIG. 1 is a diagram showing a circuit configuration of a latter stage of a U / V integrated circuit of an electronic tuning tuner circuit according to an embodiment of the present invention.

【図2】U/V集積回路の負荷インピーダンスに対する
混変調の度合いを示す図である。
FIG. 2 is a diagram showing the degree of intermodulation with respect to the load impedance of a U / V integrated circuit.

【図3】従来の電子同調チューナ回路の構成を示すブロ
ック図である。
FIG. 3 is a block diagram showing a configuration of a conventional electronic tuning tuner circuit.

【図4】従来の電子同調チューナ回路のU/V集積回路
の後段の回路構成を示す図である。
FIG. 4 is a diagram showing a circuit configuration of a subsequent stage of a U / V integrated circuit of a conventional electronic tuning tuner circuit.

【符号の説明】[Explanation of symbols]

15 U/V集積回路 30 直列回路(第2の直列回路) 31 直列回路(第1の直列回路) 32 同調回路 33 バッファ回路 15 U / V integrated circuit 30 series circuit (second series circuit) 31 series circuit (first series circuit) 32 tuning circuit 33 buffer circuit

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 UHF、VHFそれぞれ専用の局部発振
回路及び混合回路から成り、入力信号を変換して得た中
間周波信号を平衡出力するU/V集積回路を備えた電子
同調チューナ回路において;前記U/V集積回路の平衡
出力端の一方に接続される抵抗とコンデンサとから成る
第1の直列回路と;この第1の直列回路に接続され、中
間周波信号を取り出すための同調回路と;この同調回路
により取り出された中間周波信号を出力するバッファ回
路と;前記U/V集積回路の平衡出力端の他方を接地す
る抵抗とコンデンサとから成る第2の直列回路と;を具
備したことを特徴とする電子同調チューナ回路。
1. An electronic tuning tuner circuit comprising a U / V integrated circuit which comprises a local oscillation circuit and a mixing circuit dedicated to each of UHF and VHF, and balance-outputs an intermediate frequency signal obtained by converting an input signal; A first series circuit consisting of a resistor and a capacitor connected to one of the balanced outputs of the U / V integrated circuit; a tuning circuit connected to the first series circuit for extracting the intermediate frequency signal; A buffer circuit for outputting the intermediate frequency signal extracted by the tuning circuit; and a second series circuit composed of a resistor and a capacitor for grounding the other of the balanced output terminals of the U / V integrated circuit. Electronic tuning tuner circuit.
JP7208698A 1995-08-16 1995-08-16 Electronic tuner circuit Withdrawn JPH0955677A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7208698A JPH0955677A (en) 1995-08-16 1995-08-16 Electronic tuner circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7208698A JPH0955677A (en) 1995-08-16 1995-08-16 Electronic tuner circuit

Publications (1)

Publication Number Publication Date
JPH0955677A true JPH0955677A (en) 1997-02-25

Family

ID=16560600

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7208698A Withdrawn JPH0955677A (en) 1995-08-16 1995-08-16 Electronic tuner circuit

Country Status (1)

Country Link
JP (1) JPH0955677A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100366823B1 (en) * 2000-01-12 2003-01-09 알프스 덴키 가부시키가이샤 Intermediate frquency input circuit
US7567784B2 (en) 2005-07-05 2009-07-28 Samsung Electronics Co., Ltd. Tuner, broadcast signal processing apparatus comprising the same, and broadcast signal processing method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100366823B1 (en) * 2000-01-12 2003-01-09 알프스 덴키 가부시키가이샤 Intermediate frquency input circuit
US7567784B2 (en) 2005-07-05 2009-07-28 Samsung Electronics Co., Ltd. Tuner, broadcast signal processing apparatus comprising the same, and broadcast signal processing method

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Legal Events

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Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 20021105