JPS60179786A - Video ram control system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a video RAM control method for a display device.

In the conventional video RAM control method, a signal from an input circuit is written into one video RAM, and the video information written in the video RAM is read out at regular intervals and displayed on a display device. . Therefore, in the one video RAM, writing cannot be performed while reading is being performed, and writing is often delayed, resulting in a slow processing speed.

It is an object of the present invention to solve the above-mentioned disadvantages and to improve the display processing speed of a display device by reducing the number of write-in states.

To achieve the above object, the present invention provides a plurality of video RAMs arranged in parallel, an input side switching circuit for sequentially writing data into the plurality of video RAMs;
and an output-side switching circuit for sequentially reading from the AM, the display device sequentially reading out video information sequentially written to the plurality of video RAMs via the input-side switching circuit via the output-side switching circuit. This is a video RAM control method that is characterized by displaying images on a continuous basis.

Therefore, for example, if there are two video RAMs, one R
When reading from AM is being performed, it is possible to write to the other RAM, and when reading from the other RAM is being performed, it is possible to write to one RAM, reducing the state of writing. This makes it possible to improve processing speed.

FIG. 1 is a block diagram showing an example of a graphic display device for implementing the above invention, and FIG. 2 is a block diagram showing a video RAM.
FIG. 2 is a block diagram showing parts in more detail. The display device 1 is a CPU 3. ROM5. Has RAM7, serial l10
The configuration allows communication with the main control unit via 9. The keyboard 11 is a keyboard interface (not shown).
, and connected to the bus via parallel l1013,
CRT 15 does not show the CRT eraser interface)
It is connected to the parallel-to-serial conversion circuit 17 via. Communication information with the main control unit, graphic information, and graphic information from the keyboard 11 are sent to the CPU in response to a signal from the display address management counter 19.
Processed in 3. Note that in this example, the interrupt processing unit 2
3 is set up.

Referring to FIG. 2, two video RAMs (I), (■
) are provided in parallel, an input side switching circuit 25 is provided between the processing circuit (input circuit) 21 by the CPU 3, and an output side switching circuit 27 is provided between the parallel serial conversion circuit 17. In Figure 3, the signals indicated by .are respectively the horizontal synchronizing signal, horizontal retrace signal, vertical retrace signal, and vertical retrace signal from the top.For writing and reading,
For example, writing is given priority. Figure 4 shows video R
While writing (WRITE) to AM (I>), reading from video RAM (n) (READ) is performed, and video RAM (I> and (IT) are alternately switched at a cycle T. When writing to the video RAM (TI), for example, with the video RAM (I) as a reference, the same contents as those written to the video RAM (I>) are repeatedly written, and the period T is For example, it may be synchronized with a vertical synchronization signal.Although the present embodiment shows an example of a graphic display device, the same can be applied to a character display device if a character generator is provided.

As described above, the video RAM control method according to the present invention provides a plurality of video RAMs in parallel, an input side switching circuit that sequentially writes to the plurality of video RAMs, and an input side switching circuit that sequentially writes to the plurality of video RAMs. and an output side switching circuit for sequentially reading video information from the plurality of video RAMs through the input side switching circuit, and sequentially reading video information sequentially written to the plurality of video RAMs through the output side switching circuit to the display device. Since it is characterized by continuous display, it is possible to reduce the number of write-in states, and it is possible to improve the display processing speed of the display device.

[Brief explanation of the drawing]

The drawings all show embodiments; Fig. 1 is a block diagram of the display device, Fig. 2 is a detailed block diagram showing the video RAM portion, Fig. 3 is a time chart for explaining the operating state, and Fig. 4 is a writing diagram. and is an explanatory diagram of a read state. (I), (II)...Video RAM 21...Input circuit 25...Input side switching circuit 27.
... Output side switching circuit Figure 1 Figure 2 Procedural amendment stamped) Kazuo Wakasugi, Commissioner of the Japan Patent Office (1985), 1. Indication of the case, 1989 Patent Application No. 35256 2. Invention Name: Video RAM Control Method 3, Relationship with the amended case Patent applicant address (residence) Address: 200 Ishida, Isehara City, Kanagawa Prefecture
5th floor, 5th floor, Toranomon Building, 1-2-3 Toranomon, Minato-ku, Tokyo, Column 6 for detailed explanation of the invention in the specification to be amended, Contents of the amendment (1) Page 1 of the specification, 2 lines from the bottom In the eyes, the word ``disbreath'' is corrected to ``display.'' (2) On the second page of the specification, on the second line from the top, on the fourth line from the top, and on the first line from the bottom, the words ``with writing'' should be amended to ``waiting for writing.'' (3) Page 5 of the specification, top! On the 18th line, the phrase ``holding for writing'' is corrected to ``waiting for writing.''that's all

Claims (1)

[Claims] A plurality of video RAMs are provided in parallel, an input side switching circuit for sequentially writing into the plurality of video RAMs, and an output side switching circuit for sequentially reading from the plurality of video RAMs, and the input side switching circuit is provided. A video RAM control method characterized in that video information sequentially written into the plurality of video RAMs via a circuit is sequentially read out via the output side switching circuit and displayed on a display device.