JPS60179045U - チツプキヤリア型素子 - Google Patents
チツプキヤリア型素子Info
- Publication number
- JPS60179045U JPS60179045U JP1984067193U JP6719384U JPS60179045U JP S60179045 U JPS60179045 U JP S60179045U JP 1984067193 U JP1984067193 U JP 1984067193U JP 6719384 U JP6719384 U JP 6719384U JP S60179045 U JPS60179045 U JP S60179045U
- Authority
- JP
- Japan
- Prior art keywords
- type element
- chip carrier
- carrier type
- abstract
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
Landscapes
- Wire Bonding (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
め要約のデータは記録されません。
Description
第1図aは従来のチップキャリア型素子の外形図、同図
すはその断面図、第2図aは本考案の一実施例の外形図
、同図すはその断面図、第3図は本考案のチップキャリ
アを3個積み重ねて使用した場合の一実施例である。 1.1′・・・ICチップ、2.2’・・・セラミック
パッケージ、3,3′・・・外部引き出し端子、4・・
・枠、5’、5’・・・キャップ、6・・・外部基板、
−7゜8.9.10・・・外部配線ライン、11,12
,13・・・本考案の一実施例によるチップキャリア型
素子、14,15,16・・・チップキャリア型素子内
部に搭載されているICチップ、17,18,19.2
0・・・外部引き出し端子。
すはその断面図、第2図aは本考案の一実施例の外形図
、同図すはその断面図、第3図は本考案のチップキャリ
アを3個積み重ねて使用した場合の一実施例である。 1.1′・・・ICチップ、2.2’・・・セラミック
パッケージ、3,3′・・・外部引き出し端子、4・・
・枠、5’、5’・・・キャップ、6・・・外部基板、
−7゜8.9.10・・・外部配線ライン、11,12
,13・・・本考案の一実施例によるチップキャリア型
素子、14,15,16・・・チップキャリア型素子内
部に搭載されているICチップ、17,18,19.2
0・・・外部引き出し端子。
Claims (1)
- 側面及び裏面に出ている外部引き出し端子をキャップ表
面にも具備したことを特徴とするチップキャリア型素子
。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1984067193U JPS60179045U (ja) | 1984-05-09 | 1984-05-09 | チツプキヤリア型素子 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1984067193U JPS60179045U (ja) | 1984-05-09 | 1984-05-09 | チツプキヤリア型素子 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60179045U true JPS60179045U (ja) | 1985-11-28 |
Family
ID=30600780
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1984067193U Pending JPS60179045U (ja) | 1984-05-09 | 1984-05-09 | チツプキヤリア型素子 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60179045U (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012033862A (ja) * | 2010-07-09 | 2012-02-16 | Denso Corp | 半導体装置 |
-
1984
- 1984-05-09 JP JP1984067193U patent/JPS60179045U/ja active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012033862A (ja) * | 2010-07-09 | 2012-02-16 | Denso Corp | 半導体装置 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS60179045U (ja) | チツプキヤリア型素子 | |
JPS60141129U (ja) | リ−ドレスチツプキヤリアの端子構造 | |
JPS60183439U (ja) | 集積回路 | |
JPS60181051U (ja) | リ−ドフレ−ムの構造 | |
JPS5999446U (ja) | チツプキヤリア | |
JPS60169860U (ja) | 混成集積回路 | |
JPS59145047U (ja) | 半導体装置 | |
JPS6146736U (ja) | 半導体チツプの取付構造 | |
JPS592146U (ja) | 電子部品パツケ−ジ | |
JPS6061740U (ja) | 混成集積回路装置 | |
JPS583042U (ja) | Icパツケ−ジ | |
JPS58159756U (ja) | 集積回路装置 | |
JPS6061742U (ja) | 集積回路装置 | |
JPS609226U (ja) | 半導体の実装用パツケ−ジ | |
JPS606229U (ja) | 半導体集積回路のパツケ−ジ | |
JPS59146952U (ja) | Icパツケ−ジ | |
JPS5954952U (ja) | 半導体装置 | |
JPS5829873U (ja) | 電子回路パッケ−ジ | |
JPS621982U (ja) | ||
JPS606231U (ja) | 混成集積回路の構造 | |
JPS605170U (ja) | 半導体素子用プリント基板 | |
JPS59121839U (ja) | 集積回路用パツケイジ | |
JPS59131158U (ja) | チツプキヤリヤ− | |
JPS58138343U (ja) | 半導体装置 | |
JPS59115640U (ja) | 電子部品 |