JPS60179045U - チツプキヤリア型素子 - Google Patents

チツプキヤリア型素子

Info

Publication number
JPS60179045U
JPS60179045U JP1984067193U JP6719384U JPS60179045U JP S60179045 U JPS60179045 U JP S60179045U JP 1984067193 U JP1984067193 U JP 1984067193U JP 6719384 U JP6719384 U JP 6719384U JP S60179045 U JPS60179045 U JP S60179045U
Authority
JP
Japan
Prior art keywords
type element
chip carrier
carrier type
abstract
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1984067193U
Other languages
English (en)
Inventor
明 岡本
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP1984067193U priority Critical patent/JPS60179045U/ja
Publication of JPS60179045U publication Critical patent/JPS60179045U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71

Landscapes

  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図ａは従来のチップキャリア型素子の外形図、同図
すはその断面図、第２図ａは本考案の一実施例の外形図
、同図すはその断面図、第３図は本考案のチップキャリ
アを３個積み重ねて使用した場合の一実施例である。 １．１′・・・ＩＣチップ、２．２’・・・セラミック
パッケージ、３，３′・・・外部引き出し端子、４・・
・枠、５’、５’・・・キャップ、６・・・外部基板、
−７゜８．９．１０・・・外部配線ライン、１１，１２
，１３・・・本考案の一実施例によるチップキャリア型
素子、１４，１５，１６・・・チップキャリア型素子内
部に搭載されているＩＣチップ、１７，１８，１９．２
０・・・外部引き出し端子。

Claims (1)

    【実用新案登録請求の範囲】
  1. 側面及び裏面に出ている外部引き出し端子をキャップ表
    面にも具備したことを特徴とするチップキャリア型素子
    。
JP1984067193U 1984-05-09 1984-05-09 チツプキヤリア型素子 Pending JPS60179045U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984067193U JPS60179045U (ja) 1984-05-09 1984-05-09 チツプキヤリア型素子

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984067193U JPS60179045U (ja) 1984-05-09 1984-05-09 チツプキヤリア型素子

Publications (1)

Publication Number Publication Date
JPS60179045U true JPS60179045U (ja) 1985-11-28

Family

ID=30600780

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984067193U Pending JPS60179045U (ja) 1984-05-09 1984-05-09 チツプキヤリア型素子

Country Status (1)

Country Link
JP (1) JPS60179045U (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012033862A (ja) * 2010-07-09 2012-02-16 Denso Corp 半導体装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012033862A (ja) * 2010-07-09 2012-02-16 Denso Corp 半導体装置

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