JPS60178074A - Electronic appliance - Google Patents

Abstract

PURPOSE:To enable a higher speed of the data processing with an effective use of a large-capacity RAM by setting the inside of the same RAM into a data convertible and writable area and a data non-convertible and non-writable area freely. CONSTITUTION:A RAM106 outputs a signal 107 indicating whether data conversion is performed to a data writing unit 103 from address information 102. Data from a bidirectional data bus 101 of a CPU is processed with the data writing unit 103 according to the signal 107 and written into a data conversion area as a buffer for a dot data of a RAM104 or a data non-conversion area to be used for a stack or flag of the CPU based on address information 102. The data written is outputted into an output equipment 999 such as ink-jet printer. This reduces the burden on the CPU to achieve a higher speed of data processing.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to electronic equipment capable of high-speed data processing.

[Prior art]

In recent years, L81 has been installed in various electronic devices, and they are becoming increasingly multifunctional. As the capacity of RAM increases, it has become common to use the contents of class 1a RAM divided into data buffers, stacks, and flag areas.

However, devices such as laser beam printers that develop textual information such as code data sent from a host computer as a bit image on an internal random access memory, and then read and output this information at high speeds. Due to processing requirements, it is considered effective to provide a data converting and writing device that shifts the bit image to the data buffer and overwrites it like the format child data of a table.

However, when the same RAM is used as a flag or a stack, the data conversion/writing device operates (and the contents of the flag or stack change, resulting in the electronic device not being able to perform the desired function).

〔the purpose〕

In view of the above points, it is the object of the present invention to eliminate the above-mentioned drawbacks and provide an electronic device that can appropriately process data at high speed.

〔Example〕

The present invention will be described in detail below with reference to the drawings.

FIG. 1 is an external view of a page printer which is a laser beam printer to which the present invention is applied. 1 is a printer body, for example a laser beam printer (LBP). 2 is an operation display section, and 6 is a power switch. Further, 4 is a paper discharge section. 5 is a transmission cable connected to the host. Note that the printer 1 may be a terminal in a network or a fax machine. As the interface, Centronics' interface method, R8252-C method, or a video signal may be input.

In addition, the operation display section 2 displays the ON LINEJ key to indicate that data is being transmitted from the host, the ERROR5KIPJ key to skip errors, and other self-diagnosis, manual feeding keys, and the ON LINEJ key to indicate that data is being transmitted instead of printing each page. It has keys etc. to extract the data up to that point. 6 is the ROofV1 cartridge, which stores 7 characters such as the alphabet and kanji characters, as well as programs.

FIG. 2 is a block diagram showing an embodiment to which the present invention is applied.
This figure shows an interface for receiving data transmitted from a host in the printer body 1 shown in the figure.

In Fig. 2, 101 is the CPU's bidirectional data bus consisting of 8 bits, and 1o2 is also the CPU's 16-bit data bus.
The address information of the lower 12 bits of the Pitt address bus,
106 is a data writing device, 104 is a random access memory (hereinafter referred to as AM), and the data 10 is
1 passes through the data writing device 106 and is written into the RAM 104 (128 Kbytes) as data 105.

Further, 106 is a RAM that directly relates to the present invention and sends a signal 107 indicating whether data is converted (1) or not (0) from the address information 102 to the data writing device 103. In addition, the AM 106 may also be a computing device such as a microprocessor.

Note that the data written in the ltAM 104 is output to various output devices 999 such as an inkjet printer, an LED printer, and an LBP printer.

FIG. 3 is a block diagram describing the same in more detail.

201 is a read-only memory (hereinafter referred to as ROM);
02 is a register, 206 is an AND gate, 204 is an RA
A register for latching the fixed data 108 from M104, 205 is an OFL gate, 206 is an adder, 2
07 is a main control device. 208 is shift information indicating whether to shift the booter (al bit) of the RAM 104. Also, 209 is a signal indicating whether to increase the address of the RAM 104 by one (1) or leave the address unchanged (0). .

Figure WJ4 is an example showing the address areas occupied by the 16-bit addresses of RAM 104 and RAM 106.

In FIG. 4, the area of the LAM 104 and the area of the RAM 106 have a one-to-one correspondence.
Of the areas M104, 601 is used as a buffer for dot data and data conversion is performed in area 5, and 302 is used for the CPU stack and flags, so it is an area where no data conversion is performed.

As shown in FIGS. 2 and 6, when the lower 12 bits are used as the address input 102 of each RAM, the RAM 10
6, "1" is written in the area 303 by a write signal (110 in FIG. 2) from the CPU (not shown), and "1" is written in the area 604.
In other words, when the area 601 in FIG. 0".

First, the case where area 601 is accessed will be described.

The data bus 101 receives a CP signal from a dot data generation circuit (not shown) based on code information from the host computer.
The data read by U is sent. In addition,
Data conversion and writing device 103#i data bus 101
The information from the ROM 201 is transferred to the ROM 201 as shown in FIG.
This is for writing the RAM read data 108 and the OR 205 to successive RAM addresses via the RAM address.

Next, data shifting will be explained.

In FIG. 6, information on how many bits of data 101 to shift is written in register 202 by the CPU in advance.

For example, when data 101 is shifted by 5 bits and written to 5 as shown in FIG. 5, the register 202 contains a binary value. For example, data 101 is “171als141s1g
ltloJ, data 208 is "101", signal 209
When is "0", the output 215 of ROM 201 is RAM
1) When it is 1elsJ and the signal 209 is "1", the output 215 is similarly specified to the next address of the AM 104, so 8 pits including the 5 bits overflowing from the previous address to the next address are output. , that is, "141slzl
iLo000 Outputs J. Now signal 107 is “1”
In this case, since we are considering the case of data conversion (shift), the AND gate 2o6 is open, so the contents of the data 208 are the same as the contents (shift information) of the register 202. The CPU outputs data 101 and address information 102 to be written to the RAM 104,
At the same time, a write command 210 is output to the main controller 207. Further, data 101 is shifted by ROM 201 and output as data 215.

On the other hand, data 108 is output from RAM 104 after a predetermined access time, and is latched into register 204 by latch signal 211 from main controller 207 .

The signal 209 is initially "0", indicating that 1 is not added to the address information, and the address information 109 is
Same as the content of address information 102〇Also, data 2
15 and data 212 are set to 0 by 5 rc gate 2o5
RAM write signal 2 from main controller 207
13, it is written into the RAM 104.

Note that the signal 214 is a signal that becomes "0" only when the CPU reads data from the RAM 104, and opens the three-state gate 216.

Next, the main controller 207 stores the data 101 in the ROM 201.
When shifted by , in order to write the data at the next address into the RAM 104, the signal 209 is changed from "0" to "1" in order to add 1 to the address information. As a result, the output 215 of the ROM 201 becomes the data of the part of the data 101 that extends to the next address (if 209 in FIG. 6 is 1), and the output 215 of the ROM 201 becomes
The output 109 of 06 is the value obtained by adding 1 to the address information 102. Similarly, from the main controller 207
A write signal 213 is output, and the overflowing data in the RAM 104 is written to the next address.

Next, the CPU is MU! Let's talk about the case where the ordinary person M104 accesses the area 602 in Figure 4.
The output 107 of the AM 106 in FIG. 2 is "0" indicating that data conversion is not performed. When the output 107 is "0", the AND gate 203 closes in FIG.
The value obtained by shifting 0 bits, that is, the data 101 and the output 215 are the same. Further, when the output 107 is "0", the register 204 is cleared, so the data 105 becomes the same as the company data 101 and the data 215.

Also, at this time, data 101 is not shifted, so RA
Since there is no data protruding to the next address of M, the main controller 207 outputs the write signal 213 only once.

Nice.

As described above (when the signal 107 is 1, the data 101 is converted and written to the RAM 104; when the signal 107 is 0, the data 101 is written to the RAM 104 without being converted).

〔effect〕

As described above, the present invention has provided an electronic device capable of high-speed data processing.

Furthermore, according to the present invention, the inside of the same RAM can be freely set as an area where data can be converted and written, and an area where data conversion cannot be written.
Not only can it be used effectively (but the CPU does not need to be aware of it, it has the effect of speeding up data processing and reducing the burden on the CPU.

[Brief explanation of the drawing]

FIG. 1 is an external view of a page printer to which the present invention is applied. FIG. 2 is a block diagram showing an embodiment of the invention. FIG. 6 is an explanatory block diagram of the data conversion and writing device. FIG. 4 is a diagram showing the address area. FIG. 5 is an explanatory diagram when data is shifted by 5 pits. FIG. 6 is an explanatory diagram of information stored in the ROM 201. 104...B A M 201..., ROM1060
・Data conversion and writing device applicant: Canon Co., Ltd. n@"I!-n+j@i deceased

Claims (1)

[Claims] Memory means for storing image information as a bit image;
Output means 1 for outputting the bit image stored in the memory means; Processing means for converting and/or writing data stored in the memory means; wherein the data is converted by the processing means in the memory means. An electronic device characterized by having a writable area and a writable area.