JPS58192139A - Image memory controlling device - Google Patents

Abstract

PURPOSE:To make the capacity of an image memory small, by providing the image memory having 1/n of capacity of one page and outputting data in n lots. CONSTITUTION:The capacity of the image memory 41 is 1/n of that of a display screen of one page. In outputting data to a low speed printer and the like, a CPU outputs the data via the image memory 41. The CPU writes the data 4 corresponding to one page to the image memory 41 in n lots. The data is outputted from the image memory 41 as required. The data 4 corresponding to one page is outputted in n lots. Thus, even if high-density image is requested, it is permissible to use the image memory 41 of small capacity.

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention The present invention relates to an image memory control device, in particular, for outputting one image or document to a printer or display, etc. /
The present invention relates to a control device for an image memo 1 which can be stored using an image memo 1 with a capacity of n.

BACKGROUND ART Office computer computers, word processors, personal computers, etc., which are equipped with printers and displays, have control devices that perform image processing. In other words, to output characters and symbols to a normal, non-impact printer or display, use OP.
Output to page memory by program such as U e1
A page's worth of characters, symbol codes, and control codes attached to them [Stored, read out in synchronization with the timing of the output side, and converted into the addresses of the corresponding characters and number r stored in the character generator. , thereby accessing the character generator, reading out the corresponding characters and symbols, converting them from parallel to serial, and sending them to the output device.

By the way, when outputting graphs and documents to a printer, etc., a method is used in which an image memory for one page is provided in the graphic controller, and an output pattern is written there and output. ing. In order to output clear sentences*, it is necessary to increase the resolution of the printer, etc., which inevitably increases the image memory.

For example, if you use all the printers of #8 disassembly/
One page of image memory in 4 format requires approximately 500 bytes total.

What about image memory? There is a way to use a small memory and process it using software, but while it is relatively easy to process only the Bunho process, the process becomes complicated when dealing with graphs and all Ryozogo images. .

OBJECT OF THE INVENTION An object of the present invention is to solve the above-mentioned drawbacks of the conventional technology by simply adding a complete circuit to the image memory.
ll Just one page of l/n, with no significant cost.
Along with the entire needle down, the software also provides image memory and a full load control system that can simplify the process.

In order to achieve the above object, the image memory of the present invention
In an image memory control device connected to all low-speed output devices such as dot printers, the control device controls the device's image memory of 1/η for one page and the image memory n times. A data selector that accesses all specified addresses, and a data selector that sequentially specifies values from 1 to n for the data selector.
The OPU has a latch 19+, and after reading one page of documents and graphics to the image memory every specified n times, the OPU reads one page of documents and graphics from the image memory. The entire feature is that the data sound is read out in units of n and outputted to the output device.

Examples of the invention
1. FIG. 1 and FIG. 2 are system diagrams and operation if diagrams showing all embodiments of the present invention.

Figure 1 shows a complete outline of the image processing system for printing or displaying graphs and text.
PU, 2 is a graphics controller, and 3 is an image memory. The C+PU 1 can load the entire document or graph into the image memory 3 via the graphics controller 2, and read it out from the image memory 3.

The graphics controller 2 includes a line generator, a character generator, a refresh memory, and the like.

FIG. 2 shows a case where the image memory 3 of the whistle 1 is replaced by the image memory 4 of the present invention. It is shown that 41 cm of memory of ]/n is mounted for the image memory 3 corresponding to one page, and the address space of one page memory is moved downward.

What is Figure 3? FIG. 2 is a diagram showing all the connections between the image memory controller 2 and the image memory δ of A, IB<.

In Fig. 5, the control circuit of image memory 3? For simplicity, only 11 chip select signals are used, and the read/write control signals for address and data lines are omitted.

5 is (3→8) line decoder multiplexer, 6
The memory element 1 of the 1-chip is shown, and b0~ of the memory element 6 is shown.
bq indicates a bit. In Figure 3, there are three lines Al? ~A0° All line decoder, multiplexer 5 defoods into 8 lines, and sends chip select signals O8° ~aS, V to each line. This allows selection of 54 chips (bits).

Figure 4 is an assembly diagram of an image memory controller and an image memory, showing all embodiments of the present invention.

In Figure 4, 8 chips of image memory correspond to 6 in Figure 3.
In order to have all the same functions as the 4-chip, a data latch 8 and an (8→l) data selector 7 are added in addition to the (3→8) line decoder b.

FIG. 6 shows all the functions of the data selector 7 and data latch 8 in FIG.

As shown in FIG. 5, the data selector 7 has the function of selecting all one of the eight chip select signals 10soNO8 and directing it to the mounted memory chip select signal line O8. One chip to choose from
It has the function to indicate all select ay@ lines.

In FIG. 4, data latch 8 is manually operated at the loss of J1. -DI is set to (000)1i-, data latch 8 latches all of this in synchronization with clock input OK, and data selector 7 *Eo4 child receives this value (00).
0) Send Th. Thereby, the data selector 7 causes the mounted memory to select the chip select signal O8O. At this time, the mounted memory 41 in Figure 2 is located at the top address of the image memory for one page.

The aPU 1 writes one page of documents and graphs to the image memory through the graphics controller 2. Naturally, it is only intended to be written to an address other than the mounted memory 41. Then, the CPU reads the address of the mounted memory ml through the entire graphic controller 2, and outputs it to an output device such as a printer.

Next, data latch 8 is set to (001)m-, mounted memory L1 is set to chip select) f+ (no. It writes to the image memory, reads the image memory at the address aSl from the mounted memory 41, and outputs it to the printer.

By repeating the above steps n times, the entire contents of the 9-minute image memory can be output to an output device such as a printer. It is very effective when applied to

The value of n is 8 in the embodiment, but may be set arbitrarily depending on the speed of the printer, the processing of writing/reading to the image memory, and the capacity of the memory chip. In addition, 1
Data set in latch 8 when 6≧n>8. -Ds becomes 4 bits.

EFFECTS OF THE INVENTION As explained above, according to the present invention, by adding all nine simple circuits, it is possible to
It is possible to reduce the cost of image memory completely because it can be implemented in memory of 1000 yen. Also, the software processing loaded into the image memory only needs to be repeated n times. , software processing can be simplified.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the image data processing device used in the present invention, and FIG. 2 is the operation I of the image memory of the present invention.
Ci, diagram, Figure 3 is a connection diagram of the image memory controller and image memory in Figure 1, ? /λ4 Figure is a connection diagram of the image memory controller and image memory showing all the actual examples of the present invention, and Figure 5 is the data/lambda of Figure @4.
FIG. 3 is a diagram showing the functions of a selector and a data latch. 1: opu, 2 nigera hook controller, 3
,Image,Memory,4: Image memory of the present invention,
41: Implemented memory, 5-line multiplexer, 6:
Memory chip, 7: Data selector, 8: Data
latch. Patent applicant: Ricoh Co., Ltd.

Claims (1)

[Claims] Low-speed output device such as dot printer Wtt - In the connected image data processing device, 1/n of one page
Wkt - an image memory with
A data selector that reads an address +S specified n times for the memory, and 1 for the data selector.
All data latch means sequentially specify the values of ~r1,
After writing one page of documents and graphs into the first image memory by going back n frames, read out the data by 1/n of each page from the image memory by going back n times, and output it. A patented image memory control device that outputs data to a device.