JPS6017552A - Data transfer control circuit - Google Patents

Abstract

PURPOSE:To perform efficient data transfer without conciousness of an opposite device and queuing by providing a data transfer control circuit capable of controlling independently input/output. CONSTITUTION:A first-in first-out (FIFO) memory 100 capable of independently controlling input/output, is provided on the input side. In addition, an FIFO300, capable of independently controlling input/output, is provided on the output side. A main memory 200 for temporary storage of transferred data is provided between the FIFO100 and FIFO300. A selector 700 selects a read address or write address from address counters 500 and 600, and supplies the address to the main memory 200. A write control 400 fetches data from the FIFO100 on the input side and controls writing into the main memory 200. A write control 900 reads data from the main memory 200, and controls writing into the FIFO300 on the output side.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data transfer control circuit for transferring data between devices.

Conventionally, this type of data transfer control circuit cannot independently control input/output, so while one device is sending data, the other device waits until the transfer is completed, or In many cases, one device notifies the other device that the transfer has been completed, which complicates the processing of both devices, and the processing capacity of the other device decreases due to the occurrence of backlogs.

The present invention has been made in view of these drawbacks, and by independently controlling input and output at the input and output sides during data transfer, it is possible to create a queue without being aware of the other device. An object of the present invention is to provide a data transfer control circuit that can perform efficient data transfer without causing problems.

In order to achieve the above object, the present invention provides the following features:
In the data transfer control circuit when performing data transfer, there is a first-in-first-out memory provided on the input side that can independently control input and output, a main memory that temporarily stores the transferred data, and an input memory provided on the output side. First-in-first-out memory that allows you to independently control output,
a write control for controlling writing of data from the input side first-in-first-out memory into the main memory; a write address counter for specifying a write address of the main memory; and a write address counter for specifying a read address of the main memory. A read address counter, a selector that switches between the output of the write address counter and the output of the read address counter under the control of the write control, and the value of the write address counter and the value of the read trace counter are compared. and a read control that controls reading out the contents of the main memory and writing them to the output side first-in-first-out memory. It is characterized by being configured so that it can be controlled independently.

Hereinafter, the present invention will be explained in more detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment to which the circuit of the present invention is applied.

In the figure, the circuit of the present invention includes a first-in-first-out memory (hereinafter abbreviated as FIFO) 100 provided on the input side and capable of independently controlling input and output, and a main memory for temporary storage of transfer data (hereinafter abbreviated as MEM). ) 200, a first-in-first-out memory (hereinafter abbreviated as FIFO) 300 that is provided on the output side and can independently control input and output, and data is taken out from the input side FIFO 0100 and sent to the MEM 200. Write control (hereinafter abbreviated as WCTL) that controls writing 4
00 and a write address counter (hereinafter abbreviated as WAC) 5 that specifies the write address of the ME M 200.
00 and a read address counter (hereinafter abbreviated as RAC) that specifies the read address of the MEM200.
) 600,! :, a selector (hereinafter abbreviated as SEL) 700 that selects a read address or a write address and supplies it to the MEM 200, and a comparison unit (hereinafter abbreviated as CMP) that compares the read address and the write address and detects a mismatch. ) 800, and a write control (hereinafter abbreviated as RCTL) 900 that controls reading data from the MEM 200 and inputting it to the output F'IFO 300.

The operation of the present invention configured as described above will be explained separately for the input side and the output side.

When write data is sent via the data line 101 and a write pulse is sent via the AT control line 102, the data is stored in the input side FIFO 100. FIF
0100 is one in which input and output can be controlled independently, and 1
It can store data of one word or more. FI
Writing to FOZoo can be done continuously, as described above, regardless of the output. F IF 0100 indicates that data has been written to WCT L via control line 103.
400 and outputs the data to MEM 200.

When the WCTL 400 learns that it wants to write F IF 0100 K data 1) K, it uses the write timing sent via the control line 401 to determine whether the WCTL 400 is interested in writing the F IF 0100 K data. , 5EL700
Control 1m 402 K J: Tsu? ' W A C5
Switch to the 00 side and send the MEM200K write signal to the control line 4.
03 Send by K.

The data from the address [FIFOloo indicated by the MEM 200iI'i and the WAC 500 is written by the write signal from the control line 403.

After a certain timing, WCTL400 turns off the switching signal of 5EL700 and the write signal of MEM200.
F, and sends a count up pulse to the WAC 500 via the control line 404 and a next data retrieval signal to FIFOloo.

This completes the storage of one data, and when the next data is available, the above operation is repeated and the data is stored in the MEM 200 from the user.

Next, the operation on the output side will be explained.

CM P800 always uses WAC500 and RA C60
If a mismatch occurs when comparing the values of 0, RCTL9
Notify 00 that there is data to be output.

When the RCT L 900 learns that there is data to be output, it checks via the control line 301 whether or not it is possible to write 1 into the FIFO 300 . This FIFO300 is
When the maximum value that can be stored is reached, a write inhibit signal is sent.

The RCT L 900 does nothing if writing is not possible, but if it is possible, it writes the control line 9 to the FIFO 300 according to the read timing sent via the control line 901.
A write signal is sent via 02.

On the other hand, SEL 700 always uses RA except when writing.
Since the read address is supplied to the MEM 200 after switching to the C600 side, the data at the address indicated by the RAC 600 is output from the MEM 200. F I F 0300 is M E M 20
Data from 0 is written by the write signal from RCT L 900.

RCT L 900 connects the control line 90 after a certain timing.
The write signal No. 2 is turned OFF and a count-up pulse is sent to the RAC600. My father, RCTL900,
If there is a mismatch in CMP 800, the above operation is repeated if writing to PIFO 300 is possible.

Note that the timings of the control line 401 and the control line 901 are set to have a phase difference so as not to cause conflict in reading and writing.

P I F O 300 connects data line 302 . city 1j kal
Data is output to the downstream device via line 303. When the downstream device finishes processing, it is instructed to retrieve the next data from the FIFO 300 via the control line 304, so the F
IF 0300 loads the next data. still,
The city U control line 303 indicates whether data is valid or invalid.

In the above explanation, transfer was performed in one direction, but in the case of transfer in both directions, it is sufficient to add one more circuit of the present invention in the opposite direction.

As explained above, the present invention has the effect of being able to perform efficient data transfer without being aware of the other party's device and without waiting. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. 100... Input side first in first out memory (FIFO) 200... Main memory (MEM) 300... Output side first in first out memory (FIFO) 400... Write control (WCTL) 500.
...Write address counter (WAC) 600...Read address counter (RAG) 700...Selector (SEL) 800...Comparison section (CMP)

Claims (1)

[Claims] When transferring data between devices, in addition to the data transfer control circuit, there is a first-in-first-out memory that is installed on the input side and can independently control input and output, and a main memory that temporarily stores the transferred data. a memory, a first-in-first-out memory provided on the output side and capable of independently controlling input/output, and a write control for controlling writing of data from the input-side first-in-first-out memory to the main memory; A write address counter that specifies a write address of the main memory, a read address counter that specifies a read address of the main memory, and an output of the write address counter and an output of the read address counter are controlled according to the control of the write control. A selector for switching, a comparison section for comparing the value of the write address counter and the value of the read address counter, and a read control for controlling the reading of the contents of the main memory and writing to the output side first-in-first-out memory. 8. A data transfer control circuit comprising: a data transfer control circuit configured to independently control input and output on an input side and an output side during data transfer.