JPS60173856A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve step coverage by a method wherein the whole surface is covered with the lower insulation layer after formation of the lower wiring layer, and the upper end surface is flattened by applying heat-resistant region; then, the whole surface is covered again with the lower insulation layer after control etching, and the upper layer wiring is formed thereon. CONSTITUTION:After an SiO2 film 12 is formed on the surface of a semiconductor substrate 11, the Al lower wiring layer 13 is formed. Next, a PSG is formed over the lower wiring layer 13 and the film 12 and made as the lower layer insulation film 14, and a heat-resistant regin layer 15 is applied over it. The upper layer insulation film 16 is formed over the flattened surface by control-etching the insulation film 14 and the layer 15. Further, a through hole penetrating through the upper and lower insulation films 14 and 16 is opened, and the upper wiring layer 17 is formed. This makes the step produced by the lower layer wiring to be flattened at the step of the formation of an interlayer insulation layer, resulting in the prevention of defective wiring such as the disconnection of the upper layer wiring.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming a wiring layer of a semiconductor device.

BACKGROUND OF THE INVENTION A conventional general wiring method for semiconductor devices such as ICs and the like will be explained with reference to FIG. For example, an aluminum alloy layer is deposited on a silicon semiconductor substrate 1 whose surface is insulated with a silicon dioxide (Sin, 2) film 2, and patterned to form lower layer wiring I and 3. Next, the entire surface is coated with P using the CVD method.
An SG (phosphosilicate glass) layer is formed to serve as an interlayer insulating film 4. After making necessary through holes in the interlayer insulating film 4, the aluminum alloy layer is again bonded to the entire surface and patterned to form the upper layer +Thi 5. In such a wiring method, the coverage of the upper wiring layer 5 is lowered over the severe unevenness of the surface caused by the lower wiring, i.e., the step at the shoulder of the lower wiring layer 3 or the part where the spacing between the lower wiring layers is narrow. (coverage) is not sufficient,
The wiring becomes partially thin, causing disconnection or melting due to current concentration.
It causes migration.

In order to prevent such wiring defects, a technique has been proposed in which the underlying surface of the upper wiring layer is flattened by coating the entire surface with resin after forming 180 layers. However, if the resin is simply applied, there is a risk that the aluminum alloy in the upper wiring layer will come into direct contact with the lower resin or with the resin in the through-holes and cause a chemical reaction. There is a risk of cracking or etching due to exposure to chemicals and gases during the process, so it is not suitable for practical use as it is.

OBJECTS OF THE INVENTION In view of the above-mentioned prior art, it is an object of the present invention to provide a multilayer wiring with good stamp coverage.

Structure of the Invention In order to achieve the above object, the present invention, after forming a lower wiring layer, first covers the entire surface with a lower insulating layer, and then applies a heat-resistant resin thereon to flatten the upper end surface. By spin-coding the resin, it can fill in the unevenness of the underlying surface and make the surface flat. Etching is then performed by controlling the etching rates of the resin and the underlying insulating layer to be substantially equal.

With controlled etching, the etched surface remains flat.

Etching is performed until at least the heat-resistant resin present above the lower wiring layer is exhausted. This is the upper and lower wiring le
This is to prevent the aluminum of the wiring from coming into contact with the resin in the through-hole when connecting through the through-hole. After the controlled etching, the entire surface is covered again with the lower insulating layer, and the resin is embedded in the upper and lower insulating layers, eliminating the risk of contamination and exposure to chemicals and gases in subsequent steps. Since the underlying surface is flat, the surface of the lower insulating layer is flat, and wiring defects such as disconnections in the upper layer wiring formed thereon are prevented.

Examples of the invention This will be explained with reference to FIGS. 2 to 7.

Referring to FIG. 2, after forming a CVD 5iQ2 film I2 on a semiconductor substrate 11 made of silicon or the like, an aluminum (1% Si alloy) lower wiring layer 13 is formed.

For example, the lower wiring layer has a thickness of approximately 1°0 μm and a width of 4 μm.
The interval between each wiring is 1.5 μm. In addition to aluminum silicon alloy, the wiring material may be an aluminum alloy such as aluminum copper, a multilayer material such as titanium tungsten-aluminum, or a material other than aluminum such as gold or tungsten. The spacing is also not limited to the above.

Referring to FIG. 3, the lower wiring layer 13 and Si02
PSG is formed on the entire surface of the film 12 by the CVD method to a thickness of about 0.7 μm to form the lower insulating film 14. As shown in the figure, interlayer insulating films such as CVD PSG, which have been commonly used in the past, have poor coverage at the shoulders of lower wiring layers and at narrow intervals between wiring layers, and the surface cannot be flattened. In addition,
It is desirable that the thickness of the lower layer insulating film 14 is less than half the distance between the lower layer wirings. In addition to the above, insulating materials include 5i02 by CVD method and 5in2 by sputtering method.
．． ,,5i02PS by PSG% bias sputtering method
G, SiN by plasma CVD method, 5iON%
etc. may be used.

Referring to FIG. 4, a heat-resistant resin layer 15 is applied over the entire surface of the lower insulating film 14. As shown in FIG. Examples of heat-resistant resins include PL.
Using O8 (Fujitsu's silicone resin product name),
Spin coded at 5000 rprn to a thickness of about 0.5 μm, heated at 1200C for 30 minutes, then at 300'C for 30 minutes.
Heat treat for a minute to harden.

Since the spin-coded resin has fluidity, it sinks into the recesses on the surface of the lower insulating film 14 for a long time, completely filling the space between the resin layer 15 and the lower insulating film 14, and forming a void there. Never. Furthermore, the surface of the spin-coded resin layer is flattened regardless of the unevenness of the underlying insulating film. This embedding resin is one that flattens the surface as a spin cord as described above, and in consideration of the subsequent process,
Any material may be used as long as it is fire resistant to heat of about 0C, such as silicone, polyimide, etc.
555, Devot Co., Ltd.), photosensitive polyimide, heat-resistant photoresist, or other resins.

Referring to FIG. 5, control etching is performed by making the etching rates of the lower insulating film 14 and the resin layer 15 substantially equal. In the above example, CF3 (130SCCM) x CHF, (70SCCM) is
It is sufficient to flow a mixed gas of CM) at a pressure of 0.3 Torr and a power supply of 600 W.

Etching is performed until there is no resin above the lower wiring layer 13, and in the above example, the etching is performed for about 2 to 3 minutes until the thickness of the lower insulation film 14 on the lower wiring layer 13 becomes about 2000 to 3000 Å. . By this controlled etching, the resin on the flat parts of the lower insulating film 14 will generally disappear (resin may remain on the flat parts except above the lower wiring), but the resin on the flat parts, i.e., on the non-flat parts, will disappear. , the shoulders of the steps, and the recesses in the areas where the wiring spacing is narrow will remain filled with resin. As a result, the lower insulating film 1
The resin fills the recesses on the surface of No. 4 to achieve a flattened surface. This is because the surface is flattened by the spin code and etching is performed by controlling the etching speed of the resin and the underlying insulating film to be approximately equal, so that the surface that appears after controlled etching also becomes flat. achieved. Control etching conditions are selected depending on the materials of the lower insulating layer and heat-resistant resin.

Referring to FIG. 6, an upper insulating film 16 is formed on the entire surface that has been planarized by controlled etching. The surface of this upper insulating film 16 is finished flat since the underlying layer is flat. The material for the upper insulating film 16 can be the same as that for the lower insulating film 15. Furthermore, the thickness of the upper insulating film 16 is not particularly limited.

! ′! Referring to Figure 7, the upper and lower insulating films 1 are
4. Drill a through hole passing through 16 and connect the upper wiring layer 17.
form. Thereafter, the semiconductor device is completed in the usual manner.

Effects of the Invention As is clear from the above explanation, in the semiconductor device manufactured by the method of the present invention, the steps based on the lower layer wiring are flattened and eliminated at the interlayer insulating layer formation stage, so wiring defects such as disconnections in the upper layer wiring occur. In addition, since the heat-resistant resin used for planarizing the interlayer insulating layer is embedded inside the same good insulating layer as in the past, various inconveniences due to the presence of the resin are also eliminated. In this way, a practical and good multilayer wiring is provided. Note that it is obvious that the present invention is also applicable to wiring of three or more layers.

[Brief explanation of drawings]

Figure 1 is a cross-sectional view of the wiring section according to the conventional method, Figures 2 to 7
The figures are cross-sectional views of the wiring portion in the order of steps for detailed explanation of the present invention. 11... Semiconductor substrate, 12... 5t02 film, 13.
... Patent applicant below Fujitsu Ltd. Patent attorney Kazuyuki Nishidate Patent attorney Yukio Uchida 1. Indication of the case 1982 Patent Application No. 021835 2. Name of the invention Method for manufacturing a semiconductor device 3. Person making the amendment Relationship to the case Patent applicant name (522) Fujitsu Ltd. 4, Agent 5 Amendment Part 6 of the "Claims" and "Detailed Description of the Invention" of the subject specification, contents of amendment (1) The claims column is amended as shown in the attached sheet. (2) (7) Insert "And, when the lower wiring layer is exposed, four parts of the lower wiring layer are filled with resin" between the last line of page 6 and the first line of page 4 of the specification. do. (a) Insert "at least at the position where a through hole is to be formed" between "ha" and "lower layer" in the first line of page 4. (ii) Insert ``at least the position where a through hole should be formed'' between ``ha'' and ``lower layer'' on the 4th line of page 7. Z. List of amendments made by the relevant party Claims 1 2, Claim Uf1 1. A step of forming a predetermined pattern on a lower wiring layer on a substrate, and a lower layer insulation on the lower wiring layer and the substrate. a step of forming a layer; a step of filling four parts of the layer; a step of forming an upper insulating layer on the lower insulating layer and the remaining resin; and a step of forming an upper wiring layer on the upper insulating layer. A method of manufacturing a semiconductor device, comprising:

Claims (1)

[Claims] A lower wiring layer having a predetermined pattern is formed on the substrate, a lower insulation layer is formed on the lower wiring layer and the substrate, a heat-resistant resin is applied on the lower insulation layer, and the heat-resistant resin and the lower insulation layer are coated on the lower insulation layer. Controlly etching the layer to remove at least the heat-resistant resin present above the lower insulating layer 1. Forming an upper insulating layer on the entire surface of the lower insulating layer and the remaining heat-resistant resin; 1. A method for manufacturing a semiconductor device, comprising the step of forming an upper wiring layer thereon.