JPS60171781A - Method of producing low dielectric constant multilayer board - Google Patents

Method of producing low dielectric constant multilayer board

Info

Publication number
JPS60171781A
JPS60171781A JP2901584A JP2901584A JPS60171781A JP S60171781 A JPS60171781 A JP S60171781A JP 2901584 A JP2901584 A JP 2901584A JP 2901584 A JP2901584 A JP 2901584A JP S60171781 A JPS60171781 A JP S60171781A
Authority
JP
Japan
Prior art keywords
dielectric constant
low dielectric
substrate
glass
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2901584A
Other languages
Japanese (ja)
Inventor
和明 栗原
丹羽 紘一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2901584A priority Critical patent/JPS60171781A/en
Publication of JPS60171781A publication Critical patent/JPS60171781A/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 (a)発明の技術分11’ 本発明は低誘電率の誘電材料を用いて形成される多層配
線基板の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION (a) Technical Part 11' of the Invention The present invention relates to a method for manufacturing a multilayer wiring board formed using a dielectric material with a low dielectric constant.

(b)技術の背景 高速化を実現する方法として、使用する電子回路素子の
小型化と大容量化とが強力に進められている。
(b) Background of the Technology As a method for achieving higher speeds, efforts are being made to make the electronic circuit elements used smaller and larger in capacity.

ここで代表、的な回路素子はLS、1などの半導体素子
であって、単位素子の小型化による集積度の増大が進ん
でいる。
Here, typical circuit elements are semiconductor elements such as LS, 1, etc., and the degree of integration is increasing due to miniaturization of unit elements.

この場合半導体素子はセラミックなどの耐熱性基板に装
着され、従来の実装法による場合はハーメチックシール
外装が施されて半導体装置が形成され、これをプリント
配線基板に装着されている。
In this case, the semiconductor element is mounted on a heat-resistant substrate such as ceramic, and in the case of a conventional mounting method, a hermetic seal is applied to form a semiconductor device, which is mounted on a printed wiring board.

また今後の実装法としてはチップ形状の半導体素子をセ
ラミックなどの耐熱性絶縁基板に直接に装着する方法が
採られようとしている。
Furthermore, as a mounting method in the future, a method of directly mounting a chip-shaped semiconductor element onto a heat-resistant insulating substrate such as a ceramic substrate is likely to be adopted.

ここでLSIや更に集積度を一段と増加したVLSIな
どの半導体素子を耐熱性絶縁基板に装着するに当たって
は端子数が多いので必然的に多層配線基板の使用が必要
になる。
Here, when mounting a semiconductor element such as an LSI or a VLSI with a higher degree of integration onto a heat-resistant insulating substrate, it is necessary to use a multilayer wiring board because the number of terminals is large.

本発明はかかる目的に使用される多層基板の製造方法に
ついてのものである。
The present invention relates to a method for manufacturing a multilayer substrate used for such purpose.

(C)従来技術と問題点 従来半導体素子を装着する多層配線基板としてはアルミ
ナを成分とするセラミックが用いられており、導体金属
としてはモリブデン・マンガン(Mo −Mn )合金
やタングステン・マンガン(W・Mn)合金などの高融
点金属が用いられている。
(C) Conventional technology and problems Conventionally, ceramics containing alumina have been used as multilayer wiring boards on which semiconductor devices are mounted, and conductive metals such as molybdenum-manganese (Mo-Mn) alloys and tungsten-manganese (W) have been used as conductor metals.・High melting point metals such as Mn) alloys are used.

この理由はアルミナ(αA12.03)の焼結温度が十
数百度と極めて高く、金(Au )や銅(Cu)など一
般に使用される導体金属の融点を越えていることによる
The reason for this is that the sintering temperature of alumina (αA 12.03) is extremely high at several hundred degrees, which exceeds the melting point of commonly used conductive metals such as gold (Au) and copper (Cu).

ここで電算機に使用される半導体素子のように演算の高
速化が必要な用途については従来のような多層基板の構
成は問題があり、基板材料の低誘電率化と導体パターン
の低抵抗化が必要となる。
For applications that require high-speed calculations, such as semiconductor elements used in computers, the conventional multilayer board structure has problems, and it is necessary to lower the dielectric constant of the board material and lower the resistance of the conductor pattern. Is required.

すなわち多層基板の配線パターン間には静電容量が存在
するが、この容量値は対向して存在する配線パターンの
面積に比例すると共に距離に反比例する。
In other words, capacitance exists between the wiring patterns of the multilayer board, and this capacitance value is proportional to the area of the opposing wiring patterns and inversely proportional to the distance.

そのため多層配線基板の層数が増し、単位の層厚が減少
するに従って配線バクーン間の静電容量が増して漏話量
がふえ信号の高速伝播が困難となる。
Therefore, as the number of layers of the multilayer wiring board increases and the thickness of each layer decreases, the capacitance between the wiring backs increases, the amount of crosstalk increases, and high-speed propagation of signals becomes difficult.

また半導体素子の集積度の増加に対応して導体パターン
幅の減少が必要であり、約100μmの導体パターンの
実用化が必要となるが、これを実現するためには従来の
導体材料よりも遥かに低抵抗の金属を使用する必要があ
る。
Furthermore, in response to the increase in the degree of integration of semiconductor devices, it is necessary to reduce the conductor pattern width, and it is necessary to commercialize conductor patterns of about 100 μm, but in order to realize this, it is necessary to reduce the width of conductor patterns, which is much more difficult than conventional conductor materials. It is necessary to use metals with low resistance.

これらの問題を解決するためアルミナを分散させたガラ
ス基板、結晶化ガラス基板などについて実用化が進めら
れている。
In order to solve these problems, practical use of glass substrates, crystallized glass substrates, etc. in which alumina is dispersed is underway.

然しアルミナを添加した硼珪酸ガラスと結晶化ガラスに
ついては焼成温度が低(AuやCuが使用できるが誘電
率は5乃至8と以前として高く、更に少ない誘電率を示
す基板の実用化が望まれている。
However, for borosilicate glass and crystallized glass with alumina added, the firing temperature is low (Au and Cu can be used, but the dielectric constant is still high at 5 to 8, and it is desired to put a substrate with an even lower dielectric constant into practical use. ing.

(d)発明の目的 本発明の目的は低誘電率の絶縁材料を用いて基板を形成
すると共に低抵抗の導体材料を用いLSIやVLS I
などの半導体素子を装着するのに適した多層配線基板の
製造方法を提供するにある。
(d) Purpose of the Invention The purpose of the present invention is to form a substrate using an insulating material with a low dielectric constant, and to form an LSI or VLSI using a conductive material with a low resistance.
It is an object of the present invention to provide a method for manufacturing a multilayer wiring board suitable for mounting semiconductor elements such as the above.

(e)発明の構成 本発明の目的は抵抗率の低い導体金属を用いて配線パタ
ーンを形成するとともに低誘電率の耐熱材料を用いて構
成される多層配線基板において、構成容積比率が10乃
至70%の石英ガラスと低誘電率のガラスとの混合物を
主構成材料としてグリンシートを形成し、該シートを積
層して加圧したのち1100℃以下の温度で焼成するこ
とにより石英ガラスが均一に分散したガラス質の多層配
線基板を作ることを特徴とする低誘電率多層基板の製造
方法により実現することができる。
(e) Structure of the Invention The object of the present invention is to provide a multilayer wiring board in which a wiring pattern is formed using a conductive metal with a low resistivity and a heat-resistant material with a low dielectric constant, the volume ratio of which is 10 to 70. % of quartz glass and glass with a low dielectric constant as the main constituent material, the sheets are stacked and pressed, and then fired at a temperature of 1100°C or less to uniformly disperse the silica glass. This can be realized by a method for manufacturing a low dielectric constant multilayer board, which is characterized by manufacturing a glassy multilayer wiring board.

(f)発明の実施例 本発明は石英ガラスが誘電率が3.8と少なく、熱膨張
係数や絶縁抵抗値など電気的および機械的特性が優れて
いるのを利用し、これを例えば誘電率が4.6と小さい
硼珪酸ガラスのような低誘電率ガラスと混合して焼成し
、基板を作ることにより焼成温度を1ioo℃以下にま
で下げることが可能となり、これによりAuやCuのよ
うに融点がt io。
(f) Embodiments of the Invention The present invention takes advantage of the fact that quartz glass has a low dielectric constant of 3.8 and has excellent electrical and mechanical properties such as a coefficient of thermal expansion and an insulation resistance value. By mixing and firing a low dielectric constant glass such as borosilicate glass with a small dielectric constant of 4.6 to create a substrate, it is possible to lower the firing temperature to below 1ioo°C. The melting point is tio.

℃以下の導体金属の使用を可能とし、これにより上記の
目的を達成するものである。
This makes it possible to use conductive metals with temperatures below 0.degree. C., thereby achieving the above object.

以下本発明を実施例について説明する。The present invention will be described below with reference to Examples.

表は実施例のガラスを作るに用いた原料組成である。The table shows the raw material compositions used to make the glasses of Examples.

表 、ここでバインダとして本実施例ではアクリル樹脂をま
た有機溶剤としてはメチルエチルケトンを使用した。
In this example, acrylic resin was used as the binder, and methyl ethyl ketone was used as the organic solvent.

これらの材料は良く混合したのち混練してスラリー状と
し、ドクタブレード法により厚さが300μmのグリン
シートを成形した。
These materials were thoroughly mixed and then kneaded to form a slurry, which was then molded into a green sheet with a thickness of 300 μm using a doctor blade method.

次にこのシートを1501■角に打抜くと共に必要とす
る位置にバイアボールを作り、また銅ペーストをスクリ
ーン印刷して100 μm幅の配線パターンを形成した
Next, this sheet was punched out into 1501 square centimeters, via balls were formed at the required positions, and copper paste was screen printed to form a wiring pattern with a width of 100 μm.

このようにして作った10枚のグリンシートは正確に位
置合わせして積層したのち20MPaの圧力で30分加
圧して一体化し、次に窒素気流中で1000℃の温度で
30分間に互って焼成して多層基板を得た。
The 10 green sheets made in this way were laminated with precise alignment, then pressurized at 20 MPa for 30 minutes to integrate them, and then stacked on top of each other for 30 minutes at a temperature of 1000°C in a nitrogen stream. A multilayer substrate was obtained by firing.

このようにして得られた基板の誘電率は4.0であって
石英ガラスの3.8と近似しており、一方配線パターン
の面積抵抗は1.1+mΩと低い。
The dielectric constant of the substrate thus obtained is 4.0, which is close to 3.8 of quartz glass, while the sheet resistance of the wiring pattern is as low as 1.1+mΩ.

図は実施例と同じ成分組成のものについて石英ガラスと
硼珪酸ガラスの構成比を変えて作った基板の密度と誘電
率の関係を示すもので夷る。
The figure shows the relationship between density and dielectric constant of substrates made with the same composition as in the example but with different composition ratios of quartz glass and borosilicate glass.

すなわち石英の含有量が増すに従って基板の誘電率は石
英ガラスの3.8に近づくが一方基板の密度は石英ガラ
スの含有量が70%を越えると急激に低下して多孔質に
なる。
That is, as the quartz content increases, the dielectric constant of the substrate approaches 3.8 of quartz glass, but on the other hand, when the quartz glass content exceeds 70%, the density of the substrate decreases rapidly and becomes porous.

なお基板の製造は石英ガラスの含有量が少ないほうが作
りやすい。それゆえ用途に応じて石英ガラスの含有量を
10乃至70%の範囲に選択して多層基板を作ればよい
Note that it is easier to manufacture the substrate if the content of quartz glass is small. Therefore, the multilayer substrate may be manufactured by selecting the silica glass content in the range of 10 to 70% depending on the application.

(g)発明の効果 本発明は多層配線基板に装着される半導体素子の集積度
の向上に伴い一構成層数が増し、また層厚が薄くなる結
果として低誘電率基板で且つ抵抗率の低い配線パターン
を特徴とする請求に応えるためになされたもので、本発
明の実施により誘電率の小さい基板の実用化が可能にな
る。
(g) Effects of the Invention The present invention provides a substrate with a low dielectric constant and low resistivity as a result of an increase in the number of constituent layers and thinner layer thicknesses as the degree of integration of semiconductor elements mounted on a multilayer wiring board increases. This was made in response to requests for features featuring wiring patterns, and implementation of the present invention makes it possible to put a substrate with a low dielectric constant into practical use.

【図面の簡単な説明】[Brief explanation of drawings]

図は本発明の実施例について石英含有量に対する誘電率
と密度の関係を示す図である。
The figure is a diagram showing the relationship between dielectric constant and density with respect to quartz content in an example of the present invention.

Claims (1)

【特許請求の範囲】[Claims] 抵抗率の低い導体金属を用いて配線パターンを形成する
とともに低誘電率の耐熱材料を用いて構成される多層配
線基板において、構成容積比率が10乃至70%の石英
ガラスと低誘電率のガラスとの混合物を主構成材料とし
てグリンシートを形成し、該シートを積層して加圧した
のち1100℃以下の温度で焼成することにより石英ガ
ラスが均一に分散したガラス質の多層配線基板を作るこ
とを特徴とする低誘電率多層基板の製造方法。
In a multilayer wiring board that uses a conductive metal with low resistivity to form a wiring pattern and uses a heat-resistant material with a low dielectric constant, silica glass with a constituent volume ratio of 10 to 70% and glass with a low dielectric constant are used. A glassy multilayer wiring board in which silica glass is uniformly dispersed is produced by forming a green sheet using a mixture of the above as the main constituent material, laminating the sheets, applying pressure, and then firing at a temperature of 1100°C or less. A method for manufacturing a low dielectric constant multilayer substrate.
JP2901584A 1984-02-17 1984-02-17 Method of producing low dielectric constant multilayer board Pending JPS60171781A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2901584A JPS60171781A (en) 1984-02-17 1984-02-17 Method of producing low dielectric constant multilayer board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2901584A JPS60171781A (en) 1984-02-17 1984-02-17 Method of producing low dielectric constant multilayer board

Publications (1)

Publication Number Publication Date
JPS60171781A true JPS60171781A (en) 1985-09-05

Family

ID=12264582

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2901584A Pending JPS60171781A (en) 1984-02-17 1984-02-17 Method of producing low dielectric constant multilayer board

Country Status (1)

Country Link
JP (1) JPS60171781A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6435990A (en) * 1987-07-30 1989-02-07 Nec Corp Multilayered ceramic wiring board
JPH0832238A (en) * 1994-05-13 1996-02-02 Nec Corp Multilayer wiring board, its production and production of sintered silica used for it
JPH08116177A (en) * 1994-10-13 1996-05-07 Nec Corp Multilayer wiring board, its manufacture, and manufacture of silica sintered body used for the board

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6435990A (en) * 1987-07-30 1989-02-07 Nec Corp Multilayered ceramic wiring board
JPH0832238A (en) * 1994-05-13 1996-02-02 Nec Corp Multilayer wiring board, its production and production of sintered silica used for it
JPH08116177A (en) * 1994-10-13 1996-05-07 Nec Corp Multilayer wiring board, its manufacture, and manufacture of silica sintered body used for the board

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