JPH088416B2 - Method for manufacturing ceramic multilayer circuit board - Google Patents
Method for manufacturing ceramic multilayer circuit boardInfo
- Publication number
- JPH088416B2 JPH088416B2 JP63269766A JP26976688A JPH088416B2 JP H088416 B2 JPH088416 B2 JP H088416B2 JP 63269766 A JP63269766 A JP 63269766A JP 26976688 A JP26976688 A JP 26976688A JP H088416 B2 JPH088416 B2 JP H088416B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- void
- forming
- ceramic
- multilayer circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明はLSI素子を実装するためのセラミック回路基
板の製造方法に関する。The present invention relates to a method of manufacturing a ceramic circuit board for mounting an LSI device.
（従来の技術） 従来ICやLSI等の半導体素子はガラスエポキシ等のプ
リント回路基板あるいはアルミナセラミック基板に実装
されていたが、半導体素子の高集積化・微細化・高速化
に伴い実装用基板に対して高密度微細配線化・高速伝送
化・高周波数化・高熱放散化の要求が増えてきた。アル
ミナ基板は1500℃以上の高温で焼結しなければならない
ため、同時焼成される配線導体材料としては比較的電気
抵抗の高いW,Mo等の高融点金属しか利用できない。した
がって、パルス信号の伝送損失を考慮に入れた場合、配
線パターンの微細化には限界が生じてしまう。一方プリ
ント回路基板においてはパターンの微細化は困難であ
り、更に積層後、スルーホールをドリルにより形成し、
メッキを施して電気的に接続させるため高密度化は限界
にあった。そこで開発されたのが低温焼結多層セラミッ
ク基板で、1000℃以下で焼結する絶縁材料を用いている
ため、配線導体材料として電気抵抗の低いAu、Ag−Pd、
Cu等の低融点金属を用いることができる。プロセス的に
はグリーンシート積層技術を用いているため100μｍ以
下のグリーンシートを形成しビアホールを開けることに
より極めて高密度に回路配線を基板内に実現することが
できる。(Prior Art) Conventionally, semiconductor elements such as ICs and LSIs were mounted on a printed circuit board such as glass epoxy or an alumina ceramic substrate. However, as semiconductor elements become highly integrated, miniaturized, and speeded up, they are now mounted on mounting boards. On the other hand, there is an increasing demand for high-density fine wiring, high-speed transmission, high frequency, and high heat dissipation. Since the alumina substrate has to be sintered at a high temperature of 1500 ° C. or higher, only high melting point metals such as W and Mo having relatively high electric resistance can be used as the wiring conductor material to be co-fired. Therefore, if the transmission loss of the pulse signal is taken into consideration, there is a limit to the miniaturization of the wiring pattern. On the other hand, in printed circuit boards, it is difficult to miniaturize patterns, and after stacking, through holes are formed by drilling,
There was a limit to high density because plating was performed and electrical connection was made. Therefore, a low-temperature sintered multilayer ceramic substrate was developed. Since it uses an insulating material that sinters at 1000 ° C or less, Au, Ag-Pd, and
A low melting point metal such as Cu can be used. Since the green sheet stacking technology is used in terms of process, circuit wiring can be realized in the substrate at extremely high density by forming a green sheet of 100 μm or less and opening a via hole.
しかし、これらのセラミック配線基板においても、誘
電率の低減において、その絶縁材料本来の誘電率しか望
むことができず、このレベルでは信号の高速化を向上さ
せること問題がある。However, even in these ceramic wiring boards, only the original dielectric constant of the insulating material can be desired in the reduction of the dielectric constant, and at this level, there is a problem that the speeding up of signals is improved.
（発明が解決しようとする課題） このように、高速伝送化に対しては、パルス信号の伝
播遅延時間が基板材料の誘電率の平方根に比例するた
め、基板材料の低誘電率化が不可欠となる。(Problems to be Solved by the Invention) As described above, for high-speed transmission, it is essential to reduce the dielectric constant of the substrate material because the propagation delay time of the pulse signal is proportional to the square root of the dielectric constant of the substrate material. Become.
ところが、アルミナ基板（誘電率＝約10）はもちろん
最近開発されている低温焼結セラミック基板もアルミナ
に比べれば低いものの、十分な低誘電率化は図られてお
らず高速化に対してまで改善する必要がある。一方、プ
リント基板にはスルーホールメッキ性・加工性・多層化
接着・高温での熱変形が大きい等の問題があり、高密度
化には限界がある。そこでセラミック基板の誘電率を下
げる方法としては、基板を構成している絶縁材料を低誘
電率化させることが考えられる。しかし、これらのセラ
ミック配線基板においても、その絶縁材料本来の誘電率
までしか望むことができず、低誘電率化については限界
にある。一方、絶縁層を形成しているセラミック部に空
隙を存在させることにより大幅に誘電率を下げることが
可能であるが、空隙が外気と通じていると、吸水が発生
し絶縁特性並びに耐湿負荷特性に支障を来してしまう。
そこで、いかにして焼結体内に孤立空隙を生成させるか
が鍵となる。したがって、本発明の目的はこのような従
来の課題を解決することにより、低い誘電率を有し、た
とえば800℃以上1000℃以下の低温で焼成でき絶縁特性
や耐水性等信頼性の優れた高密度化が可能な孤立空隙を
有するセラミック多層回路基板を提供することにある。
さらに、電気抵抗の低い導体材料を施すことにより、パ
ルス信号の高速伝送化に極めて有利な高密度微細配線基
板を提供することもできる。However, not only alumina substrates (dielectric constant = about 10) but also low temperature sintered ceramic substrates, which have been recently developed, are lower than alumina, but they have not been sufficiently reduced in dielectric constant and improved to higher speed. There is a need to. On the other hand, printed circuit boards have problems such as through-hole plating, workability, multi-layered adhesion, and large thermal deformation at high temperatures, and there is a limit to high density. Therefore, as a method of lowering the dielectric constant of the ceramic substrate, it is conceivable to lower the dielectric constant of the insulating material forming the substrate. However, even with these ceramic wiring boards, only the original dielectric constant of the insulating material can be desired, and there is a limit to lowering the dielectric constant. On the other hand, the presence of voids in the ceramic part forming the insulating layer can significantly reduce the dielectric constant, but if the voids communicate with the outside air, water will be absorbed and the insulation and moisture resistance characteristics will increase. Will be a problem.
Therefore, the key is how to create isolated voids in the sintered body. Therefore, the object of the present invention is to solve such a conventional problem, to have a low dielectric constant, for example, it can be fired at a low temperature of 800 ℃ or more and 1000 ℃ or less, and excellent in reliability such as insulation characteristics and water resistance It is an object of the present invention to provide a ceramic multilayer circuit board having an isolated void that can be densified.
Furthermore, by applying a conductor material having a low electric resistance, it is possible to provide a high-density fine wiring board which is extremely advantageous for high-speed transmission of pulse signals.
（課題を解決するための手段） 本発明のセラミック多層回路基板は、ガラスを含んだ
セラミック混合粉末と焼成の際分解し完全に飛散する高
分子の空隙形成材料をバインダと溶剤により混合しスラ
リーを作製する工程と、均一に分散されたスラリーをグ
リーンシート化しビアホール形成し導体を埋め込むとと
もに配線を印刷する工程と、積層、熱プレス後、酸化性
雰囲気中で高分子空隙形成材料を分解せしめ完全に飛散
し空隙を形成させる工程と酸化性雰囲気中で750℃以上
で焼成し、均一な１μｍ〜30μｍの範囲にある孤立空隙
を５〜40容量パーセント含んだ構造を有するものが得ら
れる。(Means for Solving the Problems) The ceramic multilayer circuit board of the present invention is prepared by mixing a ceramic mixed powder containing glass and a polymer void-forming material that decomposes and completely scatters during firing with a binder to form a slurry. The process of manufacturing, the process of forming uniformly dispersed slurry into a green sheet, forming via holes, embedding the conductor and printing the wiring, and the process of stacking and hot pressing, and then decomposing the polymer void-forming material in an oxidizing atmosphere and completely A process of scattering and forming voids and firing at 750 ° C. or higher in an oxidizing atmosphere to obtain a uniform structure having 5 to 40 volume percent of isolated voids in the range of 1 to 30 μm are obtained.
なお、孤立空隙が１μｍ未満だと孤立空隙が均一に分
散しない。また30μｍを越えると孤立空隙が形成できな
くなる。一方空隙率が５％未満だと低誘電率効果が顕著
でなく、40％を越えると強度の低下をまねき基板として
の特性が得られなくなる。If the isolated voids are less than 1 μm, the isolated voids will not be dispersed uniformly. If it exceeds 30 μm, isolated voids cannot be formed. On the other hand, when the porosity is less than 5%, the low dielectric constant effect is not remarkable, and when it exceeds 40%, the strength is lowered and the characteristics as a substrate cannot be obtained.
（実施例） 以下に本発明を実施例により更に具体的に説明する
が、本発明はその要旨を超えない限り、以下の実施例に
限定されるものではない。(Examples) Hereinafter, the present invention will be described in more detail with reference to Examples, but the present invention is not limited to the following Examples as long as the gist thereof is not exceeded.
絶縁材料として石英ガラスとホウケイ酸系ガラスおよ
びα−石英の複合材料を用い高分子空隙形成材料として
ポリスチレンを適用した場合について述べる。ポリスチ
レンは球状の１μｍ〜40μｍの範囲にある粒子を５〜40
容量パーセントの範囲の所定の比率になるように混合
し、ポリビニルブチラールをエチルセルソルブを主成分
とする溶剤で溶かした液と均一に混ぜ合わせた粘度3000
〜10000cpになるスラリーを作製する。これをスリップ
キャスティング成膜法により50μｍ〜200μｍの厚みに
なるようにグリーンシート化する。このグリーンシート
を所定の位置に150μｍ〜300μｍのビアホールを形成
し、スクリーン厚膜印刷法によりAg−Pd導体で配線パタ
ーンを印刷するとともに層間の導通をもたせるためにビ
アホール導体を埋め込む。それぞれパターンを形成した
シートを積層し110℃、150〜250kg/cm2で熱プレスする
ことにより生積層体を得る。この生積層体を電気炉中で
酸化性雰囲気下500℃の条件で空隙形成材を完全に除去
せしめるとともにバインダーも除去する。その後750〜8
50℃の範囲で酸化性雰囲気中でガラスの軟化反応を十分
に進行させることにより孤立空隙を形成し、更に900℃
で焼結を完了させる。こうして得られたセラミック多層
回路基板の断面模式図を第１図に示す。またセラミク基
板の誘電率と空隙形成材料のポリスチレン含有量の関係
を第２図に示す。第１図で１はセラミック焼結体、２は
ビアホール、３は回路導体、４は孤立空隙である。図か
らわかるように極めて誘電率が下げられ高速化に対して
有利である。他の特性については、絶縁抵抗は1013Ω以
上、誘電損失は0.2％以上と良好であった。ここで用い
たポリスチレン以外にも空隙形成材料としてポリエステ
ル、ポリエチレン、ポリメチルメタクリレート、フッ素
樹脂などを用いても同様の効果が得られた。A case where a composite material of quartz glass, borosilicate glass and α-quartz is used as an insulating material and polystyrene is applied as a polymer void forming material will be described. Polystyrene has 5-40 spherical particles in the range of 1 μm-40 μm
Viscosity 3000, which is obtained by mixing and mixing polyvinyl butyral with a solvent containing ethyl cellosolve as a main component to obtain a predetermined ratio within the range of volume percent.
Make a slurry of ~ 10000 cp. This is formed into a green sheet by a slip casting film forming method so as to have a thickness of 50 μm to 200 μm. A via hole of 150 μm to 300 μm is formed at a predetermined position on this green sheet, and a wiring pattern is printed by an Ag-Pd conductor by a screen thick film printing method, and a via hole conductor is embedded in order to provide conduction between layers. Sheets on which each pattern is formed are laminated and hot pressed at 110 ° C. and 150 to 250 kg / cm 2 to obtain a green laminate. The green laminate is completely removed of the void-forming material and the binder under the condition of 500 ° C. in an electric furnace in an oxidizing atmosphere. Then 750-8
The isolated voids are formed by fully advancing the softening reaction of the glass in an oxidizing atmosphere in the range of 50 ° C, and then 900 ° C.
To complete the sintering. A schematic sectional view of the ceramic multilayer circuit board thus obtained is shown in FIG. The relationship between the dielectric constant of the ceramic substrate and the polystyrene content of the void forming material is shown in FIG. In FIG. 1, 1 is a ceramic sintered body, 2 is a via hole, 3 is a circuit conductor, and 4 is an isolated void. As can be seen from the figure, the permittivity is extremely lowered, which is advantageous for speeding up. Regarding other characteristics, the insulation resistance was 10 13 Ω or more, and the dielectric loss was 0.2% or more. In addition to polystyrene used here, the same effect was obtained by using polyester, polyethylene, polymethylmethacrylate, fluororesin or the like as the void forming material.
次に絶縁材料としてコーディエライトとホウケイ酸系
ガラスを用い、ポリスチレンを空隙形成材料として利用
した場合を示す。スラリーの作製以降前記実施例と同様
の条件によりセラミック多層回路基板を得た。コーディ
エライト45wt％ホウケイ酸系ガラス55wt％の組成で空隙
が存在しない場合誘電率は4.8であったが、空隙率５〜4
0vol％のとき誘電率4.4〜2.6まで低下させることができ
た。絶縁抵抗は1013Ω以上、誘電損失は0.2％以下と良
好であった。Next, a case where cordierite and borosilicate glass are used as insulating materials and polystyrene is used as a void forming material is shown. After preparation of the slurry, a ceramic multi-layer circuit board was obtained under the same conditions as in the above example. When the composition of cordierite 45 wt% borosilicate glass 55 wt% and no voids were present, the dielectric constant was 4.8, but the void ratio was 5-4.
At 0 vol%, the dielectric constant could be reduced to 4.4 to 2.6. The insulation resistance was 10 13 Ω or more, and the dielectric loss was 0.2% or less.
（発明の効果） 以上説明したように、本発明の製造方法によれば高分
子空隙形成材料が高温で分解し消失した部分をガラス質
がまわりを囲むように軟化流動し、その結果、完全なク
ローズポア形成される。従って、焼結性の信頼性を損な
うことなく、絶縁層を形成しているセラミック部に空隙
を存在させることによって大幅に誘電率を下げることが
可能となるので、従来のものより高速伝送化という点に
ついてきわめて有利なセラミック多層回路基板が提供で
きる。(Effects of the Invention) As described above, according to the production method of the present invention, the part where the polymer void-forming material decomposes and disappears at a high temperature softens and flows so that the vitreous material surrounds it, and as a result, complete Closed pores are formed. Therefore, it is possible to significantly reduce the permittivity by providing voids in the ceramic part forming the insulating layer without impairing the reliability of the sinterability, and thus it is possible to realize higher speed transmission than the conventional one. It is possible to provide a ceramic multilayer circuit board that is extremely advantageous in terms of points.
第１図は本発明のセラミック多層回路基板の断面模式
図、第２図は石英ガラス−ホウケイ酸系ガラス−α石英
複合系における空隙形成材料の含有率と誘電率の関係を
示す図、 図において、 １はセラミック焼結体、２はビアホール、３は回路導
体、４は孤立空隙をそれぞれ示す。FIG. 1 is a schematic cross-sectional view of a ceramic multilayer circuit board of the present invention, and FIG. 2 is a view showing the relationship between the content of a void-forming material and the dielectric constant in a quartz glass-borosilicate glass-α quartz composite system. , 1 is a ceramic sintered body, 2 is a via hole, 3 is a circuit conductor, and 4 is an isolated void.
Claims (1)
子の空隙形成材料とバインダーとを溶剤中で混合し前記
空隙形成材料を均一に分散させたスラリーを作製する工
程と、該スラリーをグリーンシートに成膜する工程と、
該グリーンシートにビアホールを形成し導体を埋め込む
とともにグリーンシート上に導体配線を印刷する工程
と、積層熱プレス後酸化性雰囲気中で高分子空隙形成材
料を分解せしめ完全に飛散し空隙を形成させる工程と、
焼成工程とを有することを特徴とするセラミック多層回
路基板の製造方法。1. A step of mixing a ceramic mixed powder containing glass, a polymer void-forming material and a binder in a solvent to prepare a slurry in which the void-forming material is uniformly dispersed, and the slurry is a green sheet. A step of forming a film on
A step of forming a via hole in the green sheet and embedding a conductor and printing a conductor wiring on the green sheet; and a step of decomposing the polymer void forming material in an oxidizing atmosphere after lamination hot pressing to completely scatter and form voids When,
A method of manufacturing a ceramic multilayer circuit board, comprising: a firing step.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63269766A JPH088416B2 (en) | 1988-10-25 | 1988-10-25 | Method for manufacturing ceramic multilayer circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63269766A JPH088416B2 (en) | 1988-10-25 | 1988-10-25 | Method for manufacturing ceramic multilayer circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02116196A JPH02116196A (en) | 1990-04-27 |
| JPH088416B2 true JPH088416B2 (en) | 1996-01-29 |
Family
ID=17476848
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63269766A Expired - Lifetime JPH088416B2 (en) | 1988-10-25 | 1988-10-25 | Method for manufacturing ceramic multilayer circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH088416B2 (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2757574B2 (en) * | 1991-03-14 | 1998-05-25 | 日本電気株式会社 | Method for manufacturing low dielectric constant hybrid multilayer ceramic wiring board |
| US5740603A (en) * | 1995-07-31 | 1998-04-21 | Samsung Electro-Mechanics Co., Ltd. | Method for manufacturing low dielectric constant multiple layer ceramic circuit board |
| US6528145B1 (en) * | 2000-06-29 | 2003-03-04 | International Business Machines Corporation | Polymer and ceramic composite electronic substrates |
| JP4511215B2 (en) * | 2004-02-25 | 2010-07-28 | 京セラ株式会社 | Manufacturing method of ceramic multilayer wiring board |
| JP4583047B2 (en) * | 2004-02-25 | 2010-11-17 | 京セラ株式会社 | Resin sheet and method for manufacturing ceramic multilayer wiring board using the same |
| JP2006248074A (en) * | 2005-03-11 | 2006-09-21 | Tdk Corp | Composite substrate with high dielectric constant, composite sheet with high dielectric constant, and methods for producing them |
| JP2007008762A (en) * | 2005-06-30 | 2007-01-18 | Tdk Corp | Composite porous body |
| JP4738166B2 (en) * | 2005-12-22 | 2011-08-03 | 京セラ株式会社 | Wiring board and manufacturing method thereof |
| WO2018083830A1 (en) * | 2016-11-02 | 2018-05-11 | 株式会社村田製作所 | Ceramic electronic component and method for manufacturing ceramic electronic component |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62206861A (en) * | 1986-03-07 | 1987-09-11 | Hitachi Ltd | Ceramic multilayer circuit board and semiconductor mounting structure |
| JPS63202994A (en) * | 1987-02-18 | 1988-08-22 | 富士通株式会社 | Manufacture of multilayer ceramic circuit board |
-
1988
- 1988-10-25 JP JP63269766A patent/JPH088416B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02116196A (en) | 1990-04-27 |
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