JPS60169144A - Die bonding method of semiconductor element - Google Patents
Die bonding method of semiconductor elementInfo
- Publication number
- JPS60169144A JPS60169144A JP2644584A JP2644584A JPS60169144A JP S60169144 A JPS60169144 A JP S60169144A JP 2644584 A JP2644584 A JP 2644584A JP 2644584 A JP2644584 A JP 2644584A JP S60169144 A JPS60169144 A JP S60169144A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- die pad
- semiconductor element
- pad part
- die
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は、リードフレームに半導体素子をはんだ付は
固着する。半導体素子のダイボンド方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] According to the present invention, a semiconductor element is soldered and fixed to a lead frame. The present invention relates to a die bonding method for semiconductor devices.
リードフレームへの半導体素子のけんだＫよるダイボン
ド方法の基本は、第１図に工程順に示すようにして行わ
れている。第１図（ａ）はリードフレームの平面図で、
リードフレーム（１）にはダイパッド部（２）ｌリード
部（３） 、 （４）が形成されている。このダイパッ
ド部（２）上に、第１図（１，）のように、はんだ片（
５）を熱圧着する。つづいて、リードフレーム（１）を
加熱してはんだ片（６）を溶融し、第１図（ｃ）に示す
よう、溶融はんだ（５ａ）に半導体素子（６）を載せ押
付ける。こうして、冷却によシ固化したはんだ層により
、半導体素子（６）が固着される。The basic method of die bonding a semiconductor element to a lead frame using K is carried out as shown in the order of steps shown in FIG. Figure 1(a) is a plan view of the lead frame.
A die pad portion (2), l lead portions (3) and (4) are formed on the lead frame (1). On this die pad part (2), as shown in Fig. 1 (1,), place a piece of solder (
5) are thermocompressed. Subsequently, the lead frame (1) is heated to melt the solder piece (6), and the semiconductor element (6) is placed on the molten solder (5a) and pressed as shown in FIG. 1(c). In this way, the semiconductor element (6) is fixed by the solder layer solidified by cooling.
ここで１問題になるのは、加熱による溶融はんだ（５ａ
）の表面がすぐ酸化され易いため、酸化被膜が生じるこ
とである。この状態で半導体素子（６）を固着すると、
＠２図に示すように、ダイパッド部（２）と半導体素子
（６）との間のはんだ層（５ａ）内には。One problem here is the melted solder (5a) caused by heating.
) is easily oxidized, resulting in the formation of an oxide film. If the semiconductor element (6) is fixed in this state,
@2 As shown in Figure 2, in the solder layer (5a) between the die pad part (2) and the semiconductor element (6).
はんだの巣といわれる空所（７）が生じる。このため、
半導体素子（６）の熱放散が悪くなり、半導体装置の熱
特性が低下することになる。A void (7) called a solder nest is created. For this reason,
Heat dissipation of the semiconductor element (6) will deteriorate, and the thermal characteristics of the semiconductor device will deteriorate.
そこで、これを改善した従来の方法は、喀３図に工程順
に示す説明図のようにダイボンドを行っていた。＠３図
（ａ）はダイボンド装置の概要断面図であり、ヒートブ
ロック（８）には供給穴（９）が設けられており、下方
から窒素、水素なでの不活性ガス、又は還元性のガスな
ど酸化防止の雰囲気ガスを送入する。ヒートブロック（
８）上に置かれたリードフレーム（１）のダイパッド部
（２）を覆う囲い休００を配設する。ヒートブロック（
８）を、内蔵しであるヒータ（図示は略す）により加熱
し、ダイパッド部（２）上のはんだ片（５）を溶融する
。つづいて、第３図（ｂ）に示すよう虻、ダイコレット
０υの下端に吸着している半導体素子（５）を溶融はん
だ（５ａ）上に載せて押付は固着する。Therefore, in a conventional method that improved this, die bonding was performed as shown in the explanatory diagram of the process order in Figure 3. @Figure 3 (a) is a schematic cross-sectional view of the die bonding equipment. The heat block (8) is provided with a supply hole (9), and inert gas such as nitrogen, hydrogen, or reducing gas is supplied from below. Inject atmospheric gas to prevent oxidation, such as gas. heat block (
8) An enclosure 00 is provided to cover the die pad portion (2) of the lead frame (1) placed above. heat block (
8) is heated by a built-in heater (not shown) to melt the solder piece (5) on the die pad portion (2). Subsequently, as shown in FIG. 3(b), the semiconductor element (5) adsorbed to the lower end of the die collet 0υ is placed on the molten solder (5a) and fixed by pressing.
上記従来の方法では、半導体素子（６）を吸着したダイ
コレットαηを囲い体ａＯ内に入れるとき１周囲の空気
が乱流状態となり囲い体００内に巻き込まれ。In the conventional method described above, when the die collet αη with the semiconductor element (6) adsorbed thereon is placed into the enclosure aO, the surrounding air becomes turbulent and is drawn into the enclosure 00.
これにより、溶融はんだ（５ａ）の表面に酸化被膜が生
じ、第２図の場合よりは少ないが、固化したけんだｌ’
１ｉ（５ｂ）内に空所（７）が発生するのを、完全にな
くすることはできなかった。As a result, an oxide film is formed on the surface of the molten solder (5a), and although it is less than in the case of FIG. 2, the solidified solder l'
It was not possible to completely eliminate the occurrence of the void (7) in 1i (5b).
この発明は、上記従来の方法の欠点を除くもので、ヒー
トブロック上に置かれ囲い体に覆われ。The present invention eliminates the drawbacks of the above conventional method, in which the heat block is placed on a heat block and covered with an enclosure.
雰囲気ガスに包まれたリードフレームのダイパッド部を
加熱し、ダイパッド部上のはんだ片を溶融し、被膜除去
板により溶融はんだ表面の酸化被膜を除去し活性面を露
出させ、上方から半導体素子を載せ固着するようにし、
固化したはんだ層内に空所が生じないようにし、良好な
接合がされる、半導体素子のダイボンド方法を提供する
ことを目的としている。The die pad part of the lead frame surrounded by atmospheric gas is heated to melt the solder pieces on the die pad part, and the oxide film on the surface of the molten solder is removed using a film removal plate to expose the active surface, and the semiconductor element is placed from above. Make it stick,
It is an object of the present invention to provide a die bonding method for semiconductor elements, which prevents the formation of voids in a solidified solder layer and achieves good bonding.
以下、この発明の一実施例釦よるダイパッド方法を、第
４図により説明する。図はダイパッドを行っている状態
の概要断面図であり、＋１）、 （２） 、 （５ａ）
、 （６） 、 （８）〜αＢは上記従来のものと同一
のものである。ヒートブロック（８）上のダイパッド部
（２）を囲い体α０で覆い、雰囲気ガスで包んでいる。Hereinafter, a die pad method using a button according to an embodiment of the present invention will be explained with reference to FIG. The figure is a schematic cross-sectional view of the state in which die padding is performed, +1), (2), (5a)
, (6), (8) to αB are the same as the above conventional ones. The die pad portion (2) on the heat block (8) is covered with an enclosure α0 and surrounded by atmospheric gas.
ダイパッド部（２）上にははんだ片（５）を付着しであ
る。ヒートブロック（８）によりダイパッド部（２）を
加熱し、はんだ片（５）を融かし溶融はんだ（５ａ）と
し、この表面を被膜除去板（イ）でこすり酸化被膜を除
去し活性面を露出させる。この状態の溶融はんだ（５ａ
）上にコレットα力下端の半導体素子（５）を載せて押
付け、溶融はんだ（５ａ）の固化により固着する。A solder piece (5) is attached on the die pad part (2). The die pad part (2) is heated with a heat block (8), the solder piece (5) is melted to form molten solder (5a), and the surface is rubbed with a film removal plate (a) to remove the oxide film and remove the active surface. expose. Molten solder in this state (5a
) The semiconductor element (5) at the lower end of the collet α force is placed and pressed, and the molten solder (5a) is solidified and fixed.
以上のように、この発明の方法によれば、ヒートブロッ
ク上のリードフレームのダイパッド部を雰囲気ガスで包
み、加熱によりダイパッド部上のはんだ片を溶融し、溶
融はんだの表面を被膜除去板にこすり、酸化被膜を除去
し活性面を露出させ。As described above, according to the method of the present invention, the die pad portion of the lead frame on the heat block is surrounded by atmospheric gas, the solder pieces on the die pad portion are melted by heating, and the surface of the molten solder is rubbed against the film removal plate. , remove the oxide layer and expose the active surface.
半導体素子を載せて押付は固着するようにしたので、固
化したはんだ層内に空所が生じることがなくなり、良好
な固着接合ができ、半導体装置の熱特性が改善される。Since the semiconductor element is mounted and pressed firmly, no voids are created in the solidified solder layer, good adhesive bonding is achieved, and the thermal characteristics of the semiconductor device are improved.
第１図はリードフレームに半導体素子をダイボンドする
状態を工程順に示す平面図、第２図は半導体素子を固着
したはんだ層の欠陥を示す断面図。
第３図は従来の半導体素子のダイボンド方法を工程順に
示すダイボンド用具部の断面図、＃Ｊ４図はこの発明の
一実施例による半導体素子のダイボンド方法を示すダイ
ボンド用具部の断面図である。
１・・・リードフレーム、２・・・ダイバラ）’部、５
・・・はんだ片、 ５ａ・・・溶融はんだ、６・・・半
導体素子、８・・・ヒートブロック、ｌｏ川用い体、１
１・・・ダイコレット、２２・・・被膜除去板
なお、図中同一符号は同−又は相当部分を示す。
代理人 大岩増雄
第１図
第２図
７
第３図
（久）
（ｂ）
第４図
手続補正書（自発）
１、事件の表示 特願昭５９−２６４４５９２、発明（
１）名称 半導体素子のダイボンド方法３、補正をする
者
事件との関係 特許出願人
代表者片山仁へ部
４、代理人
住 所 東京都千代田区丸の内二丁目２番３号三菱電機
株式会社内
５、補正の対象
明細書の「発明の詳細な説明」の欄〇
う、補正の内容
（１） 明細書第２ページ第１４行の「はんだ層（５ａ
）」を「はんだ層（５ｂ） ｊに補正する。
（２） 明細書第３ページ第２行の「水素なで」を「水
素など」Ｋ補正する。
（３）明細書第３ページ第１０行及び第５ページ第２行
の「半導体素子（５）」を［半導体素子（６） Ｊ Ｋ
肩正する。
（４）明細書第４ページ第１１．１２行の「ダイパッド
」を「ダイボンド」に補正する。
（５）明細書第５ページ第９行の「板に」を「板で」に
補正する。
以上FIG. 1 is a plan view showing the state in which a semiconductor element is die-bonded to a lead frame in the order of steps, and FIG. 2 is a cross-sectional view showing defects in the solder layer to which the semiconductor element is fixed. FIG. 3 is a cross-sectional view of a die-bonding tool section showing a conventional die-bonding method for semiconductor devices in the order of steps, and FIG. #J4 is a cross-sectional view of a die-bonding tool section showing a die-bonding method for semiconductor devices according to an embodiment of the present invention. 1...Lead frame, 2...Diabara)' part, 5
... Solder piece, 5a... Molten solder, 6... Semiconductor element, 8... Heat block, lo river body, 1
1... Die collet, 22... Film removal plate Note that the same reference numerals in the drawings indicate the same or corresponding parts. Agent Masuo Oiwa Figure 1 Figure 2 Figure 7 Figure 3 (Kyu) (b) Figure 4 Procedural amendment (spontaneous) 1. Indication of the case Patent application No. 59-2644592, Invention (
1) Name: Semiconductor device die bonding method 3, relationship with the amended case Patent applicant representative: Hitoshi Katayama Department 4, agent address: 5, Mitsubishi Electric Corporation, 2-2-3 Marunouchi, Chiyoda-ku, Tokyo , "Detailed Description of the Invention" column of the specification to be amended 〇 Contents of the amendment (1) "Solder layer (5a
)” to “solder layer (5b) j.” (2) “Hydrogen stroke” in the second line of page 3 of the specification is corrected to “hydrogen, etc.” K. (3) "Semiconductor element (5)" in the 10th line of the 3rd page and the 2nd line of the 5th page of the specification [Semiconductor element (6) J K
Straighten your shoulders. (4) Correct "die pad" in lines 11 and 12 of page 4 of the specification to "die bond." (5) Correct "on the board" in line 9 of page 5 of the specification to "on the board."that's all
Claims (1)
付着してヒートブロック上に載せ、上記ダイパッド部上
を囲い体で覆い雰囲気ガスで包み、上記ヒートブロック
によシ上記ダイパッド部を加熱し上記はんだ片を溶融し
、この溶融はんだ表面を被膜除去板によりこすり酸化被
膜を除去し、露出した活性面に半導体素子を載せて押付
け、固着させる半導体素子のダイボンド方法。(1) A piece of solder is attached to the die pad part of the lead frame and placed on a heat block, the die pad part is covered with an enclosure and surrounded by atmospheric gas, and the die pad part is heated by the heat block and soldered. A die bonding method for semiconductor devices, in which a piece is melted, the surface of the molten solder is rubbed with a film removal plate to remove the oxide film, and the semiconductor device is placed on the exposed active surface and pressed and fixed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2644584A JPS60169144A (en) | 1984-02-13 | 1984-02-13 | Die bonding method of semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2644584A JPS60169144A (en) | 1984-02-13 | 1984-02-13 | Die bonding method of semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60169144A true JPS60169144A (en) | 1985-09-02 |
Family
ID=12193701
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2644584A Pending JPS60169144A (en) | 1984-02-13 | 1984-02-13 | Die bonding method of semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60169144A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5770468A (en) * | 1993-01-12 | 1998-06-23 | Mitsubishi Denki Kabushiki Kaisha | Process for mounting a semiconductor chip to a chip carrier by exposing a solder layer to a reducing atmosphere |
| GB2377402A (en) * | 2001-07-12 | 2003-01-15 | Agilent Technologies Inc | Die bond strip |
-
1984
- 1984-02-13 JP JP2644584A patent/JPS60169144A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5770468A (en) * | 1993-01-12 | 1998-06-23 | Mitsubishi Denki Kabushiki Kaisha | Process for mounting a semiconductor chip to a chip carrier by exposing a solder layer to a reducing atmosphere |
| GB2377402A (en) * | 2001-07-12 | 2003-01-15 | Agilent Technologies Inc | Die bond strip |
| GB2377402B (en) * | 2001-07-12 | 2004-05-12 | Agilent Technologies Inc | Improved diebond strip |
| US6752308B2 (en) | 2001-07-12 | 2004-06-22 | Agilent Technologies, Inc. | Diebond strip |
| US7559455B2 (en) | 2001-07-12 | 2009-07-14 | Avago Technologies Fiber Ip (Singapore) Pte. Ltd. | Diebond strip |
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