JP3269398B2 - Soldering method for work with bump - Google Patents

Soldering method for work with bump

Info

Publication number
JP3269398B2
JP3269398B2 JP24584796A JP24584796A JP3269398B2 JP 3269398 B2 JP3269398 B2 JP 3269398B2 JP 24584796 A JP24584796 A JP 24584796A JP 24584796 A JP24584796 A JP 24584796A JP 3269398 B2 JP3269398 B2 JP 3269398B2
Authority
JP
Japan
Prior art keywords
work
bump
solder
bumps
solder portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP24584796A
Other languages
Japanese (ja)
Other versions
JPH1092873A (en
Inventor
忠彦 境
秀喜 永福
満 大園
省二 酒見
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to JP24584796A priority Critical patent/JP3269398B2/en
Publication of JPH1092873A publication Critical patent/JPH1092873A/en
Application granted granted Critical
Publication of JP3269398B2 publication Critical patent/JP3269398B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134Stud bumping, i.e. using a wire-bonding apparatus
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13016Shape in side view
    • H01L2224/13018Shape in side view comprising protrusions or indentations
    • H01L2224/13019Shape in side view comprising protrusions or indentations at the bonding interface of the bump connector, i.e. on the surface of the bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81193Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • H05K3/3436Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457Solder materials or compositions; Methods of application thereof

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、バンプをワークの
パッド上に半田付けするバンプ付きワークの半田付け方
法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of soldering a work with bumps, which solders bumps to pads of the work.

【0002】[0002]

【従来の技術】フリップチップなどのバンプ付きワーク
のプリント基板などのワークへの半田付けは、次のよう
にして行われていた。まず、バンプ付きワークに形成さ
れたバンプやワークのパッド上に形成された半田部の表
面にフラックスを塗布する。次にバンプを半田部に着地
させてバンプ付きワークをワーク上に搭載する。次にワ
ークを加熱炉へ送り、半田部をその融点(一般には20
0°C程度)以上に加熱して溶融させ、次いで冷却する
ことにより固化させる。以上によりバンプ付きワークを
ワークに実装する。
2. Description of the Related Art Soldering of a work with bumps such as a flip chip to a work such as a printed circuit board has been performed as follows. First, a flux is applied to the bumps formed on the work with bumps and the surface of the solder portion formed on the pads of the work. Next, the bump is landed on the solder portion, and the work with the bump is mounted on the work. Next, the work is sent to a heating furnace, and the solder part is heated to its melting point (generally,
(About 0 ° C.) or higher to melt and then solidify by cooling. Thus, the work with bumps is mounted on the work.

【0003】[0003]

【発明が解決しようとする課題】しかしながら上記従来
方法には、次のような問題点があった。すなわち、パッ
ド上の半田部の表面には、空気に触れることにより、電
気抵抗の大きい酸化膜が生じることから、バンプとパッ
ドの間の導通が不十分になりやすかった。このような問
題点を解決する方法としては、フラックスを十分に使用
することである。フラックスを十分に使用すれば、半田
のぬれ性を改善し、酸化膜の悪影響を軽減できる。
However, the above-mentioned conventional method has the following problems. That is, an oxide film having a large electric resistance is formed on the surface of the solder portion on the pad by contact with air, so that the conduction between the bump and the pad tends to be insufficient. As a method for solving such a problem, a sufficient use of flux is required. If the flux is sufficiently used, the wettability of the solder can be improved and the adverse effect of the oxide film can be reduced.

【0004】しかしながらフラックスの使用量が多い程
溶融した半田の流動性は増大し、相隣るパッド上の半田
同士がつながって短絡の原因となる半田ブリッジが生じ
やすいという問題が生じる。
However, as the amount of the flux used increases, the flowability of the molten solder increases, and the solder on adjacent pads is connected to each other, so that there is a problem that a solder bridge, which causes a short circuit, is likely to occur.

【0005】したがって本発明は、フラックスの使用量
を少なくし、更に望ましくはフラックスを不要にして、
バンプとパッドの導通性を十分に確保できるバンプ付き
ワークの半田付け方法を提供することを目的とする。
Accordingly, the present invention reduces the amount of flux used, and more desirably eliminates the need for flux.
An object of the present invention is to provide a method for soldering a work with bumps, which can sufficiently secure the conductivity between the bump and the pad.

【0006】[0006]

【課題を解決するための手段】本発明は、バンプ付きワ
ークのバンプから下方へ突出する高硬度の突出部を横倒
ししながらワークのパッド上に形成された半田部に押し
付けて、この半田部の表面の酸化膜を前記突出部により
部分的に破壊して前記突出部を前記半田部に食い込ま
せ、次いで前記半田部を加熱して接合させるようにし
た。
SUMMARY OF THE INVENTION According to the present invention, a high-hardness protruding portion projecting downward from a bump of a bumped work is pressed down on a solder portion formed on a pad of the work while lying down, and the solder portion is formed. The oxide film on the surface is partially broken by the projecting portion so that the projecting portion bites into the solder portion, and then the solder portion is heated and joined.

【0007】[0007]

【発明の実施の形態】上記構成の本発明によれば、バン
プの突出部を半田部に食い込ませたうえで、半田部を接
合させるようにしているので、バンプとパッドの導通性
を十分に確保して半田付けすることができる。
According to the present invention having the above structure, the bumps are cut into the solder portions and then the solder portions are joined, so that the conductivity between the bumps and the pads can be sufficiently improved. It can be secured and soldered.

【0008】以下、本発明の実施の形態を図面を参照し
て説明する。図1は、本発明の一実施の形態のバンプ付
きワークの半田付け工程図、図2は同バンプ付きワーク
の半田付け工程におけるバンプと半田部の拡大断面図、
図3は同バンプの形成工程図である。
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a soldering process diagram of a work with bumps according to an embodiment of the present invention. FIG.
FIG. 3 is a process chart for forming the bump.

【0009】図1(a)において、バンプ付きワーク1
の下面のパッド4にはバンプ2が形成されている。この
バンプ2は金バンプである。バンプ2は下方へ突出する
突出部3を有している。突出部3は図示するように傾い
ている。この突出部3は高硬度を有している。次に、図
3を参照して、高硬度の突出部3を有するバンプ2の形
成方法を説明する。
In FIG. 1A, a work 1 with bumps is shown.
The bumps 2 are formed on the pads 4 on the lower surface of the. This bump 2 is a gold bump. The bump 2 has a protruding portion 3 protruding downward. The protrusion 3 is inclined as shown. The protrusion 3 has high hardness. Next, a method of forming the bump 2 having the high hardness protrusion 3 will be described with reference to FIG.

【0010】図3は、ワイヤボンディング技術を用いて
バンプを形成する方法を示している。図3に示すバンプ
の形成方法は、例えば特開平4−37034号公報に記
載されている。11はホーン(図示せず)の先端部に保
持されたキャピラリツールであり、細いワイヤ(金線)
3’が挿通されている。
FIG. 3 shows a method of forming a bump by using a wire bonding technique. The method of forming the bump shown in FIG. 3 is described in, for example, Japanese Patent Application Laid-Open No. 4-37034. Reference numeral 11 denotes a capillary tool held at the tip of a horn (not shown), which is a thin wire (gold wire).
3 'is inserted.

【0011】キャピラリツール11から下方へ導出する
ワイヤ3’の下端部にトーチ12を接近させ、トーチ1
2に高電圧を印加してトーチ12とワイヤ3’の下端部
の間に電気的スパークを発生させる。するとワイヤ3’
の下端部は溶融してボール2’が生じる。次にトーチ1
2を側方へ退去させたうえで、図3(b)に示すように
キャピラリツール11を下降させ、ボール2’をワーク
1のパッド5に押し付けてボンディングする。本例のワ
ーク1は半導体素子である。
The torch 12 is moved closer to the lower end of the wire 3 'extending downward from the capillary tool 11, and
2 to generate an electric spark between the torch 12 and the lower end of the wire 3 '. Then wire 3 '
Is melted to form a ball 2 '. Next, torch 1
After leaving 2 sideways, the capillary tool 11 is lowered as shown in FIG. 3B, and the ball 2 ′ is pressed against the pad 5 of the work 1 for bonding. The work 1 of the present example is a semiconductor element.

【0012】次にキャピラリツール11を上昇させ、ま
たキャピラリツール11の上方でワイヤ3’をクランパ
(図示せず)でクランプし、ワイヤ3’を引き上げる。
するとワイヤ3’はボール2’のやや上方で切断され、
図3(c)に示すように突出部3を有するバンプ2がパ
ッド4上に完成する。すなわち突出部3は、ワイヤ3’
の切れはしである。以上により、図1(a)に示すバン
プ付きワーク1を製造する。
Next, the capillary tool 11 is raised, and the wire 3 'is clamped by a clamper (not shown) above the capillary tool 11, and the wire 3' is pulled up.
Then, the wire 3 'is cut slightly above the ball 2',
As shown in FIG. 3C, the bump 2 having the protrusion 3 is completed on the pad 4. That is, the protrusion 3 is connected to the wire 3 ′
This is a piece of paper. Thus, the work 1 with bumps shown in FIG. 1A is manufactured.

【0013】さて、図3(a)に示すように電気的スパ
ークを発生させて、バンプ2の元になるボール2’を形
成するのであるが、ボール2’の近くのワイヤ3は電気
的スパークにより高温度に加熱され、次いで急激に自然
冷却されることから、ワイヤ3’よりも高硬度となる。
この高硬度となる部分にはハッチングを付している。そ
してワイヤ3’をクランパでクランプして引き上げれ
ば、ワイヤ3’は高硬度の部分とそうでない部分の境界
で切断され、図3(c)に示す突出部3を有するバンプ
2が形成されるものである。
Now, as shown in FIG. 3 (a), an electric spark is generated to form a ball 2 'which is a source of the bump 2. The wire 3 near the ball 2' is connected to the electric spark. Is heated to a higher temperature and then rapidly cooled naturally, so that the hardness is higher than that of the wire 3 '.
The high hardness portions are hatched. When the wire 3 'is clamped by a clamper and pulled up, the wire 3' is cut at the boundary between the high hardness portion and the non-hard portion, and the bump 2 having the protruding portion 3 shown in FIG. 3C is formed. Things.

【0014】次に図3(c)に示すように押圧治具13
を突出部3の上端部に押し付ければ(鎖線で示す押圧治
具13を参照)、突出部3は傾き、図1(a)に示す突
出部3を有するバンプ付きワーク1が出来上る。
Next, as shown in FIG.
Is pressed against the upper end of the protruding portion 3 (see the pressing jig 13 shown by a dashed line), the protruding portion 3 is inclined, and the bumped work 1 having the protruding portion 3 shown in FIG.

【0015】さて、図1(a)において、5はワークで
あり、その上面にはパッド6が形成されている。またパ
ッド6上には半田部7が形成されている。本例のワーク
5はプリント基板である。また半田部7は半田メッキや
半田レベラにより形成されている。図1(a)に示すよ
うに、バンプ付きワーク1をヘッド8の下面に真空吸着
して保持し、図1(b)に示すようにヘッド8を下降さ
せてバンプ2をワーク5の半田部7上に着地させ、バン
プ2を半田部7に強く押し付ける。
In FIG. 1A, reference numeral 5 denotes a work, on which a pad 6 is formed. Further, a solder portion 7 is formed on the pad 6. The work 5 of this example is a printed circuit board. The solder portion 7 is formed by solder plating or a solder leveler. As shown in FIG. 1A, the work 1 with bumps is held by vacuum suction on the lower surface of the head 8, and as shown in FIG. 7, and the bump 2 is pressed strongly against the solder portion 7.

【0016】図2(a)、(b)は、バンプ2を半田部
7に押し付ける様子を拡大して示している。図2(a)
に示す状態からバンプ付きワーク1を下降させて、図2
(b)に示すようにバンプ2を半田部7に強く押し付け
る。半田部7の表面には、空気に触れることにより酸化
膜9が生じている。上述したように酸化膜9は電気抵抗
が大きく、バンプ2とパッド6の導通性を阻害する。こ
の酸化膜9に突出部3が横倒しされながら押し付けられ
ることにより、酸化膜9は図示するように部分的に破壊
され、突出部3は半田部7に食い込んで直に半田部7に
接触する。この場合、半田部7はPbやSnなどのやわ
らかい合金であり、また突出部3は上述したように高硬
度を有するので、酸化膜9を効果的に破壊したうえで、
半田部7に十分に食い込んで半田部7に接触することが
できる。さらには、突出部3は図3(c)に示す工程で
傾けているので、半田部7に押し付けると図2(b)に
示すように確実に横倒しされ、広範囲に酸化膜9を破壊
してより広く半田部7に直に接触することができる。
FIGS. 2A and 2B show an enlarged view of pressing the bump 2 against the solder portion 7. FIG. 2 (a)
2 is lowered from the state shown in FIG.
As shown in (b), the bump 2 is pressed strongly against the solder portion 7. An oxide film 9 is formed on the surface of the solder portion 7 by contact with air. As described above, the oxide film 9 has a large electric resistance and hinders the conductivity between the bump 2 and the pad 6. By pressing the protruding portion 3 against the oxide film 9 while lying down, the oxide film 9 is partially broken as shown in the figure, and the protruding portion 3 bites into the solder portion 7 and directly contacts the solder portion 7. In this case, the solder portion 7 is made of a soft alloy such as Pb or Sn, and the protruding portion 3 has a high hardness as described above.
It is possible to sufficiently penetrate into the solder portion 7 and come into contact with the solder portion 7. Further, since the protruding portion 3 is inclined in the step shown in FIG. 3C, when the protruding portion 3 is pressed against the solder portion 7, the protruding portion 3 is securely turned over as shown in FIG. It can directly contact the solder part 7 more widely.

【0017】以上のようにしてバンプ付きワーク1をワ
ーク5上に搭載したならば、図1(c)に示すようにバ
ンプ付きワーク1が搭載されたワーク5を加熱炉10で
加熱し、半田部7を溶融させ、次いで冷却して固化させ
てバンプ2をパッド6上に半田付けする。図2(c)
は、半田付けが終了したバンプ2付近の部分拡大図であ
る。図示するように、半田部7が溶融・固化したことに
より、バンプ2はパッド6上に半田付けされるが、酸化
膜9は破壊されているのでバンプ2は半田部6と一体と
なり、十分な導通性を確保できる。
After the work 1 with bumps is mounted on the work 5 as described above, the work 5 on which the work 1 with bumps is mounted is heated in a heating furnace 10 as shown in FIG. The part 7 is melted and then cooled and solidified to solder the bump 2 onto the pad 6. FIG. 2 (c)
FIG. 4 is a partially enlarged view of the vicinity of the bump 2 after soldering is completed. As shown in the figure, the bumps 2 are soldered on the pads 6 due to the melting and solidification of the solder portions 7, but since the oxide film 9 has been destroyed, the bumps 2 are integrated with the solder portions 6 and sufficient Conductivity can be ensured.

【0018】本発明は上記実施の形態に限定されないの
であって、例えば本発明によればフラックスを用いなく
てもバンプを十分に半田付けできるが、フラックスの使
用を禁止するものではない。また上記実施の形態では、
図3(c)に示す工程で突出部3を押圧治具13で積極
的に傾けているが、このような工程をとらず、バンプ2
からまっすぐに下方へ突出する突出部3を図1(a)、
(b)に示す工程で半田部7に押し付ければ、突出部3
は横倒しされて上記実施の形態と同様の作用効果が得ら
れる。また半田部7とバンプ2の接合方法としては、突
出部3で酸化膜9を破壊して半田部7と突出部3を接触
させ、その後この接触部分に熱と超音波を作用させて両
者を接合させてもよい。この場合、半田部7は溶融させ
る必要はない。
The present invention is not limited to the above embodiment. For example, according to the present invention, bumps can be sufficiently soldered without using flux, but the use of flux is not prohibited. In the above embodiment,
In the step shown in FIG. 3C, the protruding portion 3 is positively inclined by the pressing jig 13.
FIG. 1 (a) shows a projecting portion 3 projecting straight down from
By pressing the solder portion 7 in the step shown in FIG.
Is turned over, and the same operation and effect as in the above embodiment can be obtained. As a method of joining the solder portion 7 and the bump 2, the oxide film 9 is broken at the projecting portion 3 to bring the solder portion 7 into contact with the projecting portion 3, and then heat and ultrasonic waves are applied to the contact portion to join the two. They may be joined. In this case, the solder portion 7 does not need to be melted.

【0019】[0019]

【発明の効果】本発明は、バンプの高硬度の突出部を半
田部に食い込ませたうえで、半田部を接合させるように
しているので、バンプとパッドの導通性を十分に確保し
て半田付けすることができる。
According to the present invention, the solder portion is joined after the high-hardness protrusion of the bump is cut into the solder portion, so that the conductivity between the bump and the pad is sufficiently ensured. Can be attached.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施の形態のバンプ付きワークの半
田付け工程図
FIG. 1 is a process chart of soldering a work with bumps according to an embodiment of the present invention.

【図2】本発明の一実施の形態のバンプ付きワークの半
田付け工程におけるバンプと半田部の拡大断面図
FIG. 2 is an enlarged cross-sectional view of a bump and a solder portion in a soldering step of a work with a bump according to an embodiment of the present invention.

【図3】本発明の一実施の形態のバンプの形成工程図FIG. 3 is a process chart of forming a bump according to an embodiment of the present invention;

【符号の説明】[Explanation of symbols]

1 バンプ付きワーク 2 バンプ 3 突出部 5 ワーク 6 パッド 7 半田部 9 酸化膜 DESCRIPTION OF SYMBOLS 1 Work with a bump 2 Bump 3 Projection part 5 Work 6 Pad 7 Solder part 9 Oxide film

フロントページの続き (72)発明者 酒見 省二 大阪府門真市大字門真1006番地 松下電 器産業株式会社内 (56)参考文献 特開 平2−15635(JP,A) 特開 平2−34949(JP,A) 特開 平4−10446(JP,A) 特開 平4−273131(JP,A) 特開 平6−232209(JP,A) 特開 平7−193099(JP,A) 特開 平8−186152(JP,A) 特開 平9−306953(JP,A) 特開 平10−199935(JP,A) (58)調査した分野(Int.Cl.7,DB名) H01L 21/60 Continuation of the front page (72) Inventor Shoji Sakami 1006 Kazuma, Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. (56) References JP-A-2-15635 (JP, A) JP-A-2-34949 (JP, A) JP-A-4-10446 (JP, A) JP-A-4-273131 (JP, A) JP-A-6-232209 (JP, A) JP-A-7-1993099 (JP, A) JP-A-8-186152 (JP, A) JP-A-9-306953 (JP, A) JP-A-10-199935 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 21 / 60

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】バンプ付きワークのバンプをワークのパッ
ド上に半田付けするバンプ付きワークの半田付け方法で
あって、バンプ付きワークのバンプから下方へ突出する
高硬度の突出部を横倒ししながらワークのパッド上に形
成された半田部に押し付けて、この半田部の表面の酸化
膜を前記突出部により部分的に破壊して前記突出部を前
記半田部に食い込ませ、次いで前記半田部を加熱して接
合させることを特徴とするバンプ付きワークの半田付け
方法。
1. A method for soldering a bumped work, the method comprising: soldering a bump of the bumped work onto a pad of the work; Pressing the solder portion formed on the pad, the oxide film on the surface of the solder portion is partially broken by the protrusion, the protrusion is cut into the solder portion, and then the solder portion is heated. A method of soldering a work with bumps, characterized in that they are joined together.
JP24584796A 1996-09-18 1996-09-18 Soldering method for work with bump Expired - Lifetime JP3269398B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24584796A JP3269398B2 (en) 1996-09-18 1996-09-18 Soldering method for work with bump

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24584796A JP3269398B2 (en) 1996-09-18 1996-09-18 Soldering method for work with bump

Publications (2)

Publication Number Publication Date
JPH1092873A JPH1092873A (en) 1998-04-10
JP3269398B2 true JP3269398B2 (en) 2002-03-25

Family

ID=17139737

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24584796A Expired - Lifetime JP3269398B2 (en) 1996-09-18 1996-09-18 Soldering method for work with bump

Country Status (1)

Country Link
JP (1) JP3269398B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3344289B2 (en) * 1997-07-18 2002-11-11 松下電器産業株式会社 Mounting method of work with bump

Also Published As

Publication number Publication date
JPH1092873A (en) 1998-04-10

Similar Documents

Publication Publication Date Title
JP3565047B2 (en) Solder bump forming method and solder bump mounting method
JPH08191114A (en) Resin sealed semiconductor and manufacturing method thereof
US6168070B1 (en) Method for soldering DPAK-type electronic components to circuit boards
JP3269398B2 (en) Soldering method for work with bump
JP3381593B2 (en) How to mount electronic components with bumps
JP2828069B2 (en) Soldering method of work with bump
JPS60134444A (en) Formation for bump electrode
JP3385943B2 (en) How to mount electronic components with gold bumps
JP3344289B2 (en) Mounting method of work with bump
JP2975207B2 (en) Wire bonding equipment with solder wire
JP2870506B2 (en) Soldering method of work with bump
JPH05152485A (en) Semiconductor devices and manufacture thereof
JPS60194543A (en) Forming method of bump electrode
JP3210456B2 (en) Method of forming ball on metal wire
JP2003297874A (en) Connection structure and connection method for electronic component
JP2005101165A (en) Flip chip mounting structure, substrate for mounting the same, and method of manufacturing the same
JPH05235098A (en) Flip chip bonding method
JP3827442B2 (en) Manufacturing method of semiconductor package
JPH04181762A (en) Electronic component
JP2001053097A (en) Method for forming stud bump
JP3269399B2 (en) Mounting method of work with bump
JP2006114649A (en) Method and apparatus for manufacturing semiconductor device
JPH11145363A (en) Semiconductor device
JPH05144872A (en) Joining method of bump electrode
JPS63128574A (en) Connector pin

Legal Events

Date Code Title Description
FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080118

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090118

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090118

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100118

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100118

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110118

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110118

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120118

Year of fee payment: 10

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130118

Year of fee payment: 11

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130118

Year of fee payment: 11

EXPY Cancellation because of completion of term