JPS60168236A - Microprogram controller - Google Patents

Abstract

PURPOSE:To make debugging easy and accurate by discriminating execution of a micro instruction in an address when coincidence of this address is detected. CONSTITUTION:When a worker sets an address (m+2) following an address (m+ 1) to an external address setter 21 and starts the operation in case of debugging of a microprogram controller, execution clocks are generated at a prescribed period, and an execution address 16 is changed in accordance with them. Since a set address 22 is fixed to the address (m+2), the execution address 16 coincides with the set address when it reaches the address (m+2), and at this time, a comparison result 24 goes to the high level, and an address coincidence pulse 26 is outputted, and the operation of a CPU is analyzed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microprogram control device for controlling a CPU.

[Prior art]

A microprogram control device that controls a CPLI (central processing unit) according to a microprogram is widely used in general information processing devices.

FIG. 1 schematically shows a conventional microprogram control device. Microprogram storage memo IJ
l1 is a memory provided inside the CPLI, and is distinguished from a main storage device provided externally. The microprogram storage memory 11 is FROM (Programmable Read Only Memory) or RAM (Random Memory).
It is composed of a memory element such as an access memo, and stores a microprogram.

The individual instructions that make up a microprogram are called microinstructions. The microinstruction 12 read from the microprogram storage memory 11 is latched by the latch circuit 13. The output 14 of the latch circuit 13 is the microprogram execution circuit 15
This is where the instructions are decoded and executed. At this time, the address to be accessed next (hereinafter the execution address
) is revealed. This execution address 16 is supplied to the microprogram storage memory 11.

The microprogram storage memory 11 outputs the microinstruction at the address specified by this at the next timing.

In this way, the microinstructions are sequentially executed in synchronization with the lock 17 executed.

Since the above-mentioned microprogram control device controls the CVU using a memory in which a predetermined program is stored in advance, it can also be regarded as software converted into software (firmware). However, when actually designing or evaluating firmware, the individual signals output from the circuit device (1-ware) itself no longer have any meaning. That is, during design or evaluation, it is necessary to consider how the CPU will be controlled, and understanding the address at which an instruction is executed has an important meaning.

For this reason, when debugging a microprogram control device, the method is to connect all bits of address information that appear on the address bus to a logic analyzer, determine the signal state individually, and decipher the address. was taken. When Nanakoro used a logic analyzer, there was a problem in that it was impossible to determine the address when a connection error with the address bus occurred. Furthermore, when the address information is composed of a large number of bits, there is also the problem that the logic analyzer cannot be connected to the address bus at once. Furthermore, connecting the logic analyzer is not only very cumbersome to work with, but also has the problem of reducing work efficiency.

[Purpose of the invention]

In view of these circumstances, it is an object of the present invention to provide a microprogram control device that can easily determine whether a microinstruction at a desired address is to be executed.

[Structure of the invention]

In the present invention, a microprogram control device is equipped with an external address setting means that can specify an address from the outside, and a comparison means that compares the set address with an execution address, and when a match of addresses is detected, To make it possible to determine that a microinstruction at an address is executed.

〔Example〕

The present invention will be described in detail with reference to Examples below.

FIG. 2 shows the microprogram control device of this embodiment. Components that are the same as those in FIG. 1 are designated by the same reference numerals, and their description will be omitted as appropriate. This device is equipped with an external address setter 21. The external address setting device 21 is made up of, for example, a dip switch, and can set a desired address by operating the switch.

The set address 22 set by the external address setter 21 is compared with the execution address by a comparison circuit 23. The comparison circuit 23 is composed of n comparators that compare each piece of address information consisting of n bits (n is any integer) corresponding to each bit, and an AND gate that takes the logical product of the outputs of these comparators. can do. The comparison circuit 23 is designed to output a comparison result 24, and the sampling circuit 2
5 samples this result.

Now, when debugging this microprogram control device, the operator sets one of the addresses to be verified using the external address setter 21. Microinstructions, which are individual instructions of a microprogram, are stored in the microprogram storage memory 11 for each address. For example, FIG. 3 shows a part of how microinstructions are sequentially executed. In this example, the next address after the address (m+1>) where the branch instruction exists may be the one to be verified.In this case, the operator must check the address (m+2) or (m+50) that follows the address (m+1). is set in the external address setter 21.

Assuming that address (m+2) is set in the external address setter 21, the operator operates the microprogram control device in this state. As a result, the execution lock 17 (FIG. 4a) is generated at a predetermined period, and the execution address 16 (FIG. 4b) changes accordingly. At this time, the setting address 22 (FIG. 4C) is fixed at (m+2).

Therefore, when the execution address 16 changes to (m) and (m+1) and then becomes (m+2), it matches the set address 22 at this point, and the comparison result 24 (Fig. 4 d) becomes H (high).
level.

The sampling circuit 25 consists of a D-7 lip-flop circuit, and receives the input from the execution lock 17 and samples the comparison result 24. Therefore, when the execution address 16 and the setting address 22 match and the comparison result 24 becomes H level,
The address match pulse 26 at H level is output from the rising edge of the lock 17 to the next rising edge. The address match pulse 26 is input to a synchronization terminal of a verification device such as a digital tracer, and the operation of the CPU is analyzed.

Although the external address setter 21 has been described as a switch in the embodiment, it is of course possible to use a circuit that logically generates an address.

〔Effect of the invention〕

As explained above, according to the present invention, since the circuit portion for address discrimination is integrally provided in the microblock controller, depacking can be performed easily and accurately.

[Brief explanation of the drawing]

Figure 1 shows the blower of a conventional microprogram controller.
2 is a block diagram of a microprogram control device according to an embodiment of the present invention, FIG. 3 is a flowchart showing part of the flow of microinstructions, and FIG. 4 is a block diagram showing the operation of the device of this embodiment. This is a timing diagram that is beyond explanation. 11...Micro program storage memory, 12
・・・・・・Micro instructions, 13...
... Latch circuit, 16 ... Execution address, 17 ... Execution lock, 21 ... External address setter, 23 ...
・Comparison circuit, 25...Sampling circuit. Applicant: Fuji Xerox Co., Ltd. Agent: Patent Attorney Umeo Yamauchi 1 Figure 2 En

Claims (1)

[Claims] A microprogram storage memory storing a microprogram, a latch means for latching microinstructions read from the memory, a microprogram execution means for decoding the output of the latch means and executing the microprogram, and a microprogram execution means for decoding the output of the latch means and executing the microprogram. an external address setting means for setting an address; a comparison means for comparing the address to be executed next decoded by the microprogram execution means with the address set by the external address setting means; 1. A microprogram control device comprising: pulse generation means that outputs a pulse when a match is detected.