JPS60166151U - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS60166151U JPS60166151U JP1984052155U JP5215584U JPS60166151U JP S60166151 U JPS60166151 U JP S60166151U JP 1984052155 U JP1984052155 U JP 1984052155U JP 5215584 U JP5215584 U JP 5215584U JP S60166151 U JPS60166151 U JP S60166151U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- circuit device
- semiconductor integrated
- semiconductor
- moisture
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05073—Single internal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来の半導体集積回路装置の断面図、第2図は
本考案の一実施例の断面図である。
1・・・・・・半導体ペレット、2,4・・・・・・ポ
ンディングパッド、3・・・・・・パシベーション膜、
5・俸・・・・A1層、6・・・・・・Ti−Pt層。FIG. 1 is a sectional view of a conventional semiconductor integrated circuit device, and FIG. 2 is a sectional view of an embodiment of the present invention. 1...Semiconductor pellet, 2,4...Ponding pad, 3...Passivation film,
5. Salary... A1 layer, 6... Ti-Pt layer.
Claims (1)
ングパッド表面が、水分に対し化学反応を起し難い金属
で被われていることを特徴とする一半導体集積回路装置
。A semiconductor integrated circuit device characterized in that the surface of an aluminum bonding pad provided on a semiconductor pellet is covered with a metal that does not easily cause a chemical reaction with moisture.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1984052155U JPS60166151U (en) | 1984-04-10 | 1984-04-10 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1984052155U JPS60166151U (en) | 1984-04-10 | 1984-04-10 | Semiconductor integrated circuit device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60166151U true JPS60166151U (en) | 1985-11-05 |
Family
ID=30571852
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1984052155U Pending JPS60166151U (en) | 1984-04-10 | 1984-04-10 | Semiconductor integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60166151U (en) |
-
1984
- 1984-04-10 JP JP1984052155U patent/JPS60166151U/en active Pending
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