JPS60160557U - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS60160557U JPS60160557U JP5024284U JP5024284U JPS60160557U JP S60160557 U JPS60160557 U JP S60160557U JP 5024284 U JP5024284 U JP 5024284U JP 5024284 U JP5024284 U JP 5024284U JP S60160557 U JPS60160557 U JP S60160557U
- Authority
- JP
- Japan
- Prior art keywords
- insulating layer
- conductivity type
- epitaxial layer
- semiconductor equipment
- resistance region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
図面は本考案の一実施例を示し、第１図は平面図、第２
図は第１図の■−■線断面図、第３図は第１図の■−■
線断面図である。第４図は本考案の他の実施例を示す断
面図である。
１・・・半導体基板、２・・・エピタキシャル層、５・
・・抵抗領域、６．・・・第１の絶縁層、８・・・第２
の絶縁層、９・・・配線。The drawings show one embodiment of the present invention, and the first figure is a plan view and the second figure is a plan view.
The figure is a sectional view taken along the line ■-■ in Figure 1, and Figure 3 is a cross-sectional view taken along the line ■-■ in Figure 1.
FIG. FIG. 4 is a sectional view showing another embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Epitaxial layer, 5...
...Resistance region, 6. ...first insulating layer, 8...second
insulating layer, 9... wiring.
Claims (1)
電型のエピタキシャル層と、このエピタキシャル層に形
成された一導電型の抵抗領域と、前記エビタキシャ、用
層上に設けた第１の絶縁層と、この第１の絶縁層上に設
けた多層配線の層間絶縁を行う第２の絶縁層とを備えた
半導体装置であって、少なくとも前記抵抗領域上を交差
する配線を前記第２の絶縁層上に配設したことを特徴と
する半導体装置。A semiconductor substrate of one conductivity type, an epitaxial layer of an opposite conductivity type provided on this substrate, a resistance region of one conductivity type formed in this epitaxial layer, and a first semiconductor substrate provided on the epitaxial layer. A semiconductor device comprising an insulating layer and a second insulating layer provided on the first insulating layer for performing interlayer insulation of multilayer wiring, wherein at least the wiring crossing over the resistance region is connected to the second insulating layer. A semiconductor device characterized by being disposed on an insulating layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5024284U JPS60160557U (en) | 1984-04-04 | 1984-04-04 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5024284U JPS60160557U (en) | 1984-04-04 | 1984-04-04 | semiconductor equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60160557U true JPS60160557U (en) | 1985-10-25 |
Family
ID=30568190
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5024284U Pending JPS60160557U (en) | 1984-04-04 | 1984-04-04 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60160557U (en) |
-
1984
- 1984-04-04 JP JP5024284U patent/JPS60160557U/en active Pending
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