JPS60158667A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a MOSFET, in which a short channel effect is difficult to be generated, by making the thickness of an insulator layer inserted under an element thinner than that of a depletion layer at drain voltage in an element into which the insulator layer is not inserted. CONSTITUTION:An oxide film 13 is formed on a P type silicon wafer 12 through a thermal oxidation method. Polycrystalline silicon 14 is deposited, and the polycrystalline silicon 14 is changed into a single crystal through lateral epitaxial technique by CW laser projection. A MOSFET is prepared to the single crystal by using a normal process. B is doped to the silicon layer 17 turned into the single crystal through ion implantation, and P type silicon is formed. A gate oxide film 7 is 25nm thick, a gate electrode 8 consists of high impurity-concentration polycrystalline silicon, and As is doped through ion implantation using the gate electrode 8 as a mask to shape a source region 5 and a drain region 6. The silicon layer 17 changed into the single crystal not used for an element is removed through etching for isolating elements.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The field of application of the present invention is a MOB-LSI that operates at high speed and has an extremely high degree of integration.

[Background of the invention]

There is an increasing demand for higher performance in ultra-large computers, microprocessors, etc. As a method for realizing this, progress has been made to miniaturize elements in LSIs. This results in
It becomes possible to improve the degree of integration and increase the speed of LSI. but,
In recent years, miniaturization of elements alone has become insufficient, and studies have begun on methods of inserting a border layer directly below the element.

So-called 80B (Silicon On 5apI)
hire ) -SOI(5ilicon Qn In
5ulator). With a structure like this,
The parasitic capacitance of the element and wiring is reduced, allowing the element to operate at high speed.

[Purpose of the invention]

When miniaturizing MOS-FET and shortening the channel length,
"Short channel effect" begins to be observed. this is,
When the channel length becomes comparable to the width of the drain depletion layer, the threshold lft4 pressure also changes as the channel length changes. This situation is shown in Figure 1. Region (a) in Figure 1 is the region where the short channel effect occurs. If a MOSFET is manufactured with a channel length where the short channel effect occurs, the channel length may change due to process variations such as over-etching or under-etching the gate electrode. A small variation can cause a large variation in threshold voltage. When manufacturing LSIs, there must be no variation in custom-made elements. Therefore, in order to use minute elements in LSIs, it is essential that short channel effects do not occur within the channel length. However, in a MOSFET in which an insulating layer is inserted directly below the element, a short channel effect is more likely to occur than in a MOSFET in which an insulating layer is not inserted.

This is because the inserted insulating layer disturbs the potential distribution of the drain depletion layer. For this reason, it has been difficult to miniaturize the element. The purpose of the present invention is to solve the above-mentioned conventional problems, to miniaturize a MOSFET in which an insulating layer is inserted directly under an element suitable for high-speed operation, and to develop an LS using the FET.
[Summary of the Invention] The purpose of the present invention is to provide a structure of a MOSFET that enables a large-scale I. If thicker than . The width of the drain depletion layer of a MOSFET having an insulating layer directly below it extends to the thickness of the insulating layer in the depth direction. This is because when a voltage is applied to an insulator, the electric field strength is the same across the entire area of the insulator. This situation is shown in FIG. The equipotential lines 1 under the drain region 6 are arranged at regular intervals in the insulating layer 3 in the depth direction, so that the drain depletion layer width 11 under the drain region 6 is equal to the width of the insulating layer 3.
Consistent with thickness. For comparison, FIG. 3 shows the potential distribution in the longitudinal section of a conventional MOSFET in which no insulating layer is inserted. Comparing FIG. 2 with FIG. 3, it can be seen that the overhang 10 of the drain depletion layer toward the source region 5 is larger in the MOSFET in which an insulating layer is inserted. Under the influence of the drain depletion layer width 11 being widened in the depth direction, the lateral depletion layer width (overhang 10) has also been widened. This overhang lO has the same authority as the channel length 9
Since the short channel effect occurs when the channel length becomes 1, it is understood that the short channel effect occurs even with a relatively long channel length in a MOSFET in which an insulating layer is inserted. On the other hand, FIG. 4 shows the potential distribution in the longitudinal section when the thickness of the insulating layer 3 inserted under the element is thinner than the drain depletion layer width 11 of the conventional element. In such a device, the drain depletion layer crosses the insulating layer 3 under the drain region 6 and leaks to the semiconductor region 2 below. Therefore, the inserted insulator layer 3 has a first-order distribution 1 of the drain depletion layer.
The influence on the MOSFET is almost eliminated, and the overhang 10 of the drain depletion layer toward the source region 5 side is also the same as that of conventional MOSFETs. By forming the layer thinner than the width of the depletion layer under the drain pressure of an element without inserting an insulating layer, the short channel effect is difficult to occur. A MOSFET with an insulating layer inserted can be obtained.

[Embodiments of the invention]

The substrate insulating layer thickness is MOS with no insulating layer inserted.
We fabricated a device that was thicker than the width of the drain depletion layer under the drain bias of the FET, a device that was the same as the width of the depletion layer, and a device that was thinner than the width of the depletion layer, and measured their "threshold [normal pressure - channel length characteristics]" . Source/drain junction depth is 0.35μ
m, and the impurity concentration Fi1016an- of the active region 2 is
It is 3. At this time, the drain depletion layer width is 0.35μI
It is about n. Therefore, the insulator layer thickness is 2
．． They were selected to be 45 μm, 0.35 μin, and 0.05 μm.

Hereinafter, practical examples of the present invention will be explained in detail with reference to FIGS. 5 to 7.

An oxide film 13 is formed on a p-type silicon wafer 12 with a specific resistance of about 10 Ωcm by a thermal dredging method.At this time, by changing the oxidation time, the oxide film thickness is 2.45μIn and 0.35T.
Three types of wafers are prepared: tm and 0.05 μIn. Then, a part of the oxide film is removed using normal photolithography. Next, polycrystalline silicon 14 is 0.35μ
This is deposited and made into a single crystal by groove direction epitaxy technology using CW laser irradiation 15 and scanning 16 (FIG. 5). A MOSFET is manufactured using a normal process (
Figure 6). The monocrystalline silicon layer 17 is doped with B by ion implantation, and the p
Use mold silicon. Game) If film 7 thickness is 25 nm
The gate electrode 8 is made of polycrystalline silicon with high impurity concentration, and is doped with As by ion implantation using this as a mask.

Source area 5. A drain region 6 is formed. At this time, the impurity concentration is 10"Crn-". Next, for isolation between elements, a single crystal silicon layer 1 that was not used in the element
7 was removed by etching (Fig. 7). Manufactured with a gate width of 15 μm, and channel lengths of 0.8 μm and 1.3 μm.
2 μm and 4 μm were made. FIG. 8 shows the measurement results of the threshold voltages of these elements. The thickness of the insulating film 13 inserted with the measurement result 18 indicated by △ in the figure is 0.05μ
For the elements of m, mark 19 is the one with the insulating film thickness of 0.35 μm, and circle mark 20 is the one with the insulating film thickness of 2.45 μm. In devices with insulating layer 13 thickness of 0.05 μm and 0.35 μm, the short channel effect does not occur much even if the channel length is 1.3 μm; on the other hand, when the insulating layer 13 thickness is 2.4 μm
It can be seen that in a 5 μm element, the short channel effect is significant around a channel length of 1.3 μm.

〔Effect of the invention〕

As can be seen from the above description, according to the present invention.

MOS that operates in a short channel with an insulating layer directly below the element
It is now possible to manufacture FETs, and ultra-high speed and ultra-high integration LSI
The possibility of realization has increased.

[Brief explanation of the drawing]

Figure 1 is a conceptual diagram of the short channel effect, Figure 2 is a longitudinal cross-sectional view and potential distribution diagram of a MOSFET in which an insulating layer thicker than the width of the drain depletion layer is inserted directly under the element, and Figure 3 is a diagram of the insulating layer. This is a longitudinal cross-sectional view and potential distribution diagram of a conventional MOSFET in which the metal is not inserted under the element. Figure 4 is a vertical cross-sectional view and potential distribution diagram of a MOSFET in which an insulator layer thinner than the width of the drain depletion layer is inserted directly below the device, and Figure 5 is a monocrystalline silicon layer formed on the insulator layer by lateral epitaxial growth. Figure 6 is a vertical cross-sectional view of a MOSFET formed on silicon on an insulating layer, and Figure 7 is a vertical cross-sectional view of a MOSFET formed on silicon on an insulating layer, and Figure 7 shows isolation between elements by removing silicon on an insulating layer other than the element area. FIG. 8, which is a vertical cross-sectional view, shows the threshold voltage and channel length characteristics of the MOSFET manufactured in this example, in which an insulating layer is inserted directly below. l... etc. (position line, 2... semiconductor layer, 3... insulator layer, 5... °° source region, 6... drain region, 7...
... Gate oxide film 8... Gate voltage coverage, 9... Channel length, 1o... Drain depletion layer overhang to source region, 11... Drain depletion layer width below drain region, 1
2... Silicon wafer, 13... Silicon dioxide,
14...Polycrystalline silicon, 15...CW argon laser irradiation, 16. Paralaser scan direction, 17... Single crystallized deposited silicon, 18... Insulator layer thickness that is inserted 0.05μm MO8FET+7)
"Threshold N pressure - channel length" characteristic, 19...Inserted insulator layer thickness is 0.35 μrrl) MOS F
"Threshold voltage-channel length" characteristics of ET, 20...
MO with an inserted insulator layer thickness of 2.45μ+r+
ll of SFET. 1 Figure ■ Z Figure 3 100 4 Figure 5 Figure 3 0 1234 + Yaoru OI 771 no

Claims (1)

[Claims] 1. A semiconductor device comprising a MOB-FET in which a dielectric material having a thickness equal to or less than the width of the drain depletion layer under bias is located directly under at least one of the drain and source. 2. A structure in which an insulating film is formed entirely or partially on one or both sides of a semiconductor sea urchin, and a MOB-FET is formed in the region where the insulating film is buried under the semiconductor deposited on it. In the MOB-FET, the thickness of the insulating film is less than the depletion layer width in the drain depth direction under the drain bias of the MOB-FET fabricated in the semiconductor wafer with the impurity concentration of the active region of the MOB-FBT. A semiconductor device according to claim 1, characterized in that the semiconductor device has: 3. A structure in which an insulating film is partially formed on one or both sides of a semiconductor, and a MOB-FET is formed on the semiconductor deposited on top of it so that only the drain is on the insulating film. In this case, the thickness of the insulating film is the same as that of the MO
Claims characterized by having a MOB-FET whose impurity concentration in the active region of the MOB-FET is less than or equal to the width of the depletion layer in the drain depth direction under the drain bias of the MOB-FET manufactured in the semiconductor urchin I. Semiconductor device 0 described in item 1