JPS60154567A - Manufacture of insulated gate type field-effect transistor - Google Patents

Abstract

PURPOSE:To form source-drain regions in a self-alignment manner by an Al gate electrode by executing the introduction of an impurity and activation to the source-drain regions by using plasma. CONSTITUTION:A field oxide film 2 is formed to a field section in an N type Si substrate 1 and a gate oxide film 5 in an element region, a gate electrode 6 consisting of Al is deposited, and the film 5 is left only under the electrode 6 through etching using the electrode 6 as a mask. Shallow boron implanting regions 9 are shaped to sections to which source-drain regions must be formed while using the electrode 6 and the film 2 as masks by exposing the surface of the substrate 1 to plasma containing boron ions. An implanting impurity to the regions is activated at a low temperature by exposing the substrate 1 to Ar gas plasma, thus forming the source-drain regions 41, 42. According to the manufacture, the source-drain regions can be shaped in a self-alignment manner by the Al gate electrode because the treatment of impurity introduction and activation to the regions 41, 42 can be executed at the low temperature.

Description

[Detailed description of the invention] [Technical field to which the invention pertains] The present invention provides source and drain regions with metal gate electrodes.
z-y2hL-1 6th year old ΔI11/-IIr Yoshij9
mJaAJ type field effect transistor (hereinafter MISFK)
(denoted as T).

[Prior art and its problems]

Conventionally, this type of technology has generally been based on a manufacturing method as shown in FIGS. 1(a) to 1(d).

That is, FIG. 1 (,) shows the step of selectively covering the surface of the silicon substrate 1 except the element formation region with a thick field oxide film 2, and FIG. 1 (+,) shows the process of chemical vapor deposition (CVD).
A CVD oxide film 3 is layered in the area where the siggate electrode is to be formed by depositing an oxide film (described as method) and selective etching of the OVD oxide film, and then thermal diffusion method or ion implantation is performed using the field oxide film 2 and CVD oxide film 3 as a mask. Step of forming source and drain regions 41 and 42 by method, FIG.
) is a step in which the gate electrode, source, and drain electrode forming regions of the CVD oxide film 3 are etched away, and then the gate oxide film 5 is grown by a thermal oxidation method; FIG.

These steps are a step of opening a contact hole in the drain electrode forming region and forming a gate electrode 6 and a gate electrode 6 using aluminum or an alloy layer mainly composed of aluminum, and a step of depositing a passivation film 8. In the above method, since the melting point of aluminum is as low as 660° C., the aluminum gate electrode is formed after the source and drain region diffusion process. In this case, when forming the gate electrode, it is necessary to take into account the margin of mask alignment accuracy, which has the disadvantage that the gate electrode and the source and drain regions overlap greatly, that is, the parasitic capacitance increases. Therefore, in order to reduce the above-mentioned parasitic capacitance, a method of forming self-aligned source and drain regions using polycrystalline silicon gate electrodes is often used. However, with this method, a new problem has arisen: the resistance of the polycrystalline silicon wiring increases as the line width becomes finer, and the operating speed does not improve even though the parasitic capacitance is reduced.

[Purpose of the invention] The present invention eliminates the above drawbacks and reduces the parasitic capacitance.

It is an object of the present invention to provide a method for manufacturing an M-type ICT that enables formation of self-aligned source and drain regions using an aluminum gate electrode in order to reduce wiring resistance.

[Key points of the invention]

According to the present invention, an impurity is added to a gate electrode made of a metal provided from one main surface of a semiconductor substrate of a conductivity type via an insulating film and a region not covered with a field insulating film, and a source of a conductivity type of another conductivity type is added. In a method for forming a drain region, a gate electrode and a field insulating film are formed on the -1 surface of a semiconductor substrate, pressure is removed, and impurities are introduced from the main surface by exposing both of them to plasma containing impurities as a mask. , the source in a self-aligned manner by activating it by exposing its major surface to a gas plasma,
This forms a drain region.

[Embodiments of the invention]

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIGS. 2(a) to 2(d) are cross-sectional views showing the steps of an embodiment of the present invention, and are an example in which aluminum is used as the gate metal. First, Fig. 2(a) shows an n-type silicon substrate l.
After forming a thick oxide film 2 of approximately 1 μm in the field area and a gate oxide M5 of 300× in the element region, a gate electrode 6 made of aluminum is deposited.
This is a step in which the silicate oxide film 5 is left only under the gate electrode 6 by etching using as a mask. The thickness of the aluminum gate electrode 6 is ao and ooi. The steps shown in FIG. 2(b) and (0) are the steps to which the present invention is applied;
In b), by exposing the surface of the semiconductor substrate 1 to plasma containing boron ions, using the gate electrode 6 and the field oxide film 2 as masks, a shallower unimplanted region is formed in the portions to be the source and drain regions. form 9.

Specifically, a semiconductor substrate l is placed on a cathode plate at 300°C, B2Ha gas diluted with hydrogen to looOppm is introduced into the chamber, and plasma is generated at a gas pressure of 2 Torr and a DC applied voltage of 500 V, and the surface Inject boron. Injection time of 1 minute, surface concentration l~QXIOcm
, a shallow injection layer 9 with a depth of 0.1 μm is formed. Next, introduce argon gas into the same chamber.
By generating and exposing the surface of the semi-integrated substrate to it, the implanted impurities are activated at a low temperature to form source and drain regions 41 and 42.The temperature of the substrate is as low as about 300°C. The rounding junction depth remains at 01 μm.

Furthermore, an oxide film having a thickness of J) 500X is deposited as the glabellar insulating film 10 by the OVD method (FIG. 2(C)). FIG. 2(d) shows a well-known process in which contact holes are formed above the source and drain regions 41 and 42, and a metal wiring, for example, an aluminum-silicon alloy film wiring with a thickness of 500X is formed, and then a 1 μm thick aluminum-silicon alloy film wiring is formed. This is a process of passivating with a thick plasma nitride film 8.

〔Effect of the invention〕

In the present invention, plasma is used to introduce impurities into the source and drain regions of the MFC SF'FiT and to activate them, and these processes can be carried out at low temperatures, making it an effective method for reducing parasitic capacitance. This self-aligned impurity introduction can be applied even to gates made of low-melting-point metals such as aluminum, and combined with aluminum's low resistance, it has become possible to significantly improve operating speed. Furthermore, since the depth of the source and drain regions can be made shallow to about 0.1 .mu.m, two effects can be obtained: a further reduction in parasitic capacitance and prevention of the short channel effect. In addition, according to the present invention, there is no need to use complicated and expensive equipment such as an ion implanter, and impurity implantation and activation can be performed continuously in the same chamber, so high concentration impurity can be introduced in a short time. can be done efficiently. It goes without saying that not only aluminum but also various other metals can be used for the gate electrode.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing the manufacturing process of a conventional insulated aluminum gate a field effect transistor, and FIG. 2 is a sectional view showing the process of an embodiment of the present invention. l...Silicon substrate, 2...Field oxide film, 5
... Gate oxide film, 6 ... Aluminum gate electrode, 9 ... Impurity implantation region, 41, 42 ... Source,
drain area. 4142 Figure 1 4142 Figure 2

Claims (1)

[Claims] 1) Impurities are added to the gate electrode made of metal provided through the insulating film from the -1 surface of the -1 conductivity type semiconductor substrate and the region not covered by the field insulating film, and the source and drain regions of the other conductivity type are added. In the forming method, after providing a gate electrode and a field insulating film on one main surface of a semiconductor substrate, impurities are removed from the main surface by exposing the gate electrode and field insulating film to plasma containing impurities using the gate electrode and field insulating film as a mask. 1. A method for manufacturing an insulated gate field effect transistor, comprising introducing impurities and activating the introduced impurities by exposing the main surface to gas plasma.