KR20000045854A - Method of forming silicide layer of semiconductor device - Google Patents
Method of forming silicide layer of semiconductor device Download PDFInfo
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- KR20000045854A KR20000045854A KR1019980062450A KR19980062450A KR20000045854A KR 20000045854 A KR20000045854 A KR 20000045854A KR 1019980062450 A KR1019980062450 A KR 1019980062450A KR 19980062450 A KR19980062450 A KR 19980062450A KR 20000045854 A KR20000045854 A KR 20000045854A
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- South Korea
- Prior art keywords
- layer
- oxide film
- forming
- salicide
- gate electrode
- Prior art date
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- 238000000034 method Methods 0.000 title claims abstract description 55
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 229910021332 silicide Inorganic materials 0.000 title abstract 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title abstract 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 21
- 229920005591 polysilicon Polymers 0.000 claims abstract description 21
- 238000005530 etching Methods 0.000 claims abstract description 17
- 125000006850 spacer group Chemical group 0.000 claims abstract description 12
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 10
- 239000000956 alloy Substances 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 150000002500 ions Chemical class 0.000 claims abstract description 4
- 238000010438 heat treatment Methods 0.000 claims description 25
- 238000000151 deposition Methods 0.000 claims description 14
- 230000008021 deposition Effects 0.000 claims description 9
- 239000000203 mixture Substances 0.000 claims description 7
- 229910052759 nickel Inorganic materials 0.000 claims description 6
- 238000004544 sputter deposition Methods 0.000 claims description 6
- 238000010030 laminating Methods 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000005240 physical vapour deposition Methods 0.000 claims 1
- 238000007669 thermal treatment Methods 0.000 claims 1
- 230000000873 masking effect Effects 0.000 abstract description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 30
- 229910019001 CoSi Inorganic materials 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 229910017052 cobalt Inorganic materials 0.000 description 3
- 239000010941 cobalt Substances 0.000 description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 3
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 230000000593 degrading effect Effects 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
Abstract
Description
본 발명은 게이트전극에서 살리사이드층 형성방법에 관한 것으로서, 특히, 반도체기판 상에 게이트산화막 및 폴리실리콘층을 적층한 후 식각을 하여 게이트전극을 형성하고, 이 게이트전극에 니켈층과 코발트층을 순차적으로 적층하여 제1차 열처리공정, 선택에칭공정 및 제2차열처리공정을 거치면서 게이트전극의 폴리실리콘층과 정션영역에 Co1-xNixSi2으로 된 합금살리사이드층을 형성하므로 누설전류를 감소시킬 뿐만아니라 공정을 간소화하도록 하는 반도체소자의 살리사이드층 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a salicide layer in a gate electrode. In particular, a gate electrode is formed by laminating a gate oxide film and a polysilicon layer on a semiconductor substrate, and forming a gate electrode, and forming a nickel layer and a cobalt layer on the gate electrode. Lamination is performed sequentially to form an alloy salicide layer of Co 1-x Ni x Si 2 in the polysilicon layer and the junction region of the gate electrode during the first heat treatment process, the selective etching process and the second heat treatment process. The present invention relates to a method of forming a salicide layer of a semiconductor device that not only reduces current but also simplifies the process.
일반적으로, 트랜지스터의 소오스/드레인영역 콘택재료 및 게이트메탈로서 동시에 CoSi2층을 형성하기 위하여서는 여러 가지 방법이 있으나 대표적으로 적용되는 2가지 방법을 살펴 보도록 한다.In general, there are various methods for simultaneously forming a CoSi 2 layer as a source / drain region contact material and a gate metal of a transistor.
첫번째 방법은 Co단일층을 증착하여 소오스/드레인 지역의 실리콘과 게이트부분의 도핑된 폴리실리콘층과 동시에 반응하여 CoSi2층을 형성하도록 하는 방법이 있다.The first method involves depositing a single Co layer to simultaneously react with silicon in the source / drain regions and a doped polysilicon layer in the gate portion to form a CoSi 2 layer.
그리고, 두 번째 방법은 Co/Ti이중층을 이용하는 방법으로서, 이 방법은 소오스/드레인의 정션부분에 중간층으로서 Ti층을 사용하도록 하고, Co층의 플럭스량을 조절하여 CoSi2층을 에피성장으로 형성하도록 한다.The second method uses a Co / Ti double layer, which uses a Ti layer as an intermediate layer in the junction portion of the source / drain, and controls the flux of the Co layer to form a CoSi 2 layer as epitaxial growth. Do it.
그러나, 상기한 첫 번째 방법은, 소오스/드레인영역의 정션지역(Junction Region)의 CoSi2층이 다결정층으로 자라기 때문에 얕은 정션(Shallow Junction)에 있어서, CoSi2층의 두께조절이 어렵고, CoSi2층과 Si사이의 계면이 거칠어지는 문제점을 지니고 있었다.However, it is difficult to the first method described above, the shallow junction (Shallow Junction) method, CoSi thickness control of the second layer in because of CoSi 2 layers in the junction area of the source / drain regions (Junction Region) to grow into a polycrystalline layer, CoSi 2 The interface between the layer and Si was rough.
또한, 두 번째 방법은 TiCoSi층이 삼상층으로 생성됨으로 인한 선택적 에칭방법이 복잡하고 게이트부분의 스페이서막인 사이드월 산화막(Side Wall Oxide) 밑부분에서 Si의 확산으로 인한 공극(Void)이 형성되어 소자의 특성을 저하시키는 문제점을 지니고 있었다.In the second method, the selective etching method is complicated by the formation of the TiCoSi layer as a three-phase layer, and voids due to the diffusion of Si are formed at the bottom of the side wall oxide film, which is a spacer film of the gate part. It had a problem of degrading the characteristics of the device.
본 발명은 이러한 점을 감안하여 안출한 것으로서, 반도체기판 상에 게이트산화막 및 폴리실리콘층을 적층한 후 식각을 하여 게이트전극을 형성하고, 이 게이트전극에 니켈층과 코발트층을 순차적으로 적층하여 제1차 열처리공정, 선택에칭공정 및 제2차열처리공정을 거치면서 게이트전극의 폴리실리콘층과 정션영역에 Co1-xNixSi2으로 된 합금살리사이드층을 형성하므로 누설전류를 감소시킬 뿐만아니라 공정을 간소화하도록 하는 것이 목적이다.SUMMARY OF THE INVENTION The present invention has been made in view of this point, and a gate oxide film and a polysilicon layer are laminated on a semiconductor substrate and then etched to form a gate electrode, and a nickel layer and a cobalt layer are sequentially stacked on the gate electrode. Through the first heat treatment process, selective etching process and second heat treatment process, an alloy salicide layer of Co 1-x Ni x Si 2 is formed in the polysilicon layer and the junction region of the gate electrode, thereby reducing leakage current. The aim is to simplify the process.
도 1 내지 도 6은 본 발명에 따른 반도체소자에서 게이트전극의 살리사이드층을 형성하는 방법을 순차적으로 보인 도면이다.1 to 6 are views sequentially showing a method of forming a salicide layer of a gate electrode in a semiconductor device according to the present invention.
-도면의 주요부분에 대한 부호의 설명-Explanation of symbols on the main parts of the drawing
10 : 반도체기판 20 : 필드산화막10: semiconductor substrate 20: field oxide film
30 : 게이트산화막 40 : 하부폴리실리콘층30 gate oxide film 40 lower polysilicon layer
50 : 마스크산화막 60 : 감광막50 mask oxide film 60 photosensitive film
70 : PECVD산화막 80 : 감광막70 PECVD oxide film 80 photosensitive film
90 : 금속층 95 : 스페이서막90 metal layer 95 spacer film
90' : 살리사이드층 100 : 소오스/드레인영역90 ': salicide layer 100: source / drain region
A : 게이트전극A: gate electrode
이러한 목적은 필드산화막이 형성된 반도체기판 상에 게이트산화막 및 폴리실리콘층을 순차적으로 적층한 후 식각으로 게이트전극을 형성하는 단계와; 상기 결과물 상에 산화막을 적층하여 선택 식각으로 게이트전극의 측면부에 스페이서막을 형성한 후 정션영역에 이온을 주입하여 소오스/드레인영역을 형성하는 단계와;상기 결과물 상에 Ni층/Co층을 연속하여 적층하는 단계와; 상기 Ni층/Co층을 제1차 열처리공정을 진행하여 정션영역과 폴리실리콘층 상에 합금살리사이드층인 Co1-xNixSi2층을 형성하는 단계와; 상기 단계 후에 스페이서막과 필드산화막 상에 형성되어 있는 Co 및 Ni의 혼합층을 선택식각으로 제거하는 단계와; 상기 결과물에 제2차 열처리공정을 진행하여 합금살리사이드층인 Co1-xNixSi2층 보다 안정화시키도록 하는 단계를 포함하여 이루어진 반도체소자의 살리사이드층 형성방법을 제공함으로써 달성된다.The object is to sequentially form a gate oxide film and a polysilicon layer on a semiconductor substrate on which a field oxide film is formed, and then form a gate electrode by etching; Stacking an oxide film on the resultant to form a spacer layer on a side surface of the gate electrode by selective etching, and implanting ions into the junction region to form a source / drain region; and subsequently forming a Ni / Co layer on the resultant Laminating; Performing a first heat treatment process on the Ni layer / Co layer to form a Co 1-x Ni x Si 2 layer as an alloy salicide layer on the junction region and the polysilicon layer; Selectively removing the mixed layers of Co and Ni formed on the spacer film and the field oxide film after the step; It is achieved by providing a method of forming a salicide layer of a semiconductor device comprising the step of performing a second heat treatment process to the resultant to stabilize than an alloy salicide layer Co 1-x Ni x Si 2 layer.
그리고, 상기 폴리실리콘층은 500 ∼ 650℃의 온도범위와 80torr이하의 증착압력으로 진행하고, 증착소오스가스는 PH3와 SiH4가스를 사용하도록 한다.In addition, the polysilicon layer proceeds at a temperature range of 500 to 650 ° C. and a deposition pressure of 80 torr or less, and the deposition source gas uses PH 3 and SiH 4 gas.
상기 폴리실리콘층 상에 적층되는 Ni층/Co층은 CVD(Chemical Vapor Deposition) 혹은 PVD(Pressure Vapor Deposition)법으로 증착하도록 하고, 이 Co층 : Ni층의 증착비율은 1 : 0.05 ∼ 0.6정도로 하는 것이 바람직하다.The Ni layer / Co layer laminated on the polysilicon layer is deposited by CVD (Chemical Vapor Deposition) or PVD (Pressure Vapor Deposition) method, and the deposition ratio of this Co layer: Ni layer is about 1: 0.05 to 0.6. It is preferable.
그리고, 상기 제1차 열처리공정은 급속열처리공정(RTP; Rapid Thermal Processing)으로 하고, 400 ∼ 850 ℃의 온도범위에서 진행하거나 또는, 제1차 열처리공정은 확산로(Furnace)에서 하고, 400 ∼ 800℃의 온도범위에서 진행하도록 한다.The first heat treatment step may be a rapid thermal processing (RTP) process, and may be performed in a temperature range of 400 to 850 ° C., or the first heat treatment step may be performed in a diffusion furnace, and the 400 to Proceed to the temperature range of 800 ℃.
그리고, 상기 선택식각공정은 SPM용액, BOE용액 또는 HF용액으로 진행하도록 한다.Then, the selective etching process is to proceed to SPM solution, BOE solution or HF solution.
그리고, 상기 제2차 열처리공정은 급속열처리공정으로 하고, 550 ∼ 900℃의 온도범위에서 진행하거나 또는, 제2차 열처리공정은 확산로에서 하고, 550 ∼ 850℃의 온도범위에서 진행하도록 한다.The second heat treatment step may be a rapid heat treatment step, and may be performed at a temperature range of 550 to 900 ° C., or the second heat treatment step may be performed at a diffusion furnace, and may be performed at a temperature range of 550 to 850 ° C.
한편, 상기 Ni층/Co층을 증착하는 대신에 Co1-XNix의 스퍼링(Supttering) 혼합물을 타겟(Target)으로 이용하여 PVD방법으로 증착하고, 급속열처리공정으로 Co1-xNixSi2층을 형성할 수도 있다.Meanwhile, instead of depositing the Ni layer / Co layer, a sputtering mixture of Co 1-X Ni x is used as a target and deposited by PVD method, and Co 1-x Ni x is a rapid heat treatment process. Si 2 layers may also be formed.
이때, 이 Co1-XNix스퍼링 혼합물 타겟의 Ni비율의 값은 0.05 ∼ 0.6 으로 하고, 급속열처리공정은 500 ∼ 900℃의 온도범위로 진행하도록 한다.At this time, the value of the Ni ratio of this Co 1-X Ni x sputtering mixture target shall be 0.05-0.6, and a rapid heat processing process shall advance to the temperature range of 500-900 degreeC.
이하, 첨부한 도면에 의거하여 본 발명의 일실시예에 대하여 상세히 살펴보도록 한다.Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 도 6은 본 발명에 따른 반도체소자에서 게이트전극의 살리사이드층을 형성하는 방법을 순차적으로 보인 도면이다.1 to 6 are views sequentially showing a method of forming a salicide layer of a gate electrode in a semiconductor device according to the present invention.
도 1은 상기 필드산화막(20)이 형성된 반도체기판(10) 상에 게이트산화막(30) 및 폴리실리콘층(40)을 순차적으로 적층한 상태를 도시하고 있다.FIG. 1 illustrates a state in which the gate oxide film 30 and the polysilicon layer 40 are sequentially stacked on the semiconductor substrate 10 on which the field oxide film 20 is formed.
이때, 상기 폴리실리콘층(40)은 500 ∼ 650℃의 온도범위와 80torr이하의 증착압력으로 진행하고, 증착소오스가스는 PH3와 SiH4가스를 사용하여 증착하도록 한다.At this time, the polysilicon layer 40 is carried out at a temperature range of 500 ~ 650 ℃ and a deposition pressure of less than 80torr, the deposition source gas is to be deposited using PH 3 and SiH 4 gas.
그리고, 도 2는 상기 결과물을 마스킹식각으로 에칭하여 게이트전극(A)을 형성한 후에 게이트전극(A)의 측면에 스페이서를 형성하기 위하여 산화막(50)을 적층한 상태를 도시하고 있다.2 illustrates a state in which the oxide film 50 is stacked to form a spacer on the side of the gate electrode A after the gate electrode A is formed by etching the resultant by masking etching.
도 3는 상기 결과물 상에 산화막(50)을 적층하여 선택식각(Slectivity Etch)으로 게이트전극(A)의 측면부에 스페이서막(60)을 형성한 후 정션영역에 이온을 주입하여 소오스/드레인영역(70)을 형성하는 상태를 도시하고 있다.FIG. 3 shows the spacer layer 60 formed on the side surface of the gate electrode A by the selective etching by stacking the oxide film 50 on the resultant, and then implanting ions into the junction region. 70 shows a state of forming.
도 4는 상기 결과물 상에 Ni층(80)/Co층(90)을 연속하여 적층하는 상태를 도시하고 있다.4 shows a state in which the Ni layer 80 / Co layer 90 is successively laminated on the resultant product.
상기 Ni층(80)/Co층(90)은 CVD 혹은 PVD법으로 증착하도록 하고, Co층(90) : Ni층(80)의 증착비율은 1 : 0.05 ∼ 0.6정도로 하는 것이 바람직하다.The Ni layer 80 / Co layer 90 is preferably deposited by CVD or PVD, and the deposition ratio of the Co layer 90: Ni layer 80 is preferably about 0.05 to 0.6.
도 5는 상기 Ni층(80)/Co층(90)을 제1차 열처리공정을 진행하여 정션영역과 폴리실리콘층(40)상에 합금살리사이드층인 Co1-xNixSi2층(100)을 형성하도록 하고, 스페이서막(60)과 필드산화막(20)에는 Ni층과 Co층의 혼합층(100')이 형성된 상태를 도시하고 있다.FIG. 5 illustrates a Co 1-x Ni x Si 2 layer (alloyed salicide layer) on the junction region and the polysilicon layer 40 by performing a first heat treatment process on the Ni layer 80 / Co layer 90. 100 and a mixed layer 100 'of a Ni layer and a Co layer are formed in the spacer film 60 and the field oxide film 20.
이때, 상기 제1차 열처리공정은 급속열처리공정으로 하고, 400 ∼ 850℃의 온도범위에서 진행하거나 또는, 제1차 열처리공정은 확산로에서 하고, 400 ∼ 800℃의 온도범위에서 진행하도록 한다.At this time, the first heat treatment process is a rapid heat treatment process, and proceeds in a temperature range of 400 ~ 850 ℃, or the first heat treatment process is carried out in a diffusion furnace, and proceeds to a temperature range of 400 ~ 800 ℃.
그리고, 도 6은 상기 단계 후에 스페이서막(60)과 필드산화막(20) 상에 형성되어 있는 Co 및 Ni의 혼합층(100')을 선택식각으로 제거한 후의 상태를 도시하고 있다.6 shows a state after the etching layer removes the mixed layer 100 'of Co and Ni formed on the spacer film 60 and the field oxide film 20 after the above step.
이때, 상기 선택식각공정은 SPM용액(H2SO4+ H2O2의 혼합용액), BOE용액 또는 HF용액으로 진행하도록 한다.At this time, the selective etching process is to proceed to SPM solution (mixture of H 2 SO 4 + H 2 O 2 ), BOE solution or HF solution.
그리고, 상기 결과물에 제2차 열처리공정을 진행하여 합금살리사이드층인 Co1-xNixSi2층 보다 안정화시키도록 한다.Then, the resultant is subjected to a second heat treatment process to stabilize the Co 1-x Ni x Si 2 layer of the alloy salicide layer.
상기 제2차 열처리공정은 급속열처리공정으로 하고, 550 ∼ 900℃의 온도범위에서 진행하거나 혹은, 제2차 열처리공정은 확산로에서 하고, 550 ∼ 850℃의 온도범위에서 진행하도록 한다.The second heat treatment step is a rapid heat treatment step, and proceeds at a temperature range of 550 ~ 900 ℃, or the second heat treatment step is carried out in a diffusion furnace, and proceeds to a temperature range of 550 ~ 850 ℃.
한편, 상기 Ni층(80)/Co층(90)을 증착하는 대신에 Co1-XNix의 스퍼링 혼합물을 타겟으로 이용하여 PVD 방법으로 증착하고, 급속열처리공정으로 500 ∼ 900℃의 온도범위로 Co1-xNixSi2층(100)을 형성하도록 하며, 상기 Co1-XNix스퍼링 혼합물 타겟의 Ni층 비율의 값은 0.05 ∼ 0.6 정도가 되도록 하는 약간 변형된 방법을 이용할 수 있다.Meanwhile, instead of depositing the Ni layer 80 / Co layer 90, a sputtering mixture of Co 1-X Ni x is used as a target to be deposited by PVD method, and a rapid heat treatment is performed at a temperature of 500 to 900 ° C. In order to form a Co 1-x Ni x Si 2 layer (100) in the range, and using a slightly modified method such that the value of the Ni layer ratio of the Co 1-X Ni x sputtering mixture target is about 0.05 to 0.6 Can be.
따라서, 상기한 바와 같이 본 발명에 따른 반도체소자의 살리사이드 형성방법을 이용하게 되면, 반도체기판 상에 게이트산화막 및 폴리실리콘층을 적층한 후 식각하여 게이트전극을 형성하고, 이 게이트전극에 니켈층과 코발트층을 순차적으로 적층하여 제1차 열처리공정, 선택에칭공정 및 제2차 열처리공정을 거치면서 게이트전극의 폴리실리콘층과 정션영역에 Co1-xNixSi2으로 된 합금살리사이드층을 형성하므로 누설전류를 감소시킬 뿐만아니라 공정을 간소화하도록 하는 매우 유용하고 효과적인 발명이다.Therefore, when the salicide forming method of the semiconductor device according to the present invention is used as described above, a gate oxide film and a polysilicon layer are laminated on the semiconductor substrate and then etched to form a gate electrode, and the nickel layer is formed on the gate electrode. And a cobalt layer were sequentially laminated, followed by a first heat treatment process, a selective etching process, and a second heat treatment process, and an alloy salicide layer of Co 1-x Ni x Si 2 in the polysilicon layer and the junction region of the gate electrode. Is a very useful and effective invention that not only reduces leakage current but also simplifies the process.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100457501B1 (en) * | 2001-05-14 | 2004-11-17 | 샤프 가부시키가이샤 | DEVICE INCLUDING AN EPITAXIAL NICKEL SILICIDE ON (100)Si OR STABLE NICKEL SILICIDE ON AMORPHOUS Si AND A METHOD OF FABRICATING THE SAME |
| KR100628253B1 (en) * | 2000-08-09 | 2006-09-27 | 매그나칩 반도체 유한회사 | Method for Forming Self-Aligned Silcide of Semiconductor Device |
| KR100870176B1 (en) * | 2003-06-27 | 2008-11-25 | 삼성전자주식회사 | Nickel alloy salicide process, Methods of fabricating a semiconductor device using the same, nickel alloy silicide layer formed thereby and semiconductor devices fabricated using the same |
| KR101016337B1 (en) * | 2003-07-18 | 2011-02-22 | 매그나칩 반도체 유한회사 | Method of manufacturing a semiconductor device |
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| JPS60213058A (en) * | 1984-04-09 | 1985-10-25 | Agency Of Ind Science & Technol | Structure with silicide film and manufacture thereof |
| NL9100334A (en) * | 1991-02-26 | 1992-09-16 | Philips Nv | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE IN WHICH A SELF-REGISTRATING COBALT OR NICKEL SILICIDE IS FORMED. |
| KR19990018279A (en) * | 1997-08-27 | 1999-03-15 | 윤종용 | MOSFET device for preventing gate-source-drain short caused by salicide and method for manufacturing same |
| US6071782A (en) * | 1998-02-13 | 2000-06-06 | Sharp Laboratories Of America, Inc. | Partial silicidation method to form shallow source/drain junctions |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100628253B1 (en) * | 2000-08-09 | 2006-09-27 | 매그나칩 반도체 유한회사 | Method for Forming Self-Aligned Silcide of Semiconductor Device |
| KR100457501B1 (en) * | 2001-05-14 | 2004-11-17 | 샤프 가부시키가이샤 | DEVICE INCLUDING AN EPITAXIAL NICKEL SILICIDE ON (100)Si OR STABLE NICKEL SILICIDE ON AMORPHOUS Si AND A METHOD OF FABRICATING THE SAME |
| KR100870176B1 (en) * | 2003-06-27 | 2008-11-25 | 삼성전자주식회사 | Nickel alloy salicide process, Methods of fabricating a semiconductor device using the same, nickel alloy silicide layer formed thereby and semiconductor devices fabricated using the same |
| US7781322B2 (en) | 2003-06-27 | 2010-08-24 | Samsung Electronics Co., Ltd. | Nickel alloy salicide transistor structure and method for manufacturing same |
| KR101016337B1 (en) * | 2003-07-18 | 2011-02-22 | 매그나칩 반도체 유한회사 | Method of manufacturing a semiconductor device |
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