JPS60151699A - Pitch converter - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

[Technical Field of the Invention] The present invention is a method for changing the bits of a music signal to match the bits with other musical instruments or voices by returning the bits to restore the change in timbre when a tape recorder is turned fast or slow. This invention relates to a pitch conversion device used when [Technical 11 of the Invention and its Problems] As a method for changing the bits of an audio signal, a method is known in which an audio signal recorded on a tape recorder or the like is reproduced at a speed different from that at the time of recording. However, in this method, the time length changes and the pitch also changes, making it impossible to convert the pitch of the sound in real time. For this reason, recently, pitch conversion devices that use memory elements and are capable of pitch conversion in real time have been developed. FIG. 1 is a circuit block diagram of such a conventional pitch conversion device. This pitch conversion device includes an A/D converter 1 that converts an analog signal that is an input signal into a digital signal, a memory 2 that stores data, an address switch 3 that switches the address of the memory 2, and an address switch Write address counter 4 sends the write address to 3, address switch 3
Read address counter 5 that indicates the read address to
A clock is supplied to the memory controller 6, which performs address switching, write mode, and continuous output mode switching, the A/D converter 1, and the write address counter 4, and a write request is supplied to the memory controller 6. A write clock generator 7, a read clock generator 8 which supplies a clock to a read address counter 5 and a read request to a memory controller 6, and a read clock generator 8 which supplies a clock to a read address counter 5 and a read request to a memory controller 6; It is composed of a block counter 9 that resets the address counter 5, a data latch 10 that latches read data, and a D/A converter 11 that converts the read data supplied from the data latch 10 into analog. In such conventional pitch conversion devices, the input signal is A/
It is converted into a digital signal by the D converter 1 and written into the memory 2. At this time, a sample clock is supplied from the write clock generator 7 to the A/D converter 1, and a clock is also supplied to the write address counter 4, and the address switch 3 switches the address according to the address signal of the write address counter 4. Do the following. Reading is performed at a timing different from the write clock, and the read data is latched at -H in the data latch 10, and then returned to an analog signal through the D/A converter 11 and output. When reading data, a clock signal is supplied from the read clock generator 8 to the read address counter 5, and a latch pulse is supplied to the data latch 10. The read address counter 5 is reset by the block counter 9 every preset block length. The switching control between writing and reading to the memory 2 is performed by the memory controller 6 that receives a write request from the write clock generator 7 and the read clock generator 8 and a read request, and switches the address and write mode. , is performed by switching the read mode. FIG. 2 J5 and FIG. 3 are timing charts illustrating the operation of this pitch conversion device. Figure 2 shows the case where the read clock frequency is lower than the write clock, that is, the pitch is lowered, and Figure 3 shows the case where the read clock frequency is higher than the self-program clock, that is, the pitch is raised. There is. In these figures, (a) shows an input data string, and (b) shows an output data string. Here, the length of the block is required to be several hundred m5 in terms of auditory sense, and since an input signal with a period longer than the block length is not pitch-converted, from this point of view, the longer the block length, the better. However, if the block length is long, the memory capacity of the memory 2 increases, and the length of the lost data that disappears when performing a predetermined pitch conversion also becomes long, so that the lost sound becomes perceptibly recognizable. For this reason, the length of the block is usually about several 100 m5. When lowering the pitch using this pitch conversion device,
As shown in FIG. 2, data DI+D2 is written into the memory at the frequency of the write clock. On the other hand, if this data is not read, the frequency of the read clock will be lower than that of the output clock, so the data output by the end of the block will be the (DI) portion and (D
The data in part 2) cannot be read because the read address counter is reset for each block. However, this portion of data D2 will be lost block by block. Therefore, in this case, the pitch decreases in the same way as when the tape recorder is turned N times, and the read data catches up with the written data for each block, so the overall time does not increase, and the pitch is converted in real time. will be carried out. When increasing the pitch shown in FIG. 3, the frequency of the read clock increases, so the read address is reset in the middle of the block. That is, reading is performed from the D3 portion of the previous data, and the (D3) and (D4) portions are read before the next block is reset. That is, the portion <03) is read out redundantly before and after reset. Therefore, in a block, the bit is raised in the same way as a tape recorder is turned on quickly, and conversion is performed in real time. By the way, in such a conventional pitch conversion device, the fourth
As shown in the figure, a discontinuous portion X occurs in the audio signal S at the joint between the blocks. However, since the resetting of the read address counter 5 is performed regardless of the contents of the signal, it is almost impossible to obtain continuity of the signal stochastically. Therefore, this discontinuous portion However, it has the disadvantage that it is often very harsh on the ears, making it difficult to hear the content, and often gives an unpleasant acoustic sensation. [Object of the Invention] The present invention has been made in order to eliminate such conventional drawbacks, and an object of the present invention is to provide a pitch conversion device that eliminates noise caused by discontinuity of sounds in each block and can obtain natural sounds. purpose. [Summary of the Invention] As shown in FIG. 5, the pitch conversion device of the present invention inputs input signals (
B,) sequentially loads data at a predetermined timing while repeating reset with a preset block length. The data written in this storage means (A>) is read out to two systems of successive means (C) which sequentially read the data at different timings from the input means while repeating reset with a block length equal to the block length. System data retention means (D)
is maintained. One of the data held in the data holding means (D) is selected by the data switching means (E) and output. The zero cross detection means (F) has two systems, and detects zero crosses that cross a value corresponding to zero V in the read data for each block length, and determines the polarity of the crosses. Regardless of which polarity side it crosses, after that, only when it crosses from the same polarity side, the readout of the reading means on the detected side is stopped,
Then, when the other side detects the data switching means (E
) sends a switching signal to The data switching means (E) outputs only the data read by either one of the successive output means r(C) based on this switching (fi). [Embodiment of the Invention] An embodiment of the present invention will be described below. This will be explained with reference to the drawings. Fig. 6 is a circuit block diagram of an embodiment of the present invention. In Fig. 6, parts common to Fig. 1 are designated by the same reference numerals fl. This embodiment The pitch conversion device includes a Δ/D converter 1 that converts an analog signal, which is a human input signal, into a digital signal;
A memory 2 that stores data, an address switch 3 that switches the address of the memory 2, a write address counter 4 that sends a write address to the address switch 3, and a continuous series that instructs the address switch 3 to read an address. Address counters 5a and 5b, memory controller 6 for switching addresses, sneak mode, and read mode, Δ/D converter 1 d3, and write address counter 4
An internal clock generator 7 supplies clocks to the memory controller 6 and writes requests to the memory controller 6, and an internal clock generator 7 supplies clocks to the read address counters 5a and 5b and supplies read requests A and B to the memory controller 6. a clock generator 8, and (1) a block counter 9 that resets the read address counter 5 when the write address counter 4 counts a predetermined constant block length within a range where the difference between the write address and the read address does not exceed the memory capacity. and data latches 10a and lQ that latch the read data.
b, and a D/Δ converter 11 that converts the read data supplied from the data latch into analog. . However, the pitch conversion device of this embodiment has the following symbols 5a, 5b, 10a, 10bt' in the same figure.
Two systems of read address counters and data latches are provided. In addition, each system has a signal with a potential of zero V.
The pyrocross detectors 17a, 17b which detect the cross and the polarity of the crossing, the A1B switching request from the ten-track counter 9, and the zero cross detection signal from the zero cross detectors 17a, 1711. received

[A zero-cross controller 19 that supplies gate signals to gates 18a and 18b for timing tarlocks of the tarlock generator 8, and a data switch that selects and outputs one of the data latches 10a and 10b. 20 and -C. Next, the operation of each part of this embodiment will be explained. In this pitch conversion device, the analog input signal is A/D
It is converted into digital data by converter 1 and stored in memory 2.
recorded in There are two types of data read from the memory 2, Δ and B, and the read data is transferred -H to data latches 10a and 10b, respectively. The data of these two AlB systems are supplied to the Xerox detectors 17a, 17b4, and either one is selected by the data switch 14.
The signal is converted back to an analog signal by the /A converter 20 and outputted in °C. The output tally clock generator 7 supplies a sample clock to the A'/D converter 1, a clock to the internal address counter 4, and a write request signal to the memory controller 6. The read one check generator 8 is connected to the read address counter 5.
a, 5b, the C clock is supplied through the gates 18a, 18b, and the data latches 10a, 1. Supplies the Ob wave pulses A, , B, supplies the zero cross detectors 17a, 17b, and sends read requests A, B to the memory controller 6.
supply. The memory control F unit 6 receives the write request and the read requests A and B, and after timing, supplies an address switching signal to the address switch 3, and also selects the input mode and the read mode to the memory 2. Provides an R/W signal for the execution. The address switch 3 receives the address switching signal, selects either the write address signal or the read address signal A or 8, and supplies it to the memory 2 as address data. The zero-cross detectors 17a and 17b detect the time when the signal crosses a value corresponding to the potential zero V and the polarity at which the signal crosses, and supply a detection signal to the zero-cross controller 19. The 10-count counter 9 receives a signal from the write address counter 4 and outputs a gate signal to the zero clock [(the bus controller 19 has gates 18a, 181]). Signals A and B are respectively supplied.Next, the configuration and operation of the zero-cross detectors 17a', 17b and the zero-cross controller 19 will be explained. The circuit diagram and Figure 8 are the 1st sheet of Taiminoguchi showing its operation.Zero cross detection!17a and '17b are data A1
Each system of data B is a flip-flop FF1,
The zero cross controller 19 is composed of flip 70 tubes FF3 to FFI1. Since the zero cross beam is detected as a change point of the input pit (or MSB>), -H is latched by the data latch pulse at F'F1 and FF2, and the changes before and after that are extracted to determine the polarity of the change. A change from negative to positive (+ zero cross) and a change from positive to negative (-recross) are detected. FF3~
FF6 and FF7 to FF10 operate alternately. Now, it is assumed that the AS switching request is '1-1', and at this time the Q of FF3 to FF4 is "L".Furthermore, FF5 and FF6 are reset (R) by the Q of FF3 and FF4. When +zero cross is detected here, FF4 is set (S). Also, the reset of FF6 is canceled and FF3 is set.
FF, 5 is reset by F3, and becomes a successive number. Next, FF6 is set by +zero cross detection of data B. Since FF5 continues to be reset, one zero cross detection of data B is not accepted, and since + zero cross detection of data A precedes, F, F4 and FF6 can be activated, and zero crosses of the same polarity can be detected.
Obtain gate signal A. Also, a J:A, B switching signal is obtained for the FF 11. On the other hand, even if one zero-cross detection for data occurs first, FF3, F, and F5 become accu-dip by the same operation, and a negative zero-cross can be detected. Mako, when the A1B switching request becomes L'', FF3 to F
]20 is reset, and FF7 to FF10 become operational. In this case, either the + zero cross detection or the - zero cross detection of data B precedes the FF8
, FF10 or FF7 and FF8 become active, and gate signal @B is obtained. Next, the operation of this embodiment will be explained with reference to FIGS. 9 to 12. Input signals are sampled at regular intervals, converted into digital signals by an A/D converter 1, and then sequentially recorded in a memory 2 according to a write address counter 4. The memory controller 6 receives the write request and the read request A1B, and controls switching of the memory recording mode and read mode, and switching of address data so that they do not overlap in time. Reading is performed for the two systems AXB at a timing different from the self-loading, and the readout system is alternately switched for each block and outputted through the D/A converter 11. FIG. 9(a) shows the input signal sequence, (b+
), (bl), the read cycle is the write cycle. The figure shows two output signal sequences when the length is longer. The two systems of read address counters 5a and 5b are alternately clocked every block period (indicated by a symbol in FIG. 9). Now, if we switch the readout systems of (b + ) and '(b 2 ) at regular intervals as shown in (C), we get
The signal clatter is exactly the same as in the conventional example, and the signal discontinuity shown in FIG. 4 occurs. In addition, when outputting readout systems (bl) and (bl) by switching, if the switching is done at a point where no discontinuity occurs in both signals, signal series with different quality between switching points like (d) can be obtained. is obtained. The timing of this switching is determined as follows. When connecting the signals (a) and (b) shown in Figure 10, the one that sounds the least strange and natural is the signal shown in Figure 10 (X).
The point J indicates the point where the signal crosses the zero potential and the polarity of the crossing is the same. The signals connected at these points have no discontinuity in signal level or discontinuity in phase, and can be heard as natural speech, as shown in FIG. 2C. The zero-crossing detectors 12a, 12b and zero-crossing controller 13 in the present invention thus hold one signal at the zero-crossing point and hold one signal at the zero-crossing point in order to match the signal levels and phases of the two signals and connect them. There is a temporal shift from 1 to C. Figure 11 (7) (a) and (b) show the data A series and data B series of the 61st circuit block diagram, respectively.
There are signals corresponding to (a) and (IL) in FIG. Now, assuming that the signal is a sine wave for simplicity, the zero cross detector 1'7'a of the data A series detects the zero cross point at time e of X, and the zero cross detector 17 of the data B series
1) detects the zero cross at point C of Y. Upon receiving this piston detection signal, the zerox controller 19
In the same figure (()), goo toy No. 3 is manually inputted to the gate 188. Then, the supply of ``glue 1'' to the dress counter 5a is stopped, and the supply of the ``glue 1'' to the dress counter 5a is stopped.
The read address counter 5a stops. Therefore, the first
As shown in FIG. 1(a), the read signal maintains a constant value. Next, the zero cross detection point of the B-series signal is shown in Figure 11 (
) to return to the gate signal [Figure 11 (g)
”, the read address counter A starts operating again [FIG. 11(1)]. Kono [MeY's 04 summer 2 rA series and B
The signals in the series are in phase with each other. 11 (1) l, the output analog data is switched at the zero cross point [Figure 11 (n) 1° zero cross [1st detection is performed first. , the data string that is not currently being output is detected [Figure 11 (e), (III)]
, stops the address counter of this series, and then detects the data string currently being output [FIG. 11(r)]
, (u+)], a continuous signal sequence is obtained by starting the previous address counter's re-operation and alternately repeating a series of operations of switching the output data sequence [Fig. 11 (+1)
], it is possible to eliminate fltW and abnormal sounds due to the discontinuity of the signal joint C. Here e is for when the read cycle is longer than the write cycle (
As described above, the same applies to the case where the read cycle is shorter than the write cycle, and the pitch can be increased.In the above embodiment, an example in which a digital memory is used as the memory 2 has been described, but the present invention The present invention is not limited to the embodiment, and it is also possible to use analog memories such as BBD, C'CD elements. In this case A
/D converter and D/A converter can be omitted. [Effect of the Invention 1] As explained above, according to the present invention, when converting the pitch of an acoustic signal in real time, it is possible to remove noise and unpleasant sounds (due to discontinuity of sound) and perform pitch conversion of a natural sound. can. Furthermore, since the pitch conversion device of the present invention can be realized using a digital logic circuit, it can easily be implemented as an integrated circuit.

[Brief explanation of the drawing]

Figure 1 is a circuit block diagram of a conventional pitch conversion device, Figure 2 is a circuit block diagram of a conventional pitch conversion device.
3 and 3 are timing charts for explaining the operation of a conventional pitch conversion device, and FIG. 4 is a diagram showing a discontinuous portion of an audio signal that occurs when pitch conversion is performed by a conventional pitch conversion device.FIG. 5 6 is a block diagram schematically showing the configuration of the pitch conversion device of the present invention, FIG. 6 is a circuit block diagram of an embodiment of the present invention, FIG. 7 is a circuit diagram of a bald cross detector and zero cross controller, and FIG. 8 is a block diagram schematically showing the configuration of a pitch conversion device of the present invention. 9 is a timing chart showing the status of the block when switching between the A and B systems, and FIG. 10 is a timing chart showing the status of the block when switching between the A and B systems. FIG. 11 is a timing diagram 11 for explaining the operation of the pitch converting device of the present invention. 1...A/D converter 2...
......Memory 3...Address switch 4...
...Write address counter 5.5 as
51'...Read address counter 6...
・・・・・・Memory controller 7・・・・・・・・・・・・
Output clock generator 8...Read clock generator 9...Block counter 10.10a, 1ob...Data line y
Chi 17a, 17b...Zero cross detector 19...
......Zero cross controller 20...
・・・・・・Patent attorney who represents La Ichiyo Switching Device Sasa Suyama −

Claims (1)

[Claims] (1) (a) storage means for storing input signals; and (b)
an input means for sequentially writing data into the storage means at a predetermined timing while repeating rets with a preset block length; (c) resetting the data written in the storage means with a block length equal to the block length; (d) two systems of data holding means for holding data read by the reading means; (b) of the data holding means; , a data switching means for outputting the held data by selecting either one of them; Detect Rocross,
Then, the polarity of the crossing is determined, and in the initial state, no matter which side the polarity crosses from, reading of the reading means on the detected side is stopped only when crossing from the side of the same polarity later, and then the reading means of the detected side is stopped, and then 2. A pitch conversion device comprising: two systems of zero-cross detection means for sending a switching signal to the data switching means when the data switching means is detected.