JPH06259092A - Method for converting interval of audio signal - Google Patents

Abstract

PURPOSE:To make no sense of incompatibility occur and to hear in natural feeling by gaining the time shortened in the high speed reproduction of an audio signal with backward high speed opposite phase reproduction and the forward high speed reproduction of the same audio part and performing the connection to next data at a zero-cross point. CONSTITUTION:An original audio signal is A/D converted to record on a recording medium, and is read out at a high speed according to the interval to be raised. When first zero-cross point A after a fixed time TC lapses is detected at the time of the high speed read, the recording data in a reverse direction on time scale are read out with the opposite phase of positive/negative at the same high speed as the read speed from the point of time. When the first zero- cross point B is detected by the opposite phase high speed read, the recording data are read out toward the zero-cross point A' of the original signal in the positive direction of time scale at the same speed as the read speed from the point of time. Then, when another zero-cross point is detected after a fixed time TC elapses from the zero-cross point B, the operation is repeated. Thus, the data by time compression when the interval is raised is compensated, and the tempo is maintained at a fixed level.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pitch conversion method for suppressing a change in the voice tempo of a voice signal as much as possible and increasing its pitch.

[0002]

2. Description of the Related Art A conventional method for increasing the pitch will be described with reference to FIG. Times t ₁ , t ₂ , and t _{3 in} FIG. 4 indicate data positions (temporally equal pitch).

Here, first, as shown in (a), an input audio signal is sequentially encoded (A / D conversion, etc.) into a signal which can be written in a recording medium (semiconductor memory, etc.) in real time.

Next, the data written in this recording medium is read out, separated by a predetermined time Ta and sent to two decoders (D / A converters, etc.) alternately. At this time, the time Ta is set longer than the time from the time t ₁ to the time t _2, and the leading end of one data and the trailing end of the other data are partially separated (b).

Next, the reproduction speed in this demodulator is increased to decode the audio signal (c). As a result, the data at time Ta is compressed to time Tb (<Ta). The above (b) and (c) are actually realized at the same time by increasing the reading speed from the recording medium.

Next, as shown in (d), fade-in processing is applied to the leading end portion of both audio signals which are alternately decoded, and fade-out processing is applied to the trailing end portion. And finally,
As shown in (e), both signals are combined and output.

According to this conventional method, the pitch can be determined according to the reproduction speed, and usually, it can be realized by increasing the frequency of the read clock when reading the data from the semiconductor memory.

[0008]

However, in this conventional method, the one data and the other data of the combining portion to be combined by performing the fade processing are no longer the same data.

For this reason, the reproduction timing of the latter is faster than that of the former for the same data portion,
A timing shift (phase shift) will occur there.

Therefore, the reproduced sound of the synthesized portion is uncomfortable, which is aurally noticeable. Also, if the synthesized part contains an attack sound, it may be heard as if it sounds twice in succession.

It is an object of the present invention to provide a pitch conversion method which allows the user to hear a natural feeling as a whole without causing the above-mentioned auditory discomfort.

[0012]

To this end, the present invention reproduces an audio signal in a forward direction along a time axis at a desired speed higher than the normal reproduction speed, and reproduces the audio signal in the previous direction during the forward high speed reproduction. By detecting the zero-cross point after a lapse of a predetermined time from the zero-cross point detection, the reproduction is switched to the reverse high-speed reverse phase reproduction in the direction opposite to the time axis and the polarity is reversed, and the zero-cross point is detected in the middle of the reverse high-speed reverse phase reproduction. Thus, the structure is configured to switch to the high-speed reproduction in the forward direction, perform the high-speed reverse-phase reproduction in the reverse direction when a zero-cross point is detected after the predetermined time has elapsed from the switching point, and thereafter repeat the above operation.

[0013]

In the present invention, the pitch is raised by reproducing the voice signal at high speed. The time shortened by the high-speed reproduction is earned by the reverse high-speed reverse phase reproduction and the forward high-speed reproduction of the same voice portion, and the tempo is kept substantially constant. The connection to the next data is made at the zero crossing point and the connection is continuous.

[0014]

EXAMPLES Examples of the present invention will be described below. First, referring to FIG. 1, the principle of the present invention will be described. In the present invention, an original audio signal having a waveform as shown in FIG.
After D conversion, the data is once recorded on a recording medium in real time, and is read at a high speed according to the pitch to be raised (forward high speed reproduction), as shown in (b).

Then, at the time of this high-speed reading, the first zero-cross point A (zero-cross point A of the original signal) after a certain period Tc (corresponding to a time from time t ₁ to t ₂ in FIG. 4) elapses. (Corresponding to ') is detected, recording data in the opposite direction (past recording data) on the time axis from this point of time is read in positive / negative negative phase at the same high speed as the above-mentioned reading speed (reverse direction high-speed reverse phase reproduction).

As shown in (c), when the first zero-cross point B (corresponding to the zero-cross point B'of the original signal) is detected in this reversed-phase high-speed reading, the zero-cross point A of the original signal is detected from there. The data is read at the same speed as the above reading speed in the positive direction of the time axis (forward high-speed playback). The zero cross point C is a data position corresponding to the zero cross point A ′ of the original signal.

When another zero-cross point is detected after a certain time Tc has passed from the zero-cross point B,
The above operation (forward high speed reproduction) is repeated.

As described above, in the present invention, the pitch is raised by reading the original signal at high speed. At this time, high-speed reading is performed twice in the forward direction and once in the reverse-phase reverse direction in the B'-A 'portion of the zero-cross point of the original signal, whereby the time compression amount of the data when the pitch is increased is compensated. The tempo is kept almost constant. Further, since the connection to the next data is made at the zero cross point C (A '),
The connection is made continuously, and there is no discomfort.

The zero-cross point B at which the reverse-phase reproduction is switched to the normal-phase reproduction is not limited to the first zero-cross point from the zero-cross point A at which the normal-phase reproduction is switched to the reverse-phase reproduction. It may be the detection timing of the zero-cross point. Also, the speed of this reverse-phase high-speed playback is
It does not have to be the same as the speed of normal phase regeneration.

FIG. 2 is a concrete circuit diagram for carrying out the pitch converting method of the present invention. Reference numeral 1 is an A / D converter for converting an input audio signal into a digital signal, and 2 is a shift memory in which the audio data output from the A / D converter 1 is written with a fixed frequency clock.

The shift memory 2 is a ring buffer type memory which is used so that the address is reduced and the oldest data is rewritten with new data every writing clock. The data reading of the shift memory 2 can be executed by accessing an arbitrary address deviated from the write address. The read clock has the same frequency as the write clock.

Reference numeral 3 is a buffer for holding new data (current data) and old data (old data for one sampling period) read from the shift memory 2, and 4 is two data held in the buffer 3. When the signs (+,-) of are different, a zero-cross detector that detects this time as a zero-cross point, 5 is a phase controller that inverts the polarity of the data sequentially output from the buffer 3 to the opposite phase if necessary, 6 is a digital It is a D / A converter that converts a signal into an analog signal.

A read address register 7 gives a read address when reading data from the shift memory 2. Reference numeral 8 is an incrementer for increasing the read address of the read address register 7, and 9 is a decrementer for decreasing the read address. Reference numeral 10 is a control unit for controlling the whole by inputting the output of the zero-cross detector 4 and the "pitch-up value", etc., and assigning a base address to the read address register 7, switching the selector 11, controlling the phase controller 5, The old data in the buffer 3 is discarded. 12 is an addition point where “2” is always added.

In this embodiment, the read address register 7 has an offset address (increase or decrease) controlled by the incrementer 8 or the decrementer 9 to the base address controlled by the control unit 10 (the address reduced by 1). Shift memory 2 with the added address value
Output to.

First, when the pitch is not converted, the pitch up (pitch increase value) value in FIG. 2 is set to "0". As a result, the selector 11 is made neutral by both the incrementer 8 and the decrementer 9 by the control unit 10. Therefore, at this time, the read address register 7 is controlled only by the control unit 10 and outputs an address value (base address value) which is decreased by one.

Therefore, in the shift memory 2, as schematically shown in FIG. 3A, at the time t _n , the data “sa” is written to the address “2” and the data “o” at the address “8”. Is read out, and at the next time t _{n + 1} , the next data “SI” is written to the address “1” which is one less than the last time, and the data “C” at the address “7” which is one less than the last time is written. Is read out and this operation continues thereafter. Therefore, the data written in the shift memory 2 is read in the order of writing with a time delay of the address difference between the write address and the read address.

When the pitch is not converted in this way, the read address reduction designation is continued in accordance with the write address reduction designation of the shift memory 2, and the data is read as it is in the order of the input data and sent to the buffer 3. To be The data output from the buffer 3 passes through the phase controller 5 as it is, is converted into an analog signal by the D / A converter 6, and is output.

Next, when the pitch is raised (doubled), the pitch up value is set to "1". At this time, when the control unit 10 detects the first zero-cross point after the time Tc has passed from the previous zero-cross point detection timing, the selector 11 is switched to the incrementer 8 side, and the zero-cross point is detected next. Then, when the zero cross point is detected after the time Tc has elapsed after switching to the decrementer 9 side, the mode is switched to the incrementer 8 side and this is repeated.

Here, when the read address register 7 is controlled by the incrementer 8, the address value output from the read address register 7 is "0" → "2" →
It increases in increments of two such as “4” → “6” → and changes into a ring shape. That is, in the read address register 7, the offset address command "+3" from the incrementer 8 is added to the base address command "-1" from the control unit 10, and the address value increases by two.

On the other hand, when the read address register 7 is controlled by the decrementer 9, "12" → "10" →
The output address value decreases by two as in “8” →, and changes in a ring shape. That is, the read address register 7 adds the offset address command “−1” from the decrementer 8 to the base address command “−1” from the control unit 10.
Is added, the address value is decreased by two.

As described above, when the first zero-cross point is detected after the time Tc has passed from the previous zero-cross point detection, the selector 11 is switched to the incrementer 8 side.
As a result, as shown schematically in (b) of FIG.
_{At n} , the data “sa” is written to the address “2” in the shift memory 2 and the data “o” at the address “8” is read, and at the next time t _{n + 1} , the address “1” decreased by 1 from the previous time. The data "C" is written in "1", the data "C" is read from the address "10" which is advanced by two from the previous time, and this is repeated. Therefore,
The read data is read back in the past every other thinned data.

Since the read clock at this time has the same frequency as the write clock, it is equivalent to reverse reproduction in the opposite direction to the time axis at twice the speed. In other words, double speed reverse reproduction is performed. Then, at the time of the double speed reverse reproduction, the phase controller 5 inverts the polarity of the data input thereto by the control unit 10, so that the obtained data becomes the double speed reverse phase reverse reproduction data.

When this double speed reverse phase reverse reproduction is performed and the zero cross detector 4 subsequently detects a zero cross, the control unit 10 switches the selector 11 from the incrementer 8 side to the decrementer 9 side. As a result, (c) of FIG.
As schematically shown in FIG. 3, at a certain time t _n , data “sa” (actually, the data is different, but the same data will be described here for simplification) is written in the address “2” in the shift memory 2. At the same time, the data “o” is read from the address “8”, and at the next time t _{n + 1} , the data “si” is written to the address “1”, which is one less than the last time, and the address “two” less than the last time. The data "ki" is read from "6" and this operation is repeated. Therefore, the read data will be thinned out and read every other data in the future.

Since the read clock at this time also has the same frequency as the write clock, it is equivalent to reproduction at twice the speed. That is, the reproduction is double speed. Then, during this 2 × speed reproduction, the phase controller 5 does not operate and outputs the input data as it is.

As described above, in FIG. 3A, normal reproduction without pitch up is performed. 2 in (b)
Double speed reverse phase reverse reproduction is performed, and the reproduction from point A to point B in FIG. 1 is executed. In (c) of FIG. 3, double speed reproduction is performed, and this is executed between point B and point C in FIG.

It should be noted that in the above embodiment, only one piece of data is thinned out in the forward direction or the backward direction and read out.
Double-speed playback is being performed, but if the pitch-up value is set to "2", one out of three data will be extracted.
The speed can be tripled and the pitch can be tripled.

[0037]

As described above, according to the present invention, since the voice signal is reproduced at high speed, the pitch rises, and the time shortened at this time is earned by the reverse reverse phase reproduction and the forward high speed reproduction of the same voice portion. Therefore, the tempo is kept almost constant, and further, the connection to the voice is made at the zero-cross point, so that the connection is continuous, and there is a great advantage that the discomfort in hearing is eliminated.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of the principle of the present invention.

FIG. 2 is a functional block diagram of a circuit for implementing the method of the present invention.

FIG. 3 is an operation explanatory diagram of the circuit.

FIG. 4 is an explanatory diagram of a conventional pitch increasing process.

[Explanation of symbols]

1: A / D converter, 2: shift memory, 3: buffer,
4: zero cross detector, 5: phase controller, 6: D / A converter, 7: read address register, 8: incrementer, 9: decrementer, 10: controller, 11: selector, 12: addition point.

Claims (2)

[Claims] 1. An audio signal is reproduced in a forward direction along a time axis at a desired speed higher than a normal reproduction speed, and a zero-cross check after a predetermined time has elapsed from the previous zero-cross point detection in the middle of the high-speed reproduction in the forward direction. Output, the above-mentioned reproduction is switched to the reverse direction high-speed reverse phase reproduction in the direction opposite to the time axis and the polarity is reversed, and is switched to the forward high-speed reproduction by detecting the zero-cross point in the middle of the reverse high-speed reverse phase reproduction, and the changeover. When a zero-cross point is detected after the lapse of the predetermined time from the point, reverse high-speed reverse phase reproduction is performed, and the above operation is repeated thereafter. 2. The forward high-speed reproduction is performed by forward thinning-out reading of audio signal data recorded in advance on a recording medium, and the reverse high-speed reverse phase reproduction is reverse thinning-out of audio signal data recorded on the recording medium. The pitch conversion method according to claim 1, wherein the pitch conversion is performed by reading and phase inversion of the read data.