JP3201865B2 - Audio signal pitch conversion method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pitch conversion method for suppressing a change in the audio tempo of an audio signal as much as possible to increase the pitch (pitch) thereof.

[0002]

2. Description of the Related Art A conventional method for increasing the pitch will be described with reference to FIG. Times t ₁ , t ₂ , and t _{3 in} FIG. 4 indicate data positions (equal pitches in time).

Here, first, as shown in (a), an input audio signal is sequentially encoded (A / D converted, etc.) in real time into a signal that can be written to a recording medium (such as a semiconductor memory).

Next, the data written in the recording medium is read out, separated from the data by a predetermined time Ta, and sent alternately to two decoders (D / A converters and the like). At this time, the time Ta is set longer than the time, from time t ₁ to t _2, a portion of the rear end of the tip and the other data of one data is separated in duplicate (b).

Next, the reproduction speed of the demodulator is increased to decode the audio signal (c). Thereby, the data at the time Ta is compressed to the time Tb (<Ta). The above (b) and (c) are actually realized simultaneously by increasing the reading speed from the recording medium.

[0006] Next, as shown in (d), a fade-in process is applied to the leading end portion of the alternately decoded audio signals and a fade-out process is applied to the trailing end portion. And finally,
As shown in (e), the two signals are combined and output.

[0007] According to this conventional method, the pitch can be determined according to the reproduction speed, and this can usually be realized by increasing the frequency of the read clock for reading data from the semiconductor memory.

[0008]

However, according to this conventional method, one data and the other data of the synthesized part to be synthesized by performing the fade process are no longer the same data.

For the same data portion, the reproduction timing of the latter is faster than that of the former.
A timing shift (phase shift) occurs there.

[0010] Therefore, the reproduced sound of the synthesized portion has a sense of incongruity, which is aesthetically pleasing. Further, when an attack sound is included in the synthesized portion, it may be heard as if the attack sound was heard twice consecutively.

SUMMARY OF THE INVENTION An object of the present invention is to provide a pitch conversion method which does not cause the above-mentioned auditory discomfort and makes the whole sound natural.

[0012]

For this purpose, the present invention reproduces an audio signal in a forward direction along a time axis at a desired speed higher than a normal reproduction speed, and reproduces an audio signal in the middle of the forward high-speed reproduction. By detecting a zero-cross point after a lapse of a predetermined time from the zero-cross point detection, the reproduction is switched to reverse high-speed reverse-phase reproduction in the direction opposite to the time axis and with the polarity reversed, and zero-cross point detection during the reverse high-speed reverse phase reproduction is performed. To switch to the forward high-speed reproduction, and when a zero-cross point is detected after the lapse of the predetermined time from the switching point, the reverse high-speed reverse phase reproduction is performed, and thereafter, the above operation is repeated.

[0013]

According to the present invention, the pitch is raised by reproducing the audio signal at a high speed. The time shortened by the high-speed reproduction is gained by the reverse high-speed reverse-phase reproduction and the forward high-speed reproduction of the same audio portion, and the tempo is kept substantially constant. The connection to the next data is made at the zero crossing point, and the connection is continuous.

[0014]

Embodiments of the present invention will be described below. First, the principle of the present invention will be described with reference to FIG. In the present invention, an original audio signal having a waveform as shown in FIG.
The D-converted data is temporarily recorded on a recording medium in real time, and is read out at a high speed corresponding to the pitch to be raised (forward high-speed reproduction) as shown in FIG.

At the time of this high-speed reading, the first zero-cross point A (zero-cross point A of the original signal) after a lapse of a fixed period Tc (approximately corresponding to the time from time t ₁ to t ₂ in FIG. 4). Is detected, recording data in the reverse direction (past recording data) is read out at this time at the same high speed as the above reading speed in the negative and positive phases (reverse high speed reverse phase reproduction).

As shown in (c), when the first zero-cross point B (corresponding to the zero-cross point B 'of the original signal) is detected in the reversed-phase high-speed reading, the zero-cross point A of the original signal is detected therefrom. Reading is performed at the same speed as the above reading speed in the forward direction of the time axis toward '(forward high-speed reproduction). The zero cross point C is a data position corresponding to the zero cross point A 'of the original signal.

When another zero-cross point is detected after a predetermined time Tc has elapsed from the zero-cross point B,
The above operation (forward high-speed reproduction) is repeated.

As described above, in the present invention, the pitch is raised by reading the original signal at high speed. At this time, in the B'-A 'portion of the zero cross point of the original signal, high-speed reading is performed twice in the forward direction and once in the reverse phase and reverse direction, thereby compensating for the time compression of the data when the pitch is increased. The tempo is kept almost constant. Further, the connection to the next data is made at the zero crossing point C (A ′),
The connection is made continuously, and there is no sense of incongruity.

The zero-cross point B at which the reverse-phase reproduction is switched to the normal-phase reproduction is not limited to the first zero-cross point from the zero-cross point A at which the normal-phase reproduction is switched to the reverse-phase reproduction. The detection timing of the zero cross point may be used. Also, the speed of this reversed-phase high-speed playback is
It need not be the same as the normal phase regeneration speed.

FIG. 2 is a specific circuit diagram for implementing the pitch conversion method of the present invention. Reference numeral 1 denotes an A / D converter for converting an input audio signal into a digital signal, and reference numeral 2 denotes a shift memory in which audio data output from the A / D converter 1 is written with a fixed frequency clock.

The shift memory 2 is a ring buffer type memory that is used to reduce the address for each write clock and to rewrite the oldest data with new data. The data read from the shift memory 2 can be executed by accessing an arbitrary address shifted from the write address. Note that the read clock has the same frequency as the write clock.

Reference numeral 3 denotes a buffer for holding new data (current data) read from the shift memory 2 and old data (data old for one sampling period). Reference numeral 4 denotes two data held in the buffer 3. A zero-crossing detector which detects this point as a zero-crossing point when the signs (+,-) are different from each other; 5, a phase controller for inverting the polarity of the data sequentially output from the buffer 3 to an opposite phase if necessary; This is a D / A converter that converts a signal into an analog signal.

Reference numeral 7 denotes a read address register for giving a read address when reading data from the shift memory 2. 8 is an incrementer for increasing the read address of the read address register 7, and 9 is a decrementer for decreasing the read address. Reference numeral 10 denotes a control unit which controls the whole by inputting the output of the zero-cross detector 4, the “pitch-up value”, etc., assigning a base address to the read address register 7, switching the selector 11, controlling the phase controller 5, The old data in the buffer 3 is discarded. Reference numeral 12 denotes an addition point to which “2” is always added.

In this embodiment, the read address register 7 is provided with an offset address (increase or decrease) controlled by an incrementer 8 or a decrementer 9 at a base address (address that decreases by one) controlled by a control unit 10. To the shift memory 2
Output to

First, when the pitch is not converted, the pitch-up (pitch rise value) value in FIG. 2 is set to "0". As a result, the selector 11 becomes neutral from both the incrementer 8 and the decrementer 9 by the control unit 10. Therefore, at this time, the read address register 7 is controlled only by the control unit 10, and outputs an address value (base address value) that is decreased by one.

Accordingly, in the shift memory 2, as schematically shown in FIG. 3A, at time t _n , the data “sa” is written at the address “2” and the data “o” at the address “8”. At the next time t _{n + 1} , the next data “S” is written to the address “1” which is one less than the previous time, and the data “C” at the address “7” which is one less than the previous time is written. Is read out, and this operation continues thereafter. Therefore, the data written in the shift memory 2 is read in the order of writing with a time delay of the address difference between the write address and the read address.

When the pitch is not converted in this way, the read address is continuously designated in accordance with the designated write address of the shift memory 2, and the data is read as it is in the order of the input data and transmitted to the buffer 3. Can be The data output from the buffer 3 passes through the phase controller 5 as it is, and is converted into an analog signal by the D / A converter 6 and output.

Next, when the pitch is raised (doubled), the pitch-up value is set to "1". At this time, when the control unit 10 detects the first zero-cross point after the elapse of the time Tc from the previous zero-cross point detection timing, the selector 11 switches the selector 11 to the incrementer 8 side, and the next zero-cross point is detected. Is switched to the decrementer 9 side, and when a zero cross point is detected after the elapse of the time Tc, the switch to the incrementer 8 side is repeated.

Here, when the read address register 7 is controlled by the incrementer 8, the address value output from the read address register 7 changes from "0" to "2".
As shown by “4” → “6” →, the number increases by two and changes into a ring shape. That is, in the read address register 7, the offset address command "+3" from the incrementer 8 is added to the base address command "-1" from the control unit 10, and the address value increases by two.

On the other hand, when the read address register 7 is controlled by the decrementer 9, "12" → "10" →
The output address value decreases by two and changes like a ring as in “8” →. That is, the read address register 7 adds the offset address command “−1” from the decrementer 8 to the base address command “−1” from the control unit 10.
Is added, and the address value is decreased by two.

As described above, when the first zero-cross point is detected after the elapse of the time Tc from the previous detection of the zero-cross point, the selector 11 is switched to the incrementer 8 side.
As a result, as schematically shown in FIG.
_n in the shift memory 2 at the address "2" with data "Sa" is written is data "o" of the address "8" is read in, address decreased one from the previous at the next time t _{n + 1} " The data "c" is written into "1", and the data "c" is read from the address "10" which is two steps ahead of the previous time, and this is repeated. Therefore,
The read data is thinned and read every other data retroactively.

Since the read clock at this time has the same frequency as the write clock, it is equivalent to reverse reproduction in the direction opposite to the time axis at twice the speed. That is, double speed reverse reproduction is performed. During the double speed reverse reproduction, the phase controller 5 inverts the polarity of the data input thereto by the control unit 10, so that the obtained data is double speed reverse phase reverse reproduction data.

When the double-speed reverse-phase reverse reproduction is performed and the zero-cross detector 4 detects a zero-cross thereafter, the control unit 10 switches the selector 11 from the incrementer 8 side to the decrementer 9 side. As a result, FIG.
As shown schematically, at a certain time t _n , data “sa” is written at an address “2” in the shift memory 2 (actually, although the data is different, the same data will be described here for simplicity). At the same time, the data "o" is read from the address "8", and at the next time tn _{+ 1} , the data "shi" is written to the address "1" one less than the previous time and the address "two" less than the previous time 6 "is read out, and this operation is repeated. Therefore, the read data is thinned out every other data toward the future.

Since the read clock at this time has the same frequency as the write clock, it is equivalent to reproduction at twice the speed. That is, double speed reproduction is performed. During the double speed reproduction, the phase controller 5 does not operate, and the input data is output as it is.

As described above, in FIG. 3A, normal reproduction without pitch up is performed. In (b), 2
Double-speed reverse-phase reverse reproduction is performed, and reproduction from point A to point B in FIG. 1 is executed. In FIG. 3 (c), double speed reproduction is performed, and between point B and point C in FIG. 1 and between other points are executed.

In the above-described embodiment, by reading out only one piece of data in the forward or reverse direction and reading it out,
Although double-speed playback is performed, if the pitch-up value is set to "2", one piece of data is taken out of three pieces.
The pitch can be tripled by triple speed.

[0037]

As described above, according to the present invention, since the audio signal is reproduced at high speed, the pitch rises. At this time, the shortened time is obtained by the reverse reverse phase reproduction and the forward high speed reproduction of the same audio part. Therefore, there is a great advantage that the tempo is kept substantially constant, and that the connection to the sound thereafter is made at the zero-crossing point, so that the connection is continuous and the sense of hearing discomfort is eliminated.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of the principle of the present invention.

FIG. 2 is a functional block diagram of a circuit for implementing the method of the present invention.

FIG. 3 is an operation explanatory diagram of the circuit.

FIG. 4 is an explanatory diagram of a conventional pitch raising process.

[Explanation of symbols]

1: A / D converter, 2: shift memory, 3: buffer,
4: zero cross detector, 5: phase controller, 6: D / A converter, 7: read address register, 8: incrementer, 9: decrementer, 10: control unit, 11: selector, 12: addition point.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G10L 21/04

Claims (2)

(57) [Claims] 1. An audio signal is reproduced in a forward direction along a time axis at a desired speed higher than a normal reproduction speed, and a zero-cross check after a lapse of a predetermined time from a previous zero-cross point detection during the forward high-speed reproduction. The reproduction is switched to the reverse high-speed reverse phase reproduction in the direction opposite to the time axis and the polarity is reversed, and the zero-cross point is detected in the middle of the reverse high-speed reverse phase reproduction, and the reproduction is switched to the forward high-speed reproduction. A pitch conversion method for an audio signal, comprising: performing reverse high-speed reverse phase reproduction when a zero-cross point is detected after a lapse of the predetermined time from the point, and thereafter repeating the above operation. 2. The forward high-speed reproduction is performed by forward thinning-out reading of audio signal data previously recorded on a recording medium, and the reverse high-speed reverse-phase reproduction is performed by reverse thinning of audio signal data recorded on the recording medium. 2. The pitch conversion method according to claim 1, wherein the reading is performed by reading and phase inversion of the read data.