JPH0373000B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a speech synthesis device, and an object of the present invention is to improve the quality of a synthesized speech signal. In general, the quality of an audio signal synthesized by combining phoneme segments depends on the processing of the connecting parts of the phoneme segments. Sudden changes in waveforms, ie, discontinuities, occurring at the connection portion cause harmonic noise, lowering the S/N ratio of the synthesized sound and reducing the clarity. The present invention makes it possible to obtain a high-quality synthesized sound by calculating and processing the digital values of the audio signals at the waveform connections and engaging each phoneme in a natural manner. The detailed content of the present invention will be explained below using an audio time axis conversion device as a specific example. FIG. 1 is a block diagram illustrating a conventional time axis expansion device. In the figure, terminal 1 is an audio input terminal, 2 is an output terminal, and 3 and 4 are N-bit analog shift registers such as BBD.
5 is a low pass filter (LPF). 6,7,
8 and 9 are analog switches, and input terminal 1
From analog shift register 3 or 4, LPF
The switch controls the audio signal that reaches the output terminal 2 via the terminal 5. In addition, these analog switches are connected to the write clock circuit 1 of the analog shift registers 3 and 4.
Opening and closing are controlled as shown in the figure by the Q and output of a frequency dividing circuit 11 which divides 0 by 2 mN (m will be described later). The analog shift registers 3 and 4 are connected to OR gates 14 and 15 by the clock circuit 10 and the Q of the frequency divider circuit 11, and the output AND gates 12 and 13.
The write clock is alternately controlled via the read clock circuit 16 and the frequency divider circuit 11.
Similarly, OR is performed by output AND gates 17 and 18.
It is alternately read clock controlled via gates 14 and 15. That is, for example, an audio signal in which the time axis applied to the input terminal is compressed by m times (m>1) (such a compressed signal can be obtained, for example, by increasing the playback speed of a tape recorder to m times the recording speed) is , when the Q output of the frequency divider circuit 11 is 1, the analog shift register 4 passes through the analog switch 8.
written to. The number of bits of the shift register is N
Therefore, when the input audio signal completes sequential input as mN sampling strings, the rear end N of the mN sampling strings are stored in the shift register, and the Q output of the frequency dividing circuit 11 is inverted. becomes 0, and the switch 8 is closed. At the same time, the Q output of the frequency dividing circuit becomes 1, the switch 6 is opened, and the analog shift register 3 is written in the same manner. As is clear from the structure shown, the analog shift register 4 is then clocked by a readout clock circuit 16 and read out via a switch 9 which is also controlled by the output. During the writing period to the analog shift register 3, another analog shift register 4 performs reading in this way, and then when the Q and output of the frequency divider circuit 11 is inverted, the analog shift register 4 writes again, and the 3
performs the read. Here write clock circuit 1
0 clock frequency to ₁ , read clock circuit 1
If the clock frequency of 6 is set to ₂ , then if each clock frequency is determined so that ₁ / ₂ = m (1), the time axis will be expanded by m times, and the compressed audio input to audio input terminal 1 will be output. The restored time axis appears on terminal 2. The readout clock frequency ₂ is naturally determined so as to satisfy Nyquist's sampling theorem for the necessary output audio frequency band. In the conventional device as described above, the connection timing of the phoneme pieces that are alternately output from the analog shift registers 3 and 4 is automatically determined every mN/ _second by the output of the frequency dividing circuit 11 that divides the write clock 10 by 2 mN. Therefore, as shown in FIG. 2, discontinuous waveform changes and pitch frequency fluctuations occur at the connection portions of phoneme pieces. As mentioned above, such discontinuities in waveform and pitch at the junctions of phoneme segments significantly degrade sound quality and clarity. Next, in order to improve the drawbacks of the conventional device, the inventor of the present application previously filed a patent application No. 59-94802.
The contents of the prior art described in No. No. (filed on June 18, 1982) will be briefly explained with reference to the block diagram in Fig. 3. In the figure, 101 is an audio signal input terminal, 102 is an audio signal output terminal, and 103 is an analog-to-digital conversion circuit (hereinafter referred to as A/D) for converting the audio signal into digital data. 1
04 is a random access memory (hereinafter referred to as RAM) having a storage element of 2 ^A bytes, and when the control input terminal LT ₃ is at the logic level "0", the data input terminals I ₁ to I _d (lower I ₁ ) are The received digital value is stored at the address given by the address input terminals A ₁ to _{A a} (lower A ₁ ). When control input terminal LT ₃ is at logic level “1”, address input terminal A ₁
The contents of the address given by ~A _a are output to data output terminals O ₁ ~ _{O d} . 106 and 108 are clock generation circuits. Clock generation circuit 10
The output fR of 6 is supplied to the clock input terminal T of the read counter 107 via the OR gate 120.
The output of read counter 107 is incremented. The read counter 107 is an A bit counter,
An initial value is set by the output of the arithmetic control circuit 105. Here, we will discuss how to set this initial value. First, the arithmetic control circuit 105 is a read counter 10.
The output of the read counter 107 is cleared by applying a pulse to the clear input terminal CL of No. 7. Next, the initial value of the read counter 107 is set by applying the number of pulses to be initialized from the SC (Set Counter) terminal of the arithmetic control circuit 105 to the input of the OR gate 120. Note that the period for setting this initial value is the interval at which the output fR of the clock generation circuit 106 is counted a predetermined number, and therefore the output value of the read counter 107 at this time is the same as that initialized in the previous period. This value is the value plus a predetermined number, and the number of clocks obtained by subtracting this value from the value to be newly set as the initial value is read out via the OR gate 120 and the counter 10
It is sufficient to supply it to the clock input terminal T of No. 7. In this case, there is no need to clear the read counter.
Incidentally, the increment of the read counter 107 by the arithmetic control circuit 105 described above is performed by the clock generation circuit 106.
This must be done when the output fR of is at logic level "0". If the above setting is to be performed even when the logic level of fR is "1", an AND gate 121 is placed at the input terminal from fR of the OR gate 120 as shown in FIG. This fR is supplied, the output terminal of the arithmetic control circuit 105 is connected to the other input terminal, and the output of the AND gate 121 is connected to the input terminal of the OR gate 120. If one of the inputs is prohibited, the initial value of the read counter 107 can be set regardless of whether the logic level of fR is "0" or "1". Further, the initial value setting of the read counter 107 by the arithmetic control circuit 105 is similarly performed by using the output fH of the clock generation circuit 123 as shown in FIG. In this case, fH is a clock with a sufficiently high frequency compared to fR, and this
One input terminal of the AND gate 122 and an input terminal of the arithmetic control circuit 105 are connected. When the arithmetic control circuit 105 sets the initial value of the read counter 107, it applies a logic level "0" to the input of the AND gate 121, a logic level "1" to the input of the AND gate 122, and sets the output of the clock circuit 123 to After counting a predetermined number, the read counter can be initialized by returning the input of AND gate 121 to logic level "1" and the logic level of AND gate 122 to "0". Furthermore, it is clear that the same effect can be achieved even if the read counter is constructed from a preset counter and the initial value is directly preset. After the initial values are set in this way,
The read counter divides fR. Note that the lower bit of the outputs _Y1 to _Ya of the read counter is _Y1 . Now, the clock generation circuit 108 is the RAM 104.
Provides write clock timing. The output fw of the clock generating circuit 108 is supplied to the clock input terminal T of the A-bit frequency dividing circuit 109, and the outputs W ₁ to _{W a} (lower W ₁ ) of the frequency dividing circuit 109 are incremented sequentially. 110 is a switching circuit, and a control input
When LT ₁ is at logic level “1”, the frequency divider circuit 109
The outputs W ₁ to _{W a of}
output to address inputs A ₁ to A _a . 114,1
16 is an inverter, 115 is an AND gate,
117 is a NAND gate. R ₁ , R ₂ and R ₃ are resistors, and C ₁ , C ₂ and C ₃ are capacitors. R ₁ and C ₁ , R ₂ and C ₂ , and R ₃ and C ₃ each constitute an integrating circuit. Letting these time constants be τ ₁ , τ ₂ , and τ ₃ respectively, they are all sufficiently smaller than the period of the write clock fw. It is configured so that τ ₁ > τ ₃ > τ ₂ . That is, as shown in Figure 6,
The output of the AND gate 115 (b in the figure) becomes logic level "1" at the rising edge of fw (a in the figure), and falls when the capacitor _C1 is charged with the time constant _τ1 . The output of the NAND gate 117 (c in the same figure) is fw
It falls later than the rise of (a) in the same figure,
It rises before the output of the AND gate 115 falls. Reference numeral 111 denotes a latch circuit, which transmits the input to the output when the logic level of the control input terminal _LT2 is "0", and latches and outputs information at the time of rising when it is "1". 112 is digital
It is an analog conversion circuit (hereinafter referred to as D/A),
Convert digital values to analog values. A low-pass filter 113 removes sampling noise from the D/A converted audio signal. 130 is
It is a NAND gate, and the output of the AND gate 115 and the output of the arithmetic control circuit 105 are connected as inputs, and the output is connected as the input of the LT ₂ of the latch circuit 111. The arithmetic control circuit 105 keeps the logic level “0” while setting the initial value of the read counter 107.
Output to NAND gate 130. In a transient state where the initial value of the read counter is thereby set, the latch circuit 111 is configured not to transmit the input to the output. With this configuration, the audio signal applied to the input terminal is converted into a digital value by the A/D 103, and is sent to the RAM 104 at the cycle of the write clock fw.
is memorized. That is, when the output of the AND gate 115 is "1", the address input A ₁ of the RAM 104
~ _Aa is given the output of the frequency dividing circuit 109, the control input terminal _LT3 becomes "0", and the output of the A/D 103 is stored. Since the frequency dividing circuit 109 advances with a period of fw, the addresses of the RAM 104 where the audio signal is sampled and stored are continuous.
However, the address of ^2A is 0. write clock
The audio signal sampled according to fw and stored in the RAM 104 as a digital value is read out according to the readout clock fR, and the D/A conversion 1
12, and the audio signal is reproduced as an analog signal. This write clock FW and read clock
The ratio of fR is the ratio of time axis conversion. The read counter is incremented at the period of the read clock fR, and therefore the address from which the contents of the RAM 104 are read is incremented at the period of fR. The reason why the latch circuit 111 is provided is to prevent the contents of an erroneous address from being read out when writing to the RAM 104. That is, reading from the RAM 104 is performed at all times except when writing. Now, as explained in the prior art example of FIG. The arithmetic control circuit 105 is
Arithmetic processing unit CPU programmed by ROM
(computer). FIG. 7 shows the operation of the arithmetic control circuit 105. Each processing period is a period in which N read clocks are counted. Below, the time axis t direction is the write clock.
Described in units of fw. Of the N phoneme segment sample strings read out in [processing cycle 2], the last M sample strings are stored in [processing cycle 1] in accordance with the write clock fw. (M+r) sample sequences are taken from the beginning of [processing cycle 2], and a point K having a high phase opening is calculated for this and the above-mentioned M sample sequence. The calculation of this K will be described later. Since the phase opening degree of the above-mentioned M sample strings is high from the time when K samples have passed from the beginning of [processing cycle 2],
At the beginning of [processing cycle 3], the output of the read counter 107 is initialized to the value of the output of the frequency dividing circuit 109 at the time (K+M) times past the beginning of [processing cycle 2]. As a result, the sample string of the audio waveform read out at the connection point between [processing cycle 2] and [processing cycle 3] can be continuous.
The M sample strings from the time when (K+M) write clocks fw are counted from the beginning of [processing cycle 2] are the rear end M sample strings read out in [processing cycle 3], and are used for the next processing. This is stored for calculation of connection points between cycles. Thereafter, by performing this operation every processing cycle, the waveforms will be smoothly connected. Now, calculation of the value K of a connection point with a high phase opening will be described below. Figures 8a and b are M samples of the rear end of the preceding phoneme written in [processing cycle 1] and (M+r) samples of the front end of the succeeding phoneme at the tip of [processing cycle 2] in Figure 7, respectively. A sample is shown below. The sequence of samples at the rear end of this preceding phoneme is Xp
(p=1, 2, . . . M), and the sample sequence at the front end of the subsequent phoneme segment is Yp (p=1, 2, . . . , M+r). These Xp and Yp are obtained by sampling the output of the A/D 103 using the write clock fw. In order to calculate the similarity of phoneme segments, it is best to calculate the squared error (e ² _k ) between Xp and Yp. The squared error (e ² _k ) is: e ² _k = 1/M _M 〓 ^P=1 (Xp-X/σX-Yp+K-Y/σY) ² ...(2) However, = 1/M _M 〓 ^{P= 1} Xp,=1/M _M 〓 ^P=1 Yp, K=0, 1, 2, ..., r-1. This represents the degree of similarity when Yp is shifted by K points and superimposed on the sampling waveform Xp. However, the arithmetic processing based on equation (2) actually requires a huge number of calculation steps, and requires a high-performance computer to perform calculations in a short period of time (at least several tens of milliseconds). originally
Equation (2) examines the correlation between two waveforms with different amplitudes and levels, and therefore the standard deviations σx, σy
The error is calculated by normalizing the waveform with , and then calculating the sum of squares of the difference from the average level. By the way, in the case of the speech synthesis device of the prior art, the phoneme pieces handled have waveforms that are close in time, so it can be considered that they are originally similar in amplitude and level. In this case the difference between the two waveforms is (2)
Instead of the formula, e ² _k =1/M _M 〓 ^P=1 (Xp−Yp+k) ² ...(3) may be calculated. Furthermore, in the case of the first technique, it is sufficient to grasp the timing at which the similarity between the two waveforms is maximum, and therefore equation (3) can be further replaced with the following equation (4). g _k = _M 〓 ^P=1 |Xp−Yp+k| (4) Here, for Xp and (Yp+k), only the most significant digit of the A/D converter may be used. Alternatively, the polarity near the AC crossover point of the input signal may be used. in this case
Both Xp and (Yp+k) are [1] or

[0]
It is. That is, this is the integral of the absolute value of the difference between the corresponding sampling values, and the connection timing is determined by knowing k at which this is the minimum. In the technique of the prior application, in order to minimize the calculation processing time, g _k = 1/M _M 〓 ^P=1 (XpYp+k) ... (5) may be calculated instead of equation (4). In equation (5), Xp and (Yp
+k) is the most significant digit data of the A/D converter, [1] or

It is [0]. The symbol is a symbol for exclusive OR, and therefore, (XpYp+
k) is the exclusive OR of Xp and (Yp+k), that is, Xp and (Yp+k) are both [1], or

When [0]

[0] is given, and at other times [1] is given. Therefore, the similarity between the binary signal sampling data Xp at the rear end of the preceding phoneme and the binary signal sampling data Yp at the leading end of the subsequent phoneme is given by gk, and it is necessary to know k that minimizes this gk. The connection timing is determined by That is, the arithmetic control circuit 105 sets gk to k=0, 1, ..., r-
1, and determine k for which this is the smallest. That is, as shown in FIG. 8, the least error is achieved when the M sample strings at the rear end of the preceding phoneme are superimposed from a portion shifted by k from the beginning of the succeeding phoneme. As explained above, the arithmetic control circuit 105 receives the audio signal applied to the input terminal 101 from the A/D 103.
The digital values converted by the above are sampled by the write clock fw, which is the output of the clock generating circuit 108, to obtain the sample strings Xp and Yp. The timing of taking in the sample strings Xp and Yp is all instructed by the values of the outputs W ₁ to _{W a} of the frequency dividing circuit 109. Further, the arithmetic control circuit 105 counts the readout clocks output from the clock generation circuit 106, and when N clocks are counted, sets the initial value of the readout counter 107 and enters the next processing cycle. The value for initializing this read counter is the sum of k obtained by calculating Xp and Yp and the instruction value of the frequency dividing circuit when Yp is taken in. Note that the sample string on which the arithmetic control circuit 105 calculates the degree of similarity is obtained by using an analog input signal applied to the input terminal 101 from an A/D converter different from the A/D converter 103 or a zero-crossing polarity detection circuit ( (not shown) may be converted into a digital value and sampled in accordance with the first clock fw. In this way, the technology of the prior application is based on the arithmetic control circuit 105.
The present invention provides a time base conversion circuit which can obtain smooth connection points by the function of . Therefore, it is possible to obtain a synthesized sound with less probability of discontinuity of connection points and fluctuation of pitch frequency as in conventional devices. However, in this prior art, although it is possible to obtain an improved synthesized sound quality as described above compared to the conventional example, it is not sufficient. In other words, the technology of the prior application has been explained based on the premise that the waveforms of adjacent phoneme segments of several tens of milliseconds are similar in speech, but strictly speaking, the waveforms of adjacent phoneme segments of several tens of milliseconds are similar. This means that there is a high probability that the waveforms are similar. In other words, there are cases where adjacent phoneme segment waveforms are different from each other with a certain probability, and considering such a case, even in the prior art, discontinuity at the connection part and fluctuations in the pitch frequency may occur. It is occurring. In addition, the envelope waveform at the beginning and end of a syllable has large fluctuations in the amplitude direction, and in such cases, even if pitch connection is possible using the technology of the prior application, the amplitude envelope often fluctuates at the connection point. There is a problem that the synthesized sound quality is impaired. The present invention proposes a device that can solve this problem. That is, the present invention stores a sample string of digital values at the portion following the connection point at the rear end of the preceding phoneme stored in the RAM, and a sample string of digital values at the front end of the succeeding phoneme for each corresponding sample point. By adding them at a constant ratio and storing the added digital values at sample points at the front end of each corresponding subsequent phoneme segment, connections without discontinuities in waveforms can be obtained. In FIG. 3, the audio signal converted into a digital signal by the A/D 103 is stored in the RAM 104, read out and latched by the latch circuit 111, but in the configuration of the present invention, in addition to this,
The audio signal stored in the RAM 104 is read out by the arithmetic control circuit 105, arithmetic processing is performed, and the audio signal is read out from the RAM 104.
04, and is configured as shown in FIG. FIG. 9 is a block diagram showing this main part, and the audio signal converted into a digital signal by the A/D 103 is stored in the RAM 104.
In addition to the function explained in FIG. 3 in which this data is read out, latched by the latch circuit 111, and D/A converted, the memory contents of the RAM 104 are also read out by the arithmetic control circuit 105 and processed by the RAM 104 again.
04. Therefore, the arithmetic control circuit 105
outputs address designation outputs P ₁ to P _A to the switching circuit 110 so that the address of the memory contents of the RAM 104 can be designated. Figure 10 shows the RAM 104 in the arithmetic control circuit 105.
In order to explain the function of processing the memory contents of
This is a redrawn version of Figure 7. As explained in FIG. 7, the rear end J ₁ of the preceding phoneme and the front end J ₂ of the succeeding phoneme are connected, but the sample MP of the phoneme from the time of J ₁ and the sample MP of J ₂ are connected. MD that performs arithmetic processing on the sample MS from a point in time and rewrites the MS using this result. Figure 11 shows these MP, MS and MP
FIG. 3 is a diagram showing a sample waveform obtained by arithmetic processing of and MS. Let MP sample sequence be [MP _i j] = [MP ₁ j],
[MP ₂ j], ... [MP _A j], (j=1, 2, ...
_B ) MS sample sequence [MS _i j] = [MS ₁ j],
[MS ₂ j], ...[MS _A j], then (j=1,
2,... _B ) MD _i j=(A-i)MP _i j+i・MS _i j/A...(6) A sample sequence, that is, [MD _i j]=(A-1)MP ₁ j+MS ₁ j /A, (A-2)MP ₂ j+2MS ₂ j/A, ...MP _A j+(A-1)MS _A j/A ...(7) is created by arithmetic processing, and [MS _i j]
Just change it to . This is because the ratio of adding J pieces from the sample strings of MP and MS is changed sequentially, and each time the number i increases, the waveform of the preceding phoneme is added sequentially from the trailing end waveform (Figure 11a) to the succeeding phoneme. There is a smooth transition (Fig. 11c) to the tip waveform of the phoneme (Fig. 11b). In this way, even if a sudden change in waveform or level of a phoneme occurs, smooth waveform connection without noise fluctuation can be achieved. In addition, in the above explanation, the waveform connection point was calculated by the arithmetic control circuit 105 so that the basic pitches of the phoneme segments could be connected, and the waveform processing described above was performed after controlling the readout position. However, noise generation due to discontinuity of connection points can be prevented. However, in this case, deterioration in sound quality due to pitch fluctuation cannot be avoided. Since the present invention has such a configuration, it is possible to obtain a smooth synthesized sound of high quality without causing any discontinuity at the waveform connection point.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional speech synthesis device, FIG. 2 is a diagram showing the characteristics of the conventional device, FIG. 3 is a block diagram showing the configuration of the speech synthesis device of the present invention, and FIGS. FIG. 5 is a circuit diagram showing an example of the configuration of the main part when initializing the read counter 107 shown in FIG. 3, and FIG. Figure 7 is a diagram showing a time chart for explaining the operation of the arithmetic and control circuit 105 of the same device shown in Figure 3. Figure 8 is a diagram showing M preceding phoneme segments and subsequent phoneme units (M+r). Figure 9 is a waveform diagram of sample sequences Xp and Yp in Figure 3.
FIG. 3 is a circuit diagram of the main parts of the speech synthesis device of the present invention, which is produced by modifying FIG. 3 in order to add a function of processing the stored contents of RAM 104 in an arithmetic processing circuit 105 and writing them to RAM 104. FIG. FIG. 10 is an explanatory diagram of the operation of the present invention, which is a rewrite of FIG. 7 in order to explain the function of the arithmetic control circuit 105 in the present invention. FIG. 11 is a waveform diagram for explaining the process of creating a new sample waveform MD from the MP and MS shown in FIG. 10. 101...Signal input terminal, 102...Signal output terminal, 103...Analog-digital conversion circuit, 104...Random access memory, 105
... Arithmetic control circuit, 106 ... Clock circuit that generates a read clock, 107 ... Read counter, 108 ... Clock circuit that generates a write clock, 110 ... Switching circuit, 111 ... Latch circuit, 112 ... Digital - Analog conversion circuit, 113...Low pass filter, MP...Sample waveform of the preceding phoneme after the connection point, MS...Sample waveform of the subsequent phoneme after the connection point.

Claims (1)

[Scope of Claims] 1. A speech synthesis device that performs editing and synthesis using phoneme segments extracted from an analog speech waveform, comprising: (a) analog-to-digital conversion means for converting an analog input signal into a digital signal; (c) digital storage means for storing the output of the converting means in accordance with one clock; The degree of similarity between the digital value sample sequence at the rear end of the preceding phoneme segment and the digital value sample sequence at the front end of the subsequent phoneme segment obtained by sampling a separate analog input signal. The degree of similarity is calculated, and the connection point between the rear end of the preceding phoneme segment and the front end of the succeeding phoneme segment of the portion with the highest degree of similarity, that is, the connection point between the preceding phoneme segment in the digital storage means and the following phoneme segment in the digital storage device, is calculated. Determine the address of the connection point [connection point A ₁ of the preceding phoneme, connection point A ₂ of the succeeding phoneme], and calculate the digital value of the preceding phoneme at the part following the decided end A ₁ of the preceding phoneme. The sample string and the sample string of digital values of the subsequent phoneme in the part following the determined connection point _A2 of the subsequent phoneme are added at a fixed ratio at each corresponding address, and the sample string of the added digital values is added. (d) converting the digital value read from the digital storage means based on the second clock into an analog value; digital-to-analog converting means for reproducing audio signals, and the arithmetic control means converts a sample string of digital values of the preceding phoneme at a portion following the rear end of the preceding phoneme and a front end of the succeeding phoneme. Speech synthesis characterized in that the ratio of adding sample strings of digital values of subsequent phoneme segments at each corresponding sample point is controlled so that the former ratio is initially high and the latter ratio increases sequentially with the sample points. Device.