JPH067356B2 - Pitch converter - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a signal pitch converter.

[Constitution of Prior Art] The constitution of a conventional pitch converter is shown in FIG. 1 is a low pass filter for band limiting the input signal, 2 is an A / D converter for converting the output of the low pass filter into a digital signal, 5 is a D / A converter, and 3 is a random access memory for temporarily storing the digital signal (hereinafter RAM), 4 is RAM3
A low-pass filter (LPF) that extracts the necessary signal components from the D / A-converted signal that converts the digital signal output from the digital signal to an analog signal, 6 is a RAM for the digital signal
An address counter for writing data in 3 and an address counter 7 for designating a read address.

[Action / Operation]

Pitch conversion is performed by changing the clock frequency _W of the write address counter 6 and the relative frequency of the clock frequency _R of the read address counter 7 in FIG. 1, and the frequency of the signal shown in FIG. Fig. 7
The pitch is converted to _R / _W times as shown in (a), (b), or (c).

〔Disadvantage〕

In the configuration of the conventional pitch converter, the bit length of the A / D converter is determined by the dynamic range of the input signal, and the RAM capacity and the data length of the discontinuity processing circuit are also defined by the bit length. For example, in the case of pitch-converting an input signal having a dynamic range of about db, at least 12-bit length is required, and in the case of actually configuring the processing circuit, there are disadvantages that the processing circuit becomes large-scale and large-capacity RAM is required.

[Object of the Invention]

The present invention has been made to eliminate the above drawbacks.
When digitizing the input signal, the difference between the predicted value and the input signal is digitized to reduce the number of required data bits, and by setting the prediction coefficient to an appropriate value smaller than 1, Japanese Patent Application Sho 59-0
It allows the crossfade method proposed in No. 15365 to be performed.

[Structure of Invention]

An embodiment of the present invention will be described with reference to FIG. In FIG. 2, 1 is an LPF that limits the band of the input signal, _2a is an encoder that makes the difference between the predicted value and the input signal and makes it a digital signal,
3 (hereinafter referred to as RAM) random access memory temporarily storing the digital signal, 4 _a decoding device for reproducing the original signal from the difference value, the writing is LPF, 6 for removing unnecessary waves contained in the reproduction signal 5 A write address counter that determines an address, and a read address counter 7 that determines a read address. Where 2 _a encoder, 4 _a
The decoder may have various configurations and is shown in, for example, the document "Digital Signal Processing of Image" published by Nikkan Kogyo Shimbun. The encoder and decoder shown in FIG. 2 (a) are of a hybrid type using an analog signal and a digital signal. In FIG. 2, A is the input signal a and the predicted value b
, B is an A / D converter that converts the difference signal into digital data, and C, D, E, and F are decoders that reproduce the original signal from the difference value (in the case of an encoder, local decoding). It is called an adder), and is an adder, a delay element, a coefficient multiplier, and a D / A converter, respectively.

[Action / Operation]

The operation will be described with reference to FIGS. In FIG. 2, the subtractor A obtains the difference signal ε between the input signal a and the predicted value b. This difference signal ε is converted into digital data by the A / D converter B. Digitized data Is written at the address of the RAM 3 indicated by the write address counter 6 at the sampling speed _w . On the other hand, the above data It is reproduced by the local decoder 2 _b, to obtain a prediction value b. Ie data Is a digital signal of the predicted value b in the adder c Is added, delayed by the delay element D, multiplied by the prediction coefficient α by the coefficient multiplier E, and becomes an analog signal by the D / A converter F,
It becomes the next predicted value b. The relationship between the input signal a, the predicted value b, and the error signal ε is as shown in FIG. (X is the meaning of a function) The method for obtaining the predicted value b is shown in the above-mentioned document, but the method shown in FIG. 3 and the configuration shown in FIG.
It is called pre-prediction (DPCM), and the prediction value b is obtained by the following algorithm.

Digitized error signal Reproduced digital signal And Becomes Here, α is called a prediction coefficient and takes a value of 0 <α ≦ 1. When α = 1, it is called a perfect integration type, and when 0 <α <1, it is called a leak integration type. Reproduced digital signal Is converted into an analog signal by the D / A converter F and the predicted value b
To get

On the other hand, the error signal written in RAM3 Is read out at the read frequency _R, the original signal a is reproduced into an analog signal d obtained by the pitch conversion by the decoder 4 _a made by exactly the same structure as the local decoder 2b. That is,
Read signal Is the predicted value in the adder C ₁ Is added, and the input signal a is pitch-converted by the D / A converter F ₁ to become the analog signal d. Further, the summed signal prediction coefficient α in the coefficient multiplier E ₁ is delayed by a delay element D ₁
Multiply by and the next predicted value Sent to the adder C ₁ as Is added to. This analog signal d is finally the LPF
After passing through 5, unnecessary components are removed and then output. It is obvious that a pitch-converted signal can be obtained by changing the relative values of the write frequency _W and the read frequency _R. At this time, processing for preventing signal discontinuity is necessary, but the method described in Japanese Patent Application No. 59-015365 can be used.

An example of applying the method of Japanese Patent Application No. 59-015365 is shown in FIG.
It is shown in FIG. FIG. 4 shows the waveform when the prediction coefficient α = 1, 4- (a) is the error signal, and 4- (b) is the reproduced waveform after processing the discontinuous points. When α = 1, a DC offset may occur in the processed waveform. In FIG. 4, an offset of 4- (c) shown in the drawing occurs. This DC offset may occur at each processing of discontinuity points, and is cumulatively added, and there is a risk of exceeding the dynamic range.

In order to solve such a drawback, the prediction coefficient α may be set to be smaller than 1, and an example will be shown below.

FIG. 5 shows the case where α = 0.95, where 5- (a) is the error signal and 5- (b) is the reproduced waveform after processing the discontinuous points. In this case, the DC offset shown in FIG. 4 does not occur and a good reproduced waveform can be obtained.

In this example, the encoder and the decoder are shown as a hybrid type, but the same effect can be obtained in an all digital type.

Figure 2 (b) shows an analog encoder _2a , which is a digitized error signal. Back into an analog signal by a D / A converter F _2, integrators F ₃ this
And the coefficient multiplier E ₂ multiplies it by α and sends it to the subtractor A ₁ as the next predicted value b.

FIG. 2 (c) shows a digital encoder 2c. The input signal a is digitized by the A / D converter B ₁ and enters the subtractor A ₂ to obtain the error signal. Predicted by adder C ₂ And delay with delay element D ₂ and α with coefficient multiplier E ₃ .
Multiply by to subtractor A ₂ and then predict To send as.

FIG. 6 shows a block diagram of an embodiment of the present invention including a discontinuity processing unit.

In FIG. 6, the input signal a shown in FIGS. 7 (a) and (a) passes through the low pass filter 1 for band limiting, and the band limited signal enters the encoder _2a , where the sampling time
It is divided by t ₁ and the difference signal ε is calculated to calculate the digital signal Is converted to. That digital signal Is written in the RAM 3 at any time according to the output address WA of the write address counter 6 counted at the clock frequency _w , and the data written in this RAM 3 is read out at any time from the RAM 3 according to the address RA of the read address counter 7 counted at the clock frequency _R. Be done. Then, the read address RA and the write address W
When A and A are not close to each other, that is, when it is not necessary to perform signal processing of the connection point, the output signal of the RAM 3 passes through the multiplexer (C) 9 and enters the decoder 4 _a , and the low-pass filter 5 at the final stage. , The analog signal d is obtained and the final output is obtained by converting the input signal a into the ratio of the frequencies _W and _R , that is, the pitch conversion rate of _W / _R. For example _W > _R
The final output converted to the pitch conversion rate of is obtained. For example
_{When W} > _R , the input signal a is pitch converted to a low frequency as shown in Fig. 7 (a) (b), and when _W < _R , the input signal a is shown in Fig. 7 (a) (c). Pitch converted to frequency as shown.

Now, comparing the circumference of Fig. 7 (b) to the address of RAM3,
Now, assuming that _R > _W, both the read address RA and the write address WA are moving clockwise (clockwise), and let us consider a case where the difference between the read address RA and the write address WA is narrowing. When the difference between the two addresses becomes smaller, the fade process is performed on the signal. The number of data processed as described above is the same at any pitch conversion rate.
1000 data. The processing of the signal for 1000 data must be completed immediately before the read and write address difference is reduced and the two addresses match. Therefore, for any pitch exchange rate, signal processing should be completed just before the addresses match.
For each pitch exchange rate, the amount of address difference at which the signal processing should be started is obtained, and this information is also stored in the address difference setting unit 15. Therefore, the address difference setting unit 15 receives the information of the frequencies _W and _R and outputs the address difference information S ₁ at the start of signal processing according to the pitch conversion rate at that time. The address difference calculator 16
Calculates the address difference information S ₂ between the write address and the read address at any time, and determines whether the output data of the address difference calculator 16 and the address difference setter 15 match.
Is detected, and the coincidence detection signal S ₃ is sent to the signal processing timing generator 21.

These states will be described with reference to FIG. 7 (b). It is assumed that the read address RA and the write address WA are at the positions shown in the figure, the number of processed data is b ₁ , and the relationship between the read address frequency and the write address frequency at present. From the address difference setter 15 to a ₁
Is specified. That is, when the read address RA reaches the position shown in the figure, the address difference calculator 16 outputs the value of a ₁ and the coincidence detector 19 confirms that the outputs of the address difference setter 15 and the address difference detector 16 coincide with each other. The detection is started and the signal processing is started, and the signal processing is performed within the section of b ₁ . As a result, the signal processing is completed before the read address and the write address match.

Now, referring to the actual content of the signal processing, the signal S _o of the first signal processing timing generator 21 by the signal S ₃ when the signal processing is started occurs multiplexer (B) 13
Is switched so that two data, that is, the data read at the read address RA and the data to which the read address RA jumps, are read simultaneously. In FIG. 7 (b), it is assumed that the jump destination is marked as point J. The jump destination point J may be a position before the position of the write address WA at the time of starting the signal processing. For example, as shown in FIG. Position the tip. Therefore, assuming that the address difference between the jump destination and the read address RA is α ₁ , the jump destination address can be obtained by adding α ₁ to the read address RA at any given time, and when the read address RA moves within the range of I, The jump destination address moves in the range of II. Then, the constant adder 17 adds the α ₁ to the read address RA. That is, in FIG. 6, the output address RA of the read address counter 7 is first input to the RAM 3 through the multiplexers (B) 13 and (A) 12, and the data on that address is read. Is read from the RAM 3 and latched by the latch circuit I4b.
Next, the address RAα ₁ obtained by adding α ₁ to the output of the read address counter 7 is output from the constant adder 17, and the data on that address is similarly output. Is read from RAM3 and latched in the latch circuit II5b. When the signal processing is started in this way, the data at the address of range I, the data at the address of range II, and the data at the address of range II in FIG. 7B are read out at the same time. By the way, the data read at that time is represented by the waveform of FIG. 7 (c), the data Iε read in the range I part is a solid waveform, and the data IIε read in the range II part is a dotted line. Waveform. For those two waveforms, the waveform of I in Fig. 7 (e) is shown in Fig. 7 (d), and the waveform of the decreasing fade-out function I _a , II in Fig. 7 (d) is shown in Fig. 7
Address each of the increasing fade-in function IIa in (d)
Signal processing is performed so that the result of multiplication in the period of b ₁ and the addition of the results are output as the output of period b ₁ . That is, the function Ia is a decreasing function that starts with 1 and ends with O, and the function IIa is an increasing function that starts with O and ends with 1. From this, fade-in and fade-out are performed. For example, now 7th
Assuming that the read address RA is at the position of t ₁₀ in FIGS. (C) and (d), the data read at the point data g read at the read address RA and the read address RAα ₁ are read. The data h at the output points are first of all the latch circuit I4b and the latch circuit I4b, respectively.
Latched to II5b. At that time, the signal value S ₄ of the signal processing timing generator 21 generates the function values (i and j in the diagram (d)) from the coefficient setter 20 and supplies them to the multipliers I6a and II7a. In
The output of the latch circuit I4, that is, the signal g ₁ obtained by multiplying the data g at that point by the function value i given from the coefficient setting device 20 is output. In the multiplier II7a, the output of the latch circuit II5, that is, the data h at that point
And a signal hj obtained by multiplying the function value j given from the coefficient setter 20. Then, the outputs of the multipliers I6a and II7a are added by the adder 8, and the output data S ₅ of the adder 8 is added.
The final output at time t ₁₀ , the output data S ₅ is input to the decoder 4 a through the multi-plexer (C) 9.

In this way, a fixed amount of 1000 data is always faded in the section b ₁ , and the fade processing of 1000 data is completed, and the read address RA is at the position of 1 point X ₁ in FIG. 7 (b). When it comes, the constant adder 17 loads the α ₁ value to the read address counter 7 by the signal S _6, and presets the address value of the read address counter 7 to the address of the read address Rd + α ₁ at that time, that is, the point X ₂ . Then, the read address counter 7 jumps to the point X ₂ and reads the data c ₁ on the RAM 3 from there. Then, from the signal S ₇ of the signal processing timing generator 21, the multiplexer (C) 9 again RAMs until the address difference between the read address and the write address becomes a _1.
The data S ₆ that is read at the read address is switched so that the output of 3 is directly input to the D / A converter.
Is sent to the decoder 4a as it is.

The data S ₅ and S ₈ are the analog signals d obtained by pitch-converting the input signal a in the decoder 4a and output through the low pass filter 1.

The explanation so far was for _R ＞ _W , but _W ＞
_{The same} can be done for _R.

In the above embodiment, a multiplier was used to multiply the data by the fade function of FIG. 7 (d), but such a calculation is performed by applying the bit shift of the data without using the multiplier. You may do it.

As described above, the pitch conversion is performed by changing the ratio of the read address frequency and the write address frequency on the RAM 3, and the discontinuity of the signal caused thereby is converted into the data currently read at the read address. Prevents click noise by multiplying one of the jump destination data and one of the jump destination data by a decreasing function and an increasing function to fade out and fade in, and then add the two data and output it. It is possible to obtain a good pitch-converted signal.

In the above-mentioned device, since only the difference signal ε of the difference between the input signal a and its predicted value is encoded, the dynamic range of the difference signal stored in the RAM 3 becomes smaller than the dynamic range of the input signal a, and the difference signal The number of bits of ε, that is, the data length can be reduced.

〔effect〕

Thus, according to the present invention, since the difference between the input signal and the predicted value is encoded and stored in the RAM, the dynamic range of the stored digital signal can be reduced and therefore the number of bits of the data can be reduced. The number of gates of each element can be reduced when configuring a specific circuit, and thus an inexpensive device can be provided.

Further, according to the present invention, by setting the prediction coefficient to an appropriate value smaller than 1 during the encoding, error accumulation can be prevented and the dynamic range of the digital signal stored in the RAM can be prevented from being exceeded.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a conventional pitch converter,
FIG. 2 (a) is a block diagram showing the configuration of a pitch converter according to an embodiment of the present invention, (b) and (c) are block diagrams showing the other two cases of the encoder, and FIG. FIG. 4 is a graph showing the principle of DPCM in the invention, FIG. 4 is a graph showing a discontinuity processing waveform when the prediction coefficient is 1, and FIG. 5 is a graph showing a discontinuity processing waveform when the prediction coefficient is 0.95. FIG. 6 is a block diagram of a pitch converter according to another embodiment of the present invention, and FIG. 7 (a).
Is a graph showing the pitch-converted signal and the pitch-converted signal, and (b), (c), and (d) are explanatory diagrams showing the principle and operation thereof. 3 ... Random access memory (RAM), a ... Input signal, b ... Prediction value, ε ... Difference, 2a, 2b, 2c ... Encoder, d ... Analog signal, 4a ... Decoder, _W …… Writing frequency, _R …… Reading frequency, α …… Prediction coefficient, J …… Other location on memory, Ia …… Decrement function, IIa
…… Increment function.

Claims (3)

[Claims] 1. An encoder for encoding a difference between an input signal and a predicted value, a random access memory for temporarily storing the encoded digital signal, and a decoder for converting the digital signal read from the memory into an analog signal. In a pitch converter composed of pitch converting means for changing a ratio of a writing frequency to a memory and a reading frequency, when a prediction value is obtained from an input signal in an encoder and a decoder, the prediction coefficient is smaller than 1 and 0. A pitch converter characterized by being set to a larger value. 2. When processing a discontinuity of a signal that occurs during pitch conversion, when a write address and a read address approach each other on the memory, the read address is jumped to another location on the memory, and one of them fades out. , So that one of them fades in, the data indicated by the current read address and the jump destination data are multiplied by a decreasing function that starts at 1 and ends at 0, and an increasing function that starts at 0 and ends at 1 respectively, and then two The pitch converter according to claim 1, wherein a sum of the data of (1) is used as output data when jumping. 3. In the processing of a discontinuity point of a signal generated at the time of pitch conversion, the means according to the second aspect and the jump destination of the read address are randomized so as to jump to different addresses each time the jump is performed. The pitch converter according to claim 1.