JPS58182700A - Time axis compression/extension apparatus - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a time axis compression/expansion device (hereinafter referred to as a time axis companding device) that converts musical tones, etc., at frequencies t-1j in real time. The present invention provides a time axis compression/expansion device suitable for use when processing signals at the same time axis compression/expansion ratio.

In general, a time-base companding device for audio signals divides an input audio signal into phoneme pieces of tens of milliseconds, further samples the phoneme pieces, and stores them in an analog memory system such as a BBD.
When writing to a buffer memory composed of digital memory such as AM, and reading from this buffer memory, a read clock with a different period from the write clock is used to change the time axis of the input acoustic signal, and as a result, the input acoustic signal It attempts to convert the frequency of a signal. For example, if a time axis companding device is applied to the processing of the acoustic signal OIi transmitted on a recording tape, the frequency of the reproduced acoustic signal can be changed without using methods such as changing the reproduction speed. , the application to so-called karaoke equipment is being considered, and since the input signal only needs to be within the audio band, the application to other audio equipment is also widely considered.

FIG. 1 shows an example of the configuration of a time-base companding circuit. The input acoustic signal (Sin) has frequency components outside the processing band cuffed by an input filter ('LPF) (1), and is sent to an A/D conversion circuit (2). The A/D conversion circuit (2) receives input acoustic signal 4! ! After sampling 4 (S in ), analog-to-digital conversion is performed to convert it into a digital signal. The input audio signal converted into a digital signal is stored in the RAM
The data is written to the buffer memory configured by 1/3) according to the write clock (/w). The digital signal read from the buffer memory 1/bar 3) according to the timing of the read clock (/R) is sent to the D/A converter circuit (
4), it is converted into an analog signal, and is output through an output filter (LPF) (5). At this time, the time-axis pressure of the input acoustic signal (Sin) is set by keeping the writing clock (/W) of the digital signal to the buffer memory (3) constant at 1-1 and changing the heeling clock (/R). As a result, frequency conversion processing of the input sound signal is performed. Address signal for buffer memory (3), write, read switching No. 43, and A/
Each clock signal for the D conversion circuit (2) and D/A conversion circuit (4) is provided by an arithmetic processing circuit (microcomputer).
(6) is created by the clock generation circuit (power) and the write clock generation circuit (8).

A write address counter (9) that creates a write address to the buffer memory (3) from the write clock (/W), a read clock generation circuit OI, and a read address counter αυ that creates a read address from the read clock (/R). , (/W), (/R), and the conversion end signal from the A/D conversion circuit (2) to create a write/read switching signal. ) and a buffer memory (3)
It is composed of an address selector α which switches the address in response to a write/read switching signal. Toward,
The arithmetic processing circuit (micro combinator) (6) smoothly connects the phoneme segments based on the readout clock (/R) and the companding ratio of Chita and the written digital data. Calculate and determine the read address as follows,
The address is read and output to the address counter αυ. The readout black and white generation circuit 0ψ is a voltage controlled oscillator (
The control voltage (f
The oscillation frequency changes according to c). The microcomputer (6) constantly monitors the frequency of the readout clock (/R→), and performs the corresponding processing based on the frequency. are Japanese Patent Application No. 56-129824 (filed on August 19, 1981) and Japanese Patent Application No. 180980 (filed on August 20, 1986), which were filed earlier by the applicant.
) etc., but a detailed explanation will be omitted here.Now, as mentioned above, this type of time-base companding circuit can be used in a wide range of applications for handling audio band signals.

There are many opportunities for application to multi-channel audio signals, such as stereo audio signals. In this case, two time-axis companding circuits are prepared, and the time-axis companding process of the signal is performed for each channel. The companding ratio of each of the four channels is determined by the voltage oJ conversion circuit α Each channel is set independently, but the voltage variable switch α9 is set as shown in Figure 1.
It is difficult to accurately match the companding ratio between each channel, and for example, there may be a difference in pitch between the signals between channels after frequency conversion, which is a practical problem. It is.

The present invention aims to improve this point, and when a plurality of time-base companding circuits are operated in parallel as described above, the main time-base companding circuit is determined, and the main time-base companding circuit is The read clock (/R) is used to operate other time axis companding devices. The present invention will be described below with reference to the drawings.

Figure 2 is an example of the content of the present invention.

That is, the time axis companding circuits for persons α→ and B←η have the same configuration. 2, only the parts directly related to the present invention are shown. The readout clock output from the offset clock generation circuit (18clI) is the normally closed contact (ali+,
(Ai (tj), the clock is input to the read address counter (c) (c), the microcombi crystal (c), and the R/W control circuit cl!l19 (5) at the same time. It is also supplied to the output terminals (to) and (to).

Next, the operation of this embodiment will be explained. In FIG. 2, for example, time axis companding circuit A (1119) is used as a main circuit, and time axis companding circuit B (17) is used as a sub circuit.

Clock output terminal (to) of main circuit A (16) and sub circuit B
Connect the clock input terminal OD of αD using the connection cable ■. Clock input terminal f21) of subcircuit Ba7)
In this case, the connection plug of the connection cable (to) C31)
Normally closed contacts (a) and (b) are opened by inserting O, micro ambiator (c) (c), read address counter (2) (c) and R/W control circuit (e), (c) The main circuit A (the read clock of lE9 is the sub circuit Ba'
7) is input instead of the read clock. Therefore, the companding ratios in the main circuit A (161 and the sub circuit B07) are exactly the same, and the above-mentioned sound distortion between channels does not occur.

In addition, in the above explanation, time axis companding circuit A (lE9 was used as the main circuit, but conversely, time axis companding circuit BQ7) was used as the main circuit, and time axis companding circuit AαQ was used as the sub circuit. The results obtained are the same.

Furthermore, as shown in FIG. 8, when multiple time-base companding circuits are used to target multiple channels of sound IItgir, the clock output terminal (to) of the subcircuit (6) is connected to the subcircuit (6). A connection cable is connected to the clock input terminal (to) of O (b), and further from the clock output terminal (to) of the subcircuit (CjJ (b)) to the clock input terminal (to) of the subcircuit (to) (9). (To), (To), and (41) are connected to the cassette cords, thereby allowing multiple time-axis companding operations to be performed under the same conditions.

As described above, according to the time axis compression/expansion device of the present invention, signals of a plurality of channels can be processed at the same time axis compression/expansion ratio.

[Brief explanation of drawings]

Fig. 1 is a block circuit diagram showing a configuration example of a time axis companding device using 8AM, Fig. 2 is a block circuit diagram of the main components of the time axis compression/expansion device of the present invention, and Fig. 8 is a time axis compression/expansion device. FIG. 7 is a block circuit diagram showing another embodiment of the present invention in which a plurality of circuits are operated in parallel. [)(5)...LPFl(2)...--Mu/DR conversion circuit, (3)...Memory circuit, (4)...
・・・・・・D/A conversion circuit, (610241(c)・
... Arithmetic processing circuit, (7) ... Clock generation circuit, (8) ... Write chroma generation circuit, (9) ... Write address counter ,
(2) (c)...Read address counter, αG (189...Read clock generation circuit, α2cA)...R/W control circuit, a Ken・
...Address Senfter, α (...Voltage variable circuit, αI, group, main time axis compression/expansion circuit% (17
) (to) (b) Gη... sub-time axis compression/expansion circuit, (
20I2]) (To) (To) -1... Clock input terminal, (To) 翰 (C) (G) G43 (C)...
・Clock output terminal, cncihohυ・・・・・・
connection cable.

Claims (1)

[Claims] fl) When sampling an input signal according to a first chromatic clock and sequentially writing it into a storage means, and sequentially reading out nine stored signals written to the storage means according to a second clock,
A plurality of channels are provided with a time axis compression and expansion circuit that compresses and expands the time axis of the input signal by changing the ratio of the frequencies of the first and second clocks, and the second clock of one channel is used as the second clock of the other channel. A multi-channel time axis compression/expansion device characterized by shared use as a clock. (2) The time axis compression/expansion circuit includes a clock input terminal connected to the second four-way circuit via one terminal of a normally closed switch, an internal circuit of the compression/expansion circuit, and a normally closed clock input terminal. A clock output terminal is connected to the other terminal of the closed switch, and the two clock output terminals are output from the chroma output terminal of one channel, and the output terminal is connected to the chroma input terminal of the other channel. Open the normally closed switch of the second clock of the one channel.