JPH0894681A - Apparatus for analyzing frequency spectrum - Google Patents

Abstract

PURPOSE: To prevent higher harmonics generated correspondingly to a digital signal of a minute level from appearing in the analysis result of a frequency spectrum, by converting a digital signal of N bits to be analyzed to a digital signal of M bits showing a relationship of M>N and analyzing the M-bit digital signal. CONSTITUTION: An N-bit digital signal supplied to a terminal 1 is subjected to bit conversion in a bit conversion part 3 in a manner that a product of an analog signal waveform corresponding to the N-bit digital signal is equal to a product of an analog signal waveform corresponding to an M-bit digital signal holding a relationship of M>N within an error range of ±0.5LSB to a resolution of 1LSB which is a fraction of the Nth power of 2 between an analog signal restored correspondingly to the N-bit digital signal and an analog signal used to obtain the N-bit digital signal. Then, a frequency spectrum is analyzed by a frequency spectrum-analyzing part 4 for the M-bit, digital signal output from the conversion part 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency spectrum analyzer for analyzing a frequency spectrum using a digital signal.

[0002]

2. Description of the Related Art When digitizing an audio signal or an image signal, it has a predetermined number of bits in accordance with a standard determined in consideration of fidelity of transmission and recording / reproduction, apparatus price, and various other conditions. It is well known that digital signals are being generated, and it is also well known that many proposals have been made regarding various high-efficiency coding methods applied in transmission, recording and reproduction of digital signals. Therefore, for example, high-efficiency coding (data compression) of digital audio signals is in the stage of practical application, and in so-called DCC, MD, DAB, etc., human hearing characteristics (hearing masking effect and minimum audible limit characteristics). Is used to reduce the redundancy. By the way, as described above, if the digital signal of a predetermined number of bits according to a specific standard is, for example, an N-bit digital signal, the digital signal is an analog signal with a resolution of 1 / N of 2 Since it is in a state of being converted into a digital signal, it is natural that a minute signal portion cannot be restored with a fineness of resolution equal to or higher than the Nth power of 2 described above. It is desired to restore a minute signal portion with a fineness equal to or greater than the resolution determined by the number of bits of M, and there is also a proposal for converting it into an M-bit digital signal having a relationship of M> N. It has been done.

[0003]

As described above, since the resolution of the digital signal is determined by the number of bits of the digital signal,
Even if the original analog signal is a sine wave signal, it is reproduced as a square wave signal when it is converted into a digital signal and then restored to an analog signal even if the original analog signal is a sine wave signal. Will be.
Since the square wave signal is composed of the fundamental wave and the innumerable harmonics, the frequency spectrum of the digital signal is analyzed by, for example, FFT or a digital band pass filter group. If it is a digital signal corresponding to an analog signal of a minute signal level, a harmonic component that originally did not exist in the analog signal of the original signal will appear in the frequency analysis result. Therefore, for example, in high-efficiency encoding (data compression) of the digital audio signal described above, a problem occurs even when the data compression is controlled according to the result of the frequency spectrum analysis of the digital signal.

[0004]

The present invention is a frequency spectrum analyzer for analyzing an N-bit digital signal obtained by converting an analog signal into a digital signal with a resolution of 1 to the Nth power of 2 into a frequency spectrum. Of the analog signal restored corresponding to the N-bit digital signal and the analog signal used to obtain the N-bit digital signal. Within the error range of ± 0.5 LSB for a resolution of 1 LSB, it corresponds to the integrated value of the analog signal waveform corresponding to the above-mentioned N-bit digital signal and the M-bit digital signal in the relationship of M> N. A bit number conversion unit that performs bit number conversion so that the integrated value of the analog signal waveform becomes equivalent, and an M-bit digital signal output from the bit number conversion unit described above. A frequency spectrum analyzing unit for analyzing a frequency spectrum into a frequency spectrum, and a means for setting a dynamic range of an output signal from the frequency spectrum analyzing unit to a dynamic range of an N-bit digital signal, and an analog signal. A frequency spectrum analyzer for analyzing an N-bit digital signal obtained by converting it into a digital signal at a resolution of 1 / N of 2 and an analog signal at a resolution of 1 / N of 2 An N-bit digital signal obtained by converting the digital signal to an analog signal used to obtain the N-bit digital signal,
A resolution of 1 / N of 2 existing between the analog signal obtained by restoring the N-bit digital signal and 1LSB
Within the error range of ± 0.5 LSB,
The number of bits is set such that the integrated value of the analog signal waveform corresponding to the bit digital signal and the integrated value of the analog signal waveform corresponding to the M-bit digital signal having a relation of M> N are equivalent. In order to perform the conversion, for the N-bit digital signal to be subjected to the bit number conversion, information on the change mode of the difference between the N-bit digital signals which are separated by one adjacent sampling period is detected. , The adjacent 1 in the N-bit digital signal
According to the change mode of the difference between the N-bit digital signals separated by the sampling period, (M−N) -bit additional code information set so as to correspond to the analog signal waveform is generated, and the additional code information is generated. A bit number converter for converting the bit number so that the (M-N) -bit additional code information is continuously generated at the least significant digit of the N-bit digital signal to generate an M-bit digital signal; The frequency spectrum analysis unit that analyzes the frequency spectrum of the M-bit digital signal output from the bit number conversion unit, and the dynamic range of the output signal from the frequency spectrum analysis unit is the dynamic range of the N-bit digital signal. There is provided a frequency spectrum analyzing apparatus comprising:

[0005]

1 / N of 2 existing between the analog signal used to obtain the N-bit digital signal and the analog signal obtained by restoring the N-bit digital signal
Within the error range of ± 0.5 LSB for the resolution 1 LSB of M
The N-bit digital signal, which is the target of bit number conversion, is made to have a sequential adjacent sampling period by making the integration value of the analog signal waveform corresponding to the bit digital signal equivalent. It is set so as to correspond to the analog signal waveform on the basis of the result of detecting the information of the change mode of the difference between the N-bit digital signals (M-
N) bit additional code information is continued to the least significant digit of the N-bit digital signal, the number of bits is converted into the M-bit digital signal, and the M-bit digital signal in the relation of M> N. The frequency spectrum is analyzed by FFT or a digital band pass filter group. The analysis result is taken out in the dynamic range of the N-bit digital signal.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The specific contents of the frequency spectrum analyzer of the present invention will be described in detail below with reference to the accompanying drawings. FIG. 1 is a block diagram showing a schematic configuration of a frequency spectrum analyzer of the present invention, FIGS. 2 and 3 are block diagrams showing a partial specific configuration example of a component of the frequency spectrum analyzer of the present invention, and FIGS. 13 is a diagram for explaining the operation, FIG.
FIG. 4 is a diagram illustrating an output state of a frequency spectrum analyzer. FIG. 1 is a block diagram illustrating a schematic configuration of a frequency spectrum analyzer of the present invention. Reference numeral 1 denotes an N-bit digital signal obtained by converting an analog signal into a digital signal with a resolution of 1 / N of 2 An input terminal, 2 is an output terminal for N-bit dynamic range output data output from the frequency spectrum analyzer, 3 is a bit number conversion unit,
Reference numeral 4 is a frequency spectrum analysis unit, 5 is a display unit of N-bit dynamic range output data output from the frequency spectrum analysis device, 6 is a delay circuit, 7 is an addition circuit, and 8
Is a signal waveform conversion mode detection unit, 9 is an (M-N) bit signal generation unit, 10 is a variable delay unit, and 11 is a delay control signal generation unit.

The bit number converter 3 in FIG.
An N-bit digital signal supplied to the N-bit digital signal between the analog signal restored corresponding to the N-bit digital signal and the analog signal used to obtain the N-bit digital signal. Within the error range of ± 0.5 LSB for a resolution 1 LSB of 1 / N of 2 which is M, there is a relation of M> N with the integral value of the analog signal waveform corresponding to the N-bit digital signal. This is a component having a function of performing bit number conversion so that the integrated value of an analog signal waveform corresponding to a bit digital signal becomes equivalent. Based on the result of detecting the information of the change mode of the difference between the N-bit digital signals which are sequentially separated by one adjacent sampling period. A configuration in which an additional digital signal of (M−N) bits set so as to correspond to an analog signal waveform is continued to the least significant digit of the N-bit digital signal to generate an M-bit digital signal. It is said that Therefore, first, the configuration principle and operation principle of the above-described bit number conversion unit 3 will be described with reference to FIGS. 6 to 10.

The points a to n in FIG.
A curved line S, which is connected by a thick solid line, such as → c → d → e → f → g → h → i → j → k → l → m → n, shows an analog signal at a specific sampling period Ts (sample). For each reciprocal of the quantization frequency fs), a state of change of a digital value obtained by sampling and quantizing at a resolution of 1 / N of 2, that is, a resolution of 1 LSB of N bits is illustrated. The analog signal of the original signal that produces the digital value as shown by the curve S is the one existing in the area surrounded by the broken line in FIG. Therefore, between the analog signal used to obtain the N-bit digital signal obtained by converting into the digital signal and the analog signal obtained by restoring the N-bit digital signal, N of 2 is obtained.
An error within ± 0.5 LSB is included for a resolution of 1 LSB of 1 / multiplier. In FIG. 6, t1, t2, t3, ... Are the time points at which the sequential sampling is performed, and the time points t1, t2, t2,
The time Ts between adjacent sampling times at t3 ... Shows the sampling period.

In the bit number conversion unit 3, the N-bit digital signal obtained by converting the analog signal into a digital signal with a resolution of 1 / N of 2 is subjected to bit number conversion,
In the case of obtaining an M-bit digital signal having a relation of M> N, the value of the N-bit digital signal is changing such that it gradually increases or decreases on the time axis. , The period during which the value of the N-bit digital signal for each successive sampling period continues in the same state
The length of the (interval) (indicated by the number of sampling periods) and
An N-bit digital signal which is adjacent to the above period and differs from the value of the N-bit digital signal in the above period by a resolution of 1 LSB of 1 / N of 2 is used for each successive sampling period. The length of the period (section) continued as an N-bit digital signal is compared.

When the period lengths of the two adjacent sections are different from each other, the midpoint of the section having the shorter period length of the two adjacent sections and the section having the longer period length of the two adjacent sections are different from each other. An (M-N) -bit additional digital signal capable of representing a straight line connecting the half of the short period length and the point at the corresponding position from the boundary between the two sections is generated, and the adjacent digital signal is generated. When the two sections have the same period length, an additional digital signal of (M−N) bits that can represent a straight line connecting the midpoints of the sections in the two sections is generated, and as described above. The generated additional digital signal is continued to the least significant digit of the N-bit digital signal to generate an M-bit digital signal. Also,
When the value of the N-bit digital signal is the N-bit digital signal in the section corresponding to the extreme value, it is predetermined (MN) in correspondence with the period length of the section. The bit-added digital signal is continued to the least significant digit of the N-bit digital signal to generate an M-bit digital signal.

In FIG. 7A, the (M-N) -bit additional digital signal is connected to the least significant digit of the N-bit digital signal as described above to generate an M-bit digital signal. FIG. 7A illustrates a stepwise waveform curve Sn having a thick solid line in FIG. 7A, which is obtained by converting an analog signal into a digital signal with a resolution of 1 / N of 2 It illustrates the change of the digital signal of the bit on the time axis, and the curve S (m-
n) illustrates the change on the time axis of the additional digital signal of (M−N) bits obtained as described above.

In FIG. 7A, points a → b → c → d →
A curve Sn indicated by e → f shows a change mode on the time axis regarding the N-bit digital signal. As described above, in the frequency spectrum analyzer method and the information signal processing device of the present invention, the value of the N-bit digital signal changes in a sequentially increasing tendency or a decreasing tendency on the time axis. In this case, the length of a period (section) in which the value of the N-bit digital signal for each successive sampling cycle is the same (for example, the period length of the section indicated by point a → b, point c) → Duration of the section shown between d,
(The period length of the section indicated between points e → f) is compared for each two adjacent sections, and when the two adjacent sections have the same period length, The additional digital signal of (M−N) bits shown as a straight line connecting the midpoints of the sections is generated, and this state is the section a → b and the section c in (a) of FIG. It is shown in the part of two sections of → d. That is, in the two sections, section a → b and section c → d, which exemplify the case where two sections having the same period length are continuous, the midpoint of the section a → b An (M−N) -bit additional digital signal indicated by a straight line connecting the position h and the midpoint position i of the section in the section c → d is generated.

Next, when the value of the N-bit digital signal changes on the time axis with a tendency to increase or decrease on a time axis basis, the N-bit digital signal for each successive sampling period is changed. The lengths of the periods (sections) that continue under the same value of are compared for each two adjacent sections, and when the two adjacent sections have different lengths,
In the above two sections, the midpoint of the section with the shorter period length and the above-mentioned 2 in the section with the longer period length
This is to generate an additional digital signal of (M−N) bits which can represent a straight line that connects the point of the position corresponding to ½ of the short period length from the boundary of one section. 7 (a), it is shown in the section of two sections, section c → d and section e → f. That is, since the period length in the two sections of the section c → d and the section e → f is longer in the section e → f, the section length in the two sections c → d and e → f is longer. Of the middle point position i in the section c → d having a shorter period length and the section e → f having a longer period length in the above two sections c
1/2 of the short period length described above from the boundary d of → d and e → f
Is shown as a straight line connecting the point l at the corresponding position (M
-N) Generate an additional digital signal of bits.

Next, when the period (section) in which the value of the N-bit digital signal for each successive sampling cycle is the same is continuous and is an extreme value section, it corresponds to the period length of that section. A preset (M−N) -bit additional digital signal is continuously added to the lowest digit of the above-mentioned N-bit digital signal for M.
Since a bit digital signal is generated, it is set in advance in FIG. 7B and each of FIGS. 8 to 10 in correspondence with the period length of the extreme value section described above. An example of an additional digital signal of power (M−N) bits is shown. In FIG. 7B, the extreme value section based on the value of the N-bit digital signal should be set in advance (M−
It is a figure for demonstrating how an N) bit additional digital signal is determined. FIG. 7B shows a case where the period length of the N-bit digital signal corresponding to the extreme value is one sampling period Ts and the period length of the above period is two sampling periods Ts. And.

In FIG. 7 (b), the (M−N) -bit additional digital signal when the period length of the section corresponding to the extreme value of the N-bit digital signal is one sampling period Ts is: O → indicating a section of a period length of one sampling period Ts by an N-bit digital signal corresponding to the extreme value o →
The area of a rectangle of a thin solid line of p → q → r is set to be substantially the same as the area, that is, a region surrounded by a thick solid line in the drawing and shown by hatching. It Further, in FIG. 7B, when the period length of the section corresponding to the extreme value by the N-bit digital signal is 2 sampling periods 2Ts, the (MN) -bit additional digital signal is The area of the thin solid line rectangle of s → u → v → z, which indicates the section of the period length of 2 sampling periods 2Ts by the N-bit digital signal corresponding to the value, and the area of substantially the same area, that is, the figure The area is surrounded by a thick solid line and is set as shown by a hatched area.

As described above, the value of the N-bit digital signal originally has an N-bit resolution of 1 LSB.
Error of ± 0.5 LSB (see +0.5 LSB and −0.5 LSB shown in (b) of FIG. 7) is included, the above-mentioned extreme value due to the N-bit digital signal and When setting the additional digital signal of (M−N) bits that should be set for each period length of the corresponding section, as the area of the section corresponding to the extreme value of the N-bit digital signal, The thin solid line rectangle described above (the thin solid line rectangle indicated by o → p → q → r, or s → u →
± 0.5 described above for the thin solid line rectangle v → z)
A rectangle whose height changes within the range of LSB (for example, o →
p '→ q' → r, o → p "→ q" → r, or s → u '
(→ v '→ z, s → u ”→ v” → z, etc.)
May be set as shown by a region having substantially the same area as the area.

FIG. 8 shows an additional digital signal of (M−N) bits set corresponding to the case where the period length of the N-bit digital signal corresponding to the extreme value is one sampling period Ts. It is the figure which illustrated up to the additional digital signal of (M-N) bit set corresponding to the case where the period length by the N-bit digital signal corresponding to an extreme value is 9 sampling periods 9Ts, Further, FIG. 9 is set corresponding to the case where the period length of the section by the N-bit digital signal corresponding to the extreme value is 10 sampling periods 10Ts (M−
From the (N) -bit additional digital signal, the period length of the section by the N-bit digital signal corresponding to the extreme value is set corresponding to the case of 14 sampling periods 14Ts (M-
FIG. 10 is a diagram exemplifying up to N) bit additional digital signals. Further, FIG. 10 shows that the period length of the section by the N bit digital signal corresponding to the extreme value is 15 sampling periods 15 Ts.
Corresponding to the case where the period length of the section by the N-bit digital signal corresponding to the extreme value is 16 sampling periods 16Ts from the (M−N) -bit additional digital signal set corresponding to the case of It is the figure which illustrated to the additional digital signal of the set (M-N) bit.

The (M-N) -bit additional digital signal shown in FIGS. 8 to 10 is the (M-N) -bit signal generator described later with reference to FIGS. 1 and 3. 9
The waveform data generating ROM provided in the waveform data generating section 91 in the middle extreme value section is stored in the waveform data generating ROM, and the section by the N-bit digital signal corresponding to the extreme value is stored in the waveform data generating ROM. When the period length is supplied as address information, a predetermined (M-N) -bit additional digital signal corresponding thereto is read out and used as will be described later.

In the bit number conversion unit 3 shown in FIG. 1, the N-bit digital signal is delayed by the delay circuit 6.
Is delayed by a predetermined time and then supplied to the adder circuit 7. As will be described later with reference to FIG. 2, it includes a signal waveform change information generation unit 81, a signal waveform change mode information generation unit 82, and a signal waveform change interval information generation unit 83. The signal waveform change mode detection unit 8 detects the signal waveform change mode information and the signal waveform change interval information for the N-bit digital signal supplied through the input terminal 1.
The (MN) bit signal generator 9 outputs the detected information.
And the variable delay unit 10.

In the (M−N) -bit signal generator 9, when the value of the N-bit digital signal described above changes in a sequentially increasing tendency or a decreasing tendency on the time axis, , The length (indicated by the number of sampling cycles) of a period (section) in which the value of the N-bit digital signal for each successive sampling cycle continues in the same state is compared for adjacent sections, and When the period lengths of the two sections differ from each other, the midpoint of the section having the shorter period length between the adjacent two sections and the boundary between the two sections having the longer period length From the above, generates an additional digital signal of (M−N) bits that can represent a straight line connecting the half of the short period length and the point at the corresponding position, and supplies it to the variable delay unit 10; Two adjacent sections have the same period length Can may represent a straight line connecting the midpoints of each other section in the two sections (M-
The N) -bit additional digital signal is generated and supplied to the variable delay unit 10, and the value of the N-bit digital signal is the N-bit digital signal in the section corresponding to the extreme value. In such a case, an additional digital signal of (M−N) bits determined in advance corresponding to the period length of the section is output from the waveform data generating ROM provided in the waveform data generating section 91 of the extreme value section. It is read and supplied to the variable delay unit 10.

In the variable delay unit 10 supplied with the (M-N) -bit additional digital signal generated by the (M-N) -bit signal generating unit 9, the above-mentioned (M-N) -bit additional digital signal is output. In the adder circuit 7, an additional digital signal of (M−N) bits is added with a time delay required to generate a digital signal of M bits in succession to the least significant digit of the predetermined digital signal of N bits. Give to. The time delay amount in the variable delay unit 10 is obtained by controlling the variable delay unit 10 by the delay control signal generated by the delay control signal generation unit 11. That is, the delay control signal generation unit 11 uses the delay control signal based on the signal waveform change information, the signal waveform change mode information, the signal waveform change interval information, and the like supplied from the signal waveform change mode detection unit 5. Is generated and is supplied to the variable delay unit 10. Therefore, from the adder circuit 7 described above, the (M-N) -bit signal generated by the (M-N) -bit signal generating unit 9 is placed at the lowest digit of the N-bit digital signal that is the target of the information signal processing. The M-bit digital signal in the state where the additional digital signal of is continuous is transmitted.

Next, with reference to FIG. 2, a concrete configuration mode and operation of the detecting section 8 of the mode of changing the signal waveform will be described. In FIG. 2, the detection unit 8 for detecting the variation of the signal waveform is
Signal waveform change information generation section 81, signal waveform change mode information generation section 82, and signal waveform change interval information generation section 8
3 and 3. The N-bit digital signal to be processed by the information signal is supplied to the input terminal 12 of the signal waveform change detecting unit 8, and the clock signal pulse Pfs is supplied to the input terminal 13. As the clock signal pulse Pfs described above, a pulse having the same repetition frequency as the sampling frequency fs used when generating the digital signal targeted for the information signal processing is used. If the digital signal of interest is an acoustic signal,
As the clock signal pulse Pfs, for example, 44.1
Pulses with a repetition frequency fs of KHz are used.

The N-bit digital signal to be subjected to the information signal processing, which is supplied to the signal waveform change information generating section 81 through the input terminal 12 of the signal waveform change mode detecting section 8, is the magnitude comparator 812. At A
It is given to the input terminal and the data terminal of the D-type flip-flop 811.
The clock signal Pfs is supplied to the clock terminal 11 of the input terminal 11 through the input terminal 13. The B input terminal of the magnitude comparator 812 is supplied with the Q terminal output of the D-type flip-flop 811. Therefore, the D-type flip-flop 811 described above is
To the clock terminal of the D-type flip-flop 811, via the input terminal 13, a clock signal Pf which is sequentially provided for each sampling period.
Each time s is supplied, the N-bit digital data given to the data terminal of the D-type flip-flop 811 one sampling period before is output from the Q-terminal of the D-type flip-flop 811 described above, It will be input to the B input terminal of the magnitude comparator 812.

The magnitude comparator 812 described above.
As a result, the size of the N-bit digital data A supplied to its A input terminal and the size of the N-bit digital data B supplied to its B input terminal are compared, and the digital data A is When it is larger than the digital data B, only the output terminal A> B is the output H in the high level state, and the other output terminals A <B and the output terminal A = B are both the output L in the low level state. When the digital data A and the digital data B in the N-bit digital data supplied to the input terminals A and B are equal, only the output terminal A = B is the output H in the high level state. , The other output terminals A> B and the output terminals A <B are both set to the output L in the low level state, and the digital data in the N-bit digital data supplied to the input terminals A and B is further set. If the B side is larger than the digital data A, the output terminal A <only the output H of the high-level state B, the other output terminal A> B and the output terminal A = B
It is possible to use the magnitude comparator 74HC85 in an operation mode in which both of the above are output L in the low level state.

The output terminal A of the magnitude comparator 812 in the signal waveform change information generating section 81>
The output from B and the output from the output terminal A <B are supplied to the exclusive OR circuit 813. The output terminal A of the magnitude comparator 812 described above is also used.
The output from B is the signal waveform change mode information generation unit 82.
Is also supplied to the data terminal of the D-type flip-flop 823. Then, the output of the exclusive OR circuit 813 described above is set to a high level state H in which one of the output from the output terminal A> B and the output from the output terminal A <B of the magnitude comparator 812 is at a high level. When it becomes, it becomes the high level state H. In FIG. 2, the output from the output terminal A> B of the magnitude comparator 812 and the output from the output terminal A <B are supplied to the exclusive OR circuit 813. 81
Even if an OR circuit is used instead of 3, the same operation as in the case of using the exclusive OR circuit 813 described above (from the magnitude comparator 812 in FIG. 2 to the two input terminals of the exclusive OR circuit 813) is performed. This is because the state of being given a high-level signal at the same time does not occur).

The output signal from the exclusive OR circuit 813 is supplied to the AND circuit 814, and the AND circuit 814 is supplied with Pfs bar as a gate pulse. The gate pulse Pfs bar is a pulse having a phase difference of 180 degrees with the clock signal pulse Pfs at the same repetition frequency as the clock signal pulse Pfs described above. Therefore, the AND circuit 814 described above
In the case where the values of the adjacent digital data on the time axis are different from each other by one sampling period in the N-bit digital signal, the clock signal CLK is output at the timing of the gate pulse Pfs bar. Will be.

In response to the change on the time axis of the N-bit digital signal supplied to the input terminal 12 of the signal waveform change mode detecting section 8, the signal in the signal waveform change mode detecting section 8 is changed. The state of generation of the clock signal CLK output from the AND circuit 814 of the waveform change information generation unit 81 will be described below with reference to FIG. In FIG. 4, a, b, h ... O described in the upper part of the drawing are N bits which are the target of the information signal processing supplied to the input terminal 12 of the detection unit 8 of the change state of the signal waveform. Pfs1, Pfs2, P shown at the bottom of FIG.
fs3 ... Pfs19 are clock signal pulses Pfs supplied to the input terminal 13, and Pfs1 bar,
Pfs2 bar, Pfs3 bar ... Pfs19 bar are gate pulses supplied to the AND circuit 814.

The above-mentioned signal waveform change information generating section 81
In addition, the N-bit digital signal, which is the target of the information signal processing and is supplied through the input terminal 12, is given to the A input terminal of the magnitude comparator 812 and the data terminal of the D-type flip-flop 811. Then, the clock terminal of the D-type flip-flop 811 is supplied with the serial clock signals Pfs1, Pfs2, Pfs3 ... The Q terminal of outputs the N-bit code information (digital data) given to the data terminal of the D-type flip-flop 811 one sampling period Ts before, and outputs it to the B input terminal of the magnitude comparator 812. Is entered.

As shown in FIG. 4 on the time axis, the signal level of the N-bit digital signal which is the object of the information signal processing supplied through the input terminal 12 is
Supposing that there is a change such as B, C ... At the time of the clock signal Pfs1, the magnitude comparator 812 is detected.
, And the data terminal of the D-type flip-flop 811 are provided with digital data of the signal level "a". The digital data given from the terminal is indefinite "?". So, at the time of the clock signal Pfs1,
The output from the magnitude comparator 812 is indeterminate “?”.

Next, at the time after one sampling period Ts from the time of the clock signal Pfs1, that is, at the time of the clock signal Pfs2, the magnitude comparator 8
A input terminal of 12 and the D-type flip-flop 81
The digital data of the signal level “b” is given to the data terminal of No. 1, and the B input terminal of the magnitude comparator 812 has the Q of the D-type flip-flop 811.
Digital data of signal level "a" is given from the terminal. Therefore, at the time of the clock signal Pfs2, the output from the magnitude comparator 812 is output terminal A>
Only B is in the high level state. Only the output terminal A> B of the magnitude comparator 812 is in the high level state because the digital signal tends to increase on the time axis (in FIG. 5, the digital signal tends to increase on the time axis. Are indicated by the symbols “>” and “U.” In addition, the display method such as “A> B (>, U)” is adopted in FIG. .

As described above, at the time of the clock signal Pfs2, the output terminal A of the magnitude comparator 812>
Since only B is in the high level state, the output of the exclusive OR circuit 813 is in the high level state at the time of the clock signal Pfs2. Then, the AND circuit 814 to which the output of the magnitude comparator 812 is applied outputs the clock signal CLK2 in the high level state at the time when the gate pulse Pfs2 bar is applied (see FIG. 4).

Next, the clock signal Pf after one sampling period Ts from the time of the clock signal Pfs2 described above.
At the time of s3, the digital data of the signal level "b" is given to the A input terminal of the magnitude comparator 812 and the data terminal of the D-type flip-flop 811, but at this time, the magnitude comparator 81
2 to the B input terminal, the D-type flip-flop 811
Since the digital data given from the Q terminal of the signal is also the signal level "b", the output from the magnitude comparator 812 at the time of the clock signal Pfs3 is in the high level state only at the output terminal A = B, and therefore the exclusive The output of the OR circuit 813 is the clock signal P.
Even when the gate pulse Pfs bar is given to the AND circuit 814 which is in the low level state at the time of fs3, and thus the output of the low level state from the magnitude comparator 812 is given, it is in the high level state. The clock signal CLK is not output.

Next, the clock signal Pfs after one sampling period Ts from the time of the clock signal Pfs3 described above.
At time 4, digital data of signal level “C” is given to the A input terminal of the magnitude comparator 812 and the data terminal of the D-type flip-flop 811, and the B input terminal of the magnitude comparator 812 is input to the D-type flip-flop. Digital data having a signal level "b" is given from the Q terminal of the block 811. Therefore, at the time of the clock signal Pfs4, the output from the magnitude comparator 812 is in the high level state only at the output terminal A> B. As described above, the clock signal Pf
At time s4, since only the output terminal A> B of the magnitude comparator 812 is in the high level state, the output of the exclusive OR circuit 813 outputs the clock signal P
The AND circuit 814, which is in the high level state at the time of fs4 and receives the output of the magnitude comparator 812, outputs the clock signal CLK3 in the high level state at the time when the gate pulse Pfs4 bar is applied ( (See FIG. 4).

At the time of the clock signal Pfs5 after one sampling period Ts from the time of the clock signal Pfs4, the signal level "H" is applied to the A input terminal of the magnitude comparator 812 and the data terminal of the D-type flip-flop 811. The digital data given from the Q terminal of the D-type flip-flop 811 to the B input terminal of the magnitude comparator 812 at this time is also the signal level “C”, so the magnitude at the time of the clock signal Pfs5 The output from the comparator 812 is output terminal A =
Since only B becomes the high level state and the output of the exclusive OR circuit 813 becomes the low level state at the time of the clock signal Pfs5, even if the gate pulse Pfs bar is given to the AND circuit 814, The clock signal CLK in the high level state is not output.

Next, the clock signal Pfs after one sampling period Ts from the time of the clock signal Pfs5 described above.
At time 6, digital data of signal level “d” is given to the A input terminal of the magnitude comparator 812 and the data terminal of the D-type flip-flop 811, and the B input terminal of the magnitude comparator 812 is fed to the D-type flip-flop. Digital data having a signal level “C” is given from the Q terminal of the block 811. Then, at the time of the clock signal Pfs6, the output from the magnitude comparator 812 is in the high level state only at the output terminal A> B, so that the output of the exclusive OR circuit 813 is at the high level at the time of the clock signal Pfs6. Then, the AND circuit 814, to which the output of the magnitude comparator 812 is applied, becomes the gate pulse P.
At the time when the fs6 bar is given, the high-level clock signal CLK4 is output (see FIG. 4).

Next, the clock signal Pf after one sampling period Ts from the time of the clock signal Pfs6 described above.
At time s7, digital data of the signal level “e” is given to the A input terminal of the magnitude comparator 812 and the data terminal of the D-type flip-flop 811, and the B input terminal of the magnitude comparator 812 is supplied to the D-type flip-flop. Digital data of signal level "d" is given from the Q terminal of the block 811. Therefore, at the time of the clock signal Pfs7, the output from the magnitude comparator 812 is in the high level state only at the output terminal A <B.

Then, the magnitude comparator 81
The reason why only the output terminal A <B of 2 becomes the high level is that the digital signal tends to decrease on the time axis (see FIG.
In the figure, the signs of “<” and “D” indicate that the digital signal tends to decrease on the time axis. Also,
Even in FIG. 4, the display method such as “A <B (<, D)” is adopted). The output of the exclusive OR circuit 813 is brought to a high level state at the time of the clock signal Pfs7, and the output of the magnitude comparator 812 is applied to the AND circuit 813.
14 is at the time when the gate pulse Pfs7 bar is given,
The clock signal CLK5 in the high level state is output (see FIG. 4).

The clock signal Pfs8 shown in FIG.
The operation of each section of the signal waveform change information generating section 81 performed at each time of ~ Pfs19 is performed by clock signals Pfs1 to Pfs7.
Since it can be easily understood from the description of the operation of each section of the signal waveform change information generation section 81 performed at each time, detailed description thereof will be omitted. As can be understood from the above description, the sequential clock signals Pfsi (where i is 1, 2, 3, ...) Given at each sampling period.
Magnitude comparator 81 performed at every time
Only one of the output terminal A> B or the output terminal A <B of the comparison output from 2 is in the high level state.
This is only when the signal level of the N-bit digital signal, which is the object of information signal processing and is supplied through the input terminal 12, tends to increase or decrease on the time axis.

Then, from the AND circuit 814 of the signal waveform change information generating section 81, the clock signal CLKi (however,
i is 1, 2, 3, 4 ...) is output when only one of the output terminal A> B or the output terminal A <B of the magnitude comparator 812 is at a high level,
That is, this is when the signal level of the N-bit digital signal which is the target of the information signal processing supplied through the input terminal 12 tends to increase or decrease on the time axis.

As described above, the clock signal CLKi (where i is 1, 2, 3, 4 ...) Transmitted from the AND circuit 814 of the signal waveform change information generating section 81 is the signal waveform change mode information. The clock terminals of the D-type flip-flops 823 to 825 of the generation unit 82 and the D-type flip-flops 839 to 84 of the generation unit 83 of the signal waveform change interval information.
1 clock terminal. The D-type flip-flop 823 of the signal waveform change mode information generation unit 82 described above.
.About.825 read the digital data supplied to the data terminals of the flip-flops 823 to 825 at the time when the clock signal CLK is given, and D of the signal waveform change interval information generating unit 83. Type flip-flops 839 to 841 are connected to the clock signal C.
At the time when LK is given, the D-type flip-flop 839
The digital data supplied to the data terminals at ~ 841 are read.

The signal appearing at the output terminal A> B of the magnitude comparator 812 of the signal waveform change information generating section 81 is applied to the data terminal of the D-type flip-flop 823 of the signal waveform change mode information generating section 82. Since it is supplied, the D-type flip-flop 823 receives the sequential clock signal CLKi.
(However, each time i is 1, 2, 3, 4 ...), the above-described sequential clock signal CLKi (where i is
, 1, 2, 3, 4 ...) When the magnitude comparator 812 of the signal waveform change information generation unit 81
The state (high level state or low level state) of the signal appearing at the output terminal A> B at is read.

At the time of generation of the above-mentioned sequential clock signals CLKi (where i is 1, 2, 3, 4 ...), it appears at the output terminal A> B of the magnitude comparator 812 of the signal waveform change information generating section 81. Whether the state of the signal is a high level state or a low level state depends on whether the digital signal at the time of generation of the sequential clock signals CLKi (where i is 1, 2, 3, 4 ...) It is determined depending on whether the time axis has an increasing tendency or the time axis has a decreasing tendency.
When the digital signal at the time of occurrence of i (where i is 1, 2, 3, 4 ...) Has an increasing tendency on the time axis, a signal appearing at the output terminal A> B of the magnitude comparator 812. Is a high level state, and conversely to the above, the digital signals at the time of generation of sequential clock signals CLKi (where i is 1, 2, 3, 4 ...) If there is a decreasing tendency, the magnitude comparator 812
The state of the signal appearing at the output terminal A> B in is at a low level.

The above points will be described below with reference to FIGS. 4 and 5. That is, the digital signal at the time of generation of the sequential clock signals CLKi (where i is 1, 2, 3, 4, ...) Has a tendency to increase on the time axis, and the clock signal CLK (gate pulse Pfs bar). At this time, the signal in the high level state is the D-type flip-flop 8 in the signal waveform change mode information generating section 82.
23, the numbers of the clock signal CLK shown in FIGS. 4 and 5 are 2 to 4, 12 to 14, 17, 18,
21 to 27 (the time of the clock signal CLK indicated by the upward arrow in FIG. 4), and the sequential clock signals CLKi (where i is 1, 2, 3, 4 ...)
The digital signal at the time of the occurrence of the signal tends to decrease on the time axis, and at the time of the clock signal CLK (gate pulse Pfs bar), the signal in the low level state is the signal waveform change mode information generation unit 82. Are read into the D-type flip-flop 823 in which the numbers of the clock signal CLK shown in FIGS. 4 and 5 are 5 to 11, 15, 16 and
19 and 20 (the time of the clock signal CLK indicated by the downward arrow in FIG. 4).

As described above, the sequential clock signals CLKi
(However, every time i is 1, 2, 3, 4 ...),
The signals sequentially supplied to the data terminals of the D-type flip-flops 823 in the signal waveform change mode information generation section 82, that is, the output terminal A of the magnitude comparator 812 of the signal waveform change information generation section 81>
The signal appearing at B is sequentially transferred to the data terminals of the D-type flip-flops 824 and 825 each time a sequential clock signal CLKi (where i is 1, 2, 3, 4 ...) Is supplied. Go, but the state is "DFF823 in FIG.
Input ”,“ output of DFF823 ”,“ output of DFF824 ”, and“ output of DFF825 ”. In addition, "U" described in the above column means a high level state, and "D" described in the column means a low level state.

The output of the D-type flip-flop 823 and the output of the D-type flip-flop 824 of the signal waveform change mode information generating section 82 are given to the exclusive OR circuit 826, and also the output of the D-type flip-flop 824. The output and the output of the D-type flip-flop 825 are given to the exclusive OR circuit 827, and the exclusive OR circuit 8 is used.
The outputs of 26 and 827 are the "exclusive OR circuit 8" in FIG.
26 output ”and“ output of exclusive OR circuit 827 ”. Note that "1" in this column means a high level state, and "0" shows a low level state. “D”, “L”, “F”, “T”, “S” shown in the column of “Position of extreme value of signal waveform” in FIG.
The display of “N” or the like indicates the N-bit digital signal which is the target of the information signal processing and is supplied to the input terminal 12 of the detection unit 8 of the signal waveform change mode shown in the upper part of FIG. Among the symbols indicating the signal level, the position of the signal level corresponding to the extreme value of the signal waveform is shown.

Then, the digital data of the extreme position of the signal waveform in the N-bit digital signal to be subjected to the information signal processing, which is supplied to the input terminal 12 of the signal waveform change detecting section 8, is A clock having a clock signal number smaller by 2 than the clock signal CLK number when the output of the exclusive OR circuit 826 of the generation unit 82 in the signal waveform change mode information is in the high level state “1”. It can be seen from the signal CLK that the signal is read into the D-type flip-flop 823. In addition, the digital data of the extreme position of the signal waveform in the N-bit digital signal that is supplied to the input terminal 12 of the detection unit 8 of the signal waveform change mode and is subjected to the information signal processing is described above. A clock signal having a clock signal number that is smaller by 3 than the clock signal CLK number when the output of the exclusive OR circuit 827 of the generation unit 82 in the signal waveform change mode information is in the high level state “1”. The position of the extreme value may be detected on the assumption that the D flip-flop 823 is read by CLK. Therefore, the output signals from the exclusive OR circuits 816 and 827 in the generator 82 in the above-mentioned signal waveform change mode information are (MN) bit signal generator 6 which will be described later.
Can be used as position information of the extreme value of the signal waveform required for the signal processing in the above, and can also be used for the extreme value of the signal waveform required for the signal processing in the delay control signal generator 8 described later. It can also be used as position information.

Next, the clock signal CLKi sent from the AND circuit 814 of the signal waveform change information generating section 81.
(Where i is 1, 2, 3, 4 ...) is the data terminal of the D-type flip-flop 839 in the D-type flip-flops 839 to 841 of the generator 83 of the interval information of the signal waveform change supplied to the clock terminal. Is supplied with the address value output from the address counter 838 performing the counting operation with the clock signal pulse Pfs having the sampling period as the counted pulse. Then, the D-type flip-flop 839 of the signal waveform change interval information generating unit 83 generates the clock signal CLKi (where i is 1, 2, 3, 4 ...) At each time when the clock signal CLKi is supplied to the clock terminal. The output value (address value) of the address counter 838 will be read.

The address value read into the D-type flip-flop 839 is used as the signal waveform change information generating section 81.
Of the D-type flip-flops 839 to 841 each time the sequential clock signals CLKi (where i is 1, 2, 3, 4 ...) Sent from the AND circuit 814 of the D-type flip-flops are supplied to the clock terminals of the D-type flip-flops 839 to 841. 840, 84
It will be moved to 1. The address value output from each of the D-type flip-flops 839 to 841 is
The address value output from the D-type flip-flop 839 and the address value output from the D-type flip-flop 840 are supplied to the subtractor 842 while being sent to the individual output terminals 14, 17, and 18, respectively. ,
The address value output from the D-type flip-flop 840 and the address value output from the D-type flip-flop 841 are supplied to the subtractor 843.

The output values N1 and N2 from the subtractors 842 and 843 are clock signals CLK adjacent to each other on the time axis.
As described above, the address counter 838 performs the counting operation using the clock signal pulse Pfs having the sampling period as the counted pulse, so that the subtractor 842 described above is used. The numerical values of the output values N1 and N2 from the 843 are numerical values showing how many times the interval between the adjacent clock signals CLK on the time axis is the sampling period Ts. The subtractor 84 described above
The output values N1 and N2 from 2,843 are sent to the output terminals 15 and 23, respectively, and are also supplied to the comparator 544. The comparator 544 compares the output values N1 and N2 from the two subtractors 842 and 843, and determines the smaller numerical value Ns of the two numerical values N1 and N2.
(When N1 and N2 are the same, N1 is set to Ns) is sent to the output terminal 16. The address value output from each of the D-type flip-flops 839 to 841 of the signal waveform change interval generation unit 83, the output value Ns from the comparator 544, the output values from the subtractors 842 and 843, etc. Can be used as interval information of a signal waveform change required for signal processing in the (M−N) -bit signal generator 9 described later, and can be used as a signal in the delay control signal generator 8 described later. It can also be used as interval information for waveform changes.

Next, the (MN) bit signal generator 9 shown in FIG. 3 will be described. (M-N) bit signal generator 9
Indicates that if the value of the N-bit code information that is the target of signal processing changes in a sequentially increasing trend or a decreasing trend on the time axis, it changes for each successive sampling cycle. When the length of a period (section) (indicated by the number of sampling periods Ts) in which the value of the N-bit code information continues is different between two adjacent sections, the adjacent 2 The midpoint of the shorter section of the two sections is connected to the point at the position corresponding to 1/2 of the shorter section of the boundary of the two sections in the section of the longer section. When (M−N) -bit additional code information that can represent a straight line is generated, and when the two adjacent sections have the same period length, the midpoint between the sections of the two sections is (MN) bit additional code information that can represent a connecting straight line Further, when the value of the N-bit code information is generated and is the N-bit code information in the section corresponding to the extreme value, it is predetermined in correspondence with the period length of the section. The (MN) bit additional code information can be read from the waveform data generating ROM, and the operation of supplying the (MN) bit additional code information generated as described above to the variable delay unit 10 can be performed. Is configured.

In FIG. 3, reference numeral 91 denotes a waveform data generator for the extreme value section, and the waveform data generator 91 for the extreme value section.
As described above with reference to FIG. 7B and FIGS. 8 to 10, the period length of the section corresponding to the extreme value based on the N-bit code information that is the target of the signal processing. Accordingly, the area is approximately the same as the area of the rectangle indicated by the extreme value section based on the N-bit code information (M
-N) A waveform data generation ROM in which bit code information is stored is provided. Further, reference numeral 92 designates a value of 1LSB in the N-bit code information to be subjected to the signal processing as a dividend, and the generator 8 of the interval information of the signal waveform change.
Numerical value Ns sent from the comparator 844 in FIG. 3 via the output terminal 16, that is, the shorter period length of the lengths of two adjacent sections (when the period lengths of two adjacent sections are the same. Is a “calculation unit for generating a value for performing an N-bit 1LSB / Ns operation” that performs an operation in which a numerical value Ns representing the sampling period Ts as a unit is used as a divisor.

Reference numeral 93 indicates a tendency that the value of the N-bit code information targeted for signal processing increases sequentially on the time axis,
Alternatively, when the values are sequentially decreasing and changing, the length of a period (section) in which the value of the N-bit code information for each successive sampling cycle is the same is two adjacent sections. 7 are different from each other, or the same, and when the two adjacent sections do not include an extreme value section, the two sections are already described with reference to FIG. This is a “waveform data generation unit other than the extreme value section” for generating (MN) bit additional code information by applying such a method, and 94 is, for example, a random access memory (RAM) or a read only memory ( ROM),
The control circuit includes a microprocessor and the like. Further, 95 is an inverter, 96 and 97 are selectors, and 98 is an OR circuit.

The signals output from the output terminals 14 to 23 of the detecting section 8 in the above-described signal waveform change mode are supplied to the input terminals 24 to 33 of the (MN) bit signal generating section 9. However, the connection relationship between each of the input terminals 24 to 33 in the (M−N) -bit signal generator 9 and the output terminals 14 to 23 of the signal waveform change detecting unit 8 is the same as that of the output terminal 14 respectively. → input terminal 30, output terminal 15 → input terminal 24, output terminal 16 → input terminal 26, output terminal 17 → input terminal 31, output terminal 18 → input terminal 3
2, output terminal 19 → input terminal 33, output terminal 20 → input terminal 25, output terminal 21 → input terminal 28, output terminal 22
→ Input terminal 27, output terminal 23 → input terminal 29.

The waveform data generator 91 in the extreme value section operating under the control of the control circuit 94, N bits of 1 LSB /
In the calculation unit 92 that generates a value for performing the calculation of Ns and the waveform data generation unit 93 other than the extreme value section, the waveform data generation unit 91 in the extreme value section described above changes the signal waveform with respect to the input terminal 24. Numerical value N1 supplied from the output terminal 15 of the detection unit 8 (output value N1 of the subtractor 842) and the extreme value section supplied from the output terminal 20 of the detection unit 8 of the signal waveform change mode with respect to the input terminal 25. And a signal indicating that the above-mentioned numerical value N1 is used as address information to read additional code information of (M-N) bits predetermined from the waveform data generation ROM in correspondence with the period length of the extreme value section. From the waveform data generator 91 in the extreme value section to the selector 96.

That is, when the signal indicating the extreme value section supplied from the output terminal 20 of the detecting section 8 of the variation of the signal waveform to the input terminal 25 is "1", the input terminal 24 The numerical value N1 given to the above indicates the period length of the extreme value section (how many times the sampling period Ts is multiplied) (see (b) of FIG. 11).
If is used as the address information, the waveform of the extreme value section in which the waveform data of a predetermined extreme value section (a part of which is illustrated in FIGS. 8 to 10) is stored in advance for each period length of the extreme value section. From the data generating ROM, additional (MN) -bit additional code information corresponding to the period length of the extreme value section (the extreme value section is shown in FIG.
It corresponds to the input data as exemplified in (b) of 1 (M
The -N) bit additional code information can be output as output data having a waveform as illustrated in FIG. 11C. Then, in the extreme value section, since the signal “1” indicating the extreme value section is supplied to the selector 96 via the input terminal 25, it is output from the waveform data generating section 91 in the extreme value section. The (MN) bit additional code information is sent to the output terminal 35 via the selector 96 and the OR circuit 98.

Next, an arithmetic unit 92 for generating a value for performing an arithmetic operation of 1 LSB / Ns of N bits, with respect to the input terminal 26, a numerical value Ns (supplied from the output terminal 16 of the detecting unit 8 of the change mode of the signal waveform). Using the output value Ns) of the comparator 844, an N-bit 1LSB / Ns operation is performed, and the operation result is supplied to the waveform data generation unit 93 other than the extreme value section and an N-bit 1LSB / Ns operation is performed. The above-mentioned numerical value Ns is also supplied to the waveform data generating section 93 other than the extreme value section from the calculating section 92 for generating a value for performing. The input terminal 2 is connected to the waveform data generator 93 other than the extreme value section.
7, the output terminal 2 of the detection unit 8 of the variation of the signal waveform
A> B signal supplied from 2 (if the value of N-bit code information has a tendency to sequentially increase on the time axis, “1”,
When the value of the N-bit code information has a decreasing tendency on the time axis, it is a signal of “0”, and in FIGS. 4 and 5, “>”, “U”, “<”, and “D” are used. Is supplied, and the waveform data generating section 93 other than the extreme value section has a tendency that the value of the N-bit code information sequentially increases on the time axis due to the A> B signal, or The mode of waveform data generation is changed by sequentially judging whether there is a decreasing tendency.

FIG. 12 shows a case where the A> B signal of “1” is supplied to the waveform data generating section 93 other than the extreme value section, that is, the value of the N-bit code information is on the time axis. FIG. 9 is a diagram illustrating a method of generating waveform data in the waveform data generation unit 93 other than the extreme value section, taking as an example a case where the waveform data sequentially increases in FIG. FIG. 12 (a)
, The section whose signal level is "K" has a period length of N1, and the section adjacent to the above section has a signal level of "Y".
The section has a period length of N2, and the relationship between the period lengths N1 and N2 of the two adjacent sections is N1> N2. In this case, the numerical value Ns supplied from the comparator 844 to the input terminal 26 via the output terminal 16 of the signal waveform change detecting section 8 is N2. The numerical value Ns (= N2) illustrated in FIG. 12 is 16 (the clock signal pulse Pfs generated at every sampling period Ts is 16).
Individual).

Further, the boundary position β between the section "K" and the section "Y" in FIG. 12 is supplied to the input terminal 31 through the output terminal 17 of the signal waveform change detecting section 8. The terminal position γ of the section “Y” is indicated by the address value supplied to the input terminal 30 through the output terminal 14 of the signal waveform change detecting section 8. Further, the starting end position α of the section “K” is indicated by the address value supplied to the input terminal 32 via the output terminal 18 of the detecting section 8 of the change mode of the signal waveform. Waveform data generator 9 other than the extreme value section
3 is provided with a memory, an arithmetic circuit, etc., and from the boundary position β between the two adjacent sections “YA” and “KU”,
Position 0 of Ns / 2 in section "ku" and N in section "ya"
Additional code information having a value as shown in the following formula for each position of 0, 1, 2, 3, ... 16 set for each sampling cycle between the position 16 of s / 2 and Generate.

First, it is assumed that the value of the additional code information at the position of 0 set in the section "K" is 0. Next, the value of the additional code information at the position of 1 set in the section "K" is (N-bit 1 LSB) / Ns (= N2). The value of the additional code information at the position 2 set in the section “K” is 2 × (1 LSB of N bits) / Ns (= N2), and the additional code information at the position 3 set in the section “K” Is 3 × (1 LSB of N bits) / Ns (= N2), and the value of the additional code information at the position of 4 set in the section “K” is 4 × (1 LSB of N bits) / Ns (= N2 ), The value of the additional code information at the 5th position set in the section “K” is 5 × (1 LSB of N bits) / Ns (= N2), and the addition at the 6th position set in the section “K” The value of the code information is 6 × (1 LSB of N bits) / Ns (= N 2), and the value of the additional code information at the 7th position set in the section “K” is 7 × (1 LSB of N bits) / Ns ( = N2).

Next, the value of the additional code information at the boundary position β (position of 8) between the section "K" and the section "YA" in FIG. 12 is [{8 × (1 LSB of N bits) / Ns ( = N2)}
-N bits of 1 LSB]. Hereinafter, the value of the additional code information at the position 9 set in the section “YA” is [{9
× (N-bit 1 LSB) / Ns (= N 2)}-N-bit 1 LSB], the value of the additional code information at the 10 positions set in the section “YA” is [{10 × (N-bit 1 LSB]
SB) / Ns (= N2)}-N bits of 1 LSB], and the value of the additional code information at the 11 positions set in the section “YA” is [{11 × (1 LSB of N bits) / Ns (= N
2)}-N-bit 1 LSB], the value of the additional code information at the 12 positions set in the section “YA” is [{12 ×
(N-bit 1 LSB) / Ns (= N2)}-N-bit 1 LSB], the value of the additional code information at the 13 positions set in the section “YA” is [{13 × (N-bit 1 LSB]
B) / Ns (= N2)}-N bits of 1 LSB], the value of the additional code information at 14 positions set in the section "YA" is [{14 × (1 LSB of N bits) / Ns (= N
2)}-N-bit 1 LSB], and the value of the additional code information at the 15 positions set in the section “YA” is [{15 ×
(N-bit 1 LSB) / Ns (= N2)}-N-bit 1 LSB], the value of the additional code information at the 16 positions set in the section “YA” is [{16 × (N-bit 1 LSB]
B) / Ns (= N2)}-N bits of 1 LSB].

By performing the above-described calculation, the signal waveform based on the original N-bit code information in the two adjacent sections "ku" and "ya" has a waveform of K1 → K2 → K3 → K4.
→ K5 → K6 → K7 → K8, but the above-mentioned operation is performed to add (MN) bit additional code information to the least significant digit of the original N-bit digital signal. By continuing, K1 → K2 → K3 → K5 → K7
→ The signal waveform as indicated by K8, that is, the waveform between the position of δ and the position of ε in FIG. As shown in FIG. 12B.

The description given so far with reference to FIG. 12 has been made in the case where the waveform data generating section 93 other than the extreme value section is supplied with the signal of A> B signal of "1", that is, As for the case where the value of the N-bit code information has a tendency to sequentially increase on the time axis, a signal of which A> B signal is “0” is supplied to the waveform data generator 93 other than the extreme value section. In the case of the state of being maintained, that is, in the case where the value of the N-bit code information tends to decrease sequentially on the time axis, the above formula is simply changed (M−N).
It goes without saying that the generation of the bit additional code information can be performed in the same manner as described above. Considering a case where the signal level in the section “K” shown in FIG. 12A is higher by 1 LSB of N bits than that in the section “Y”,
From the boundary position β between two adjacent sections “YA” and “KU”, 1 between the position 0 of Ns / 2 in the section “KU” and the position 16 of Ns / 2 in the section “YA”. The additional code information to be generated for each position of 0, 1, 2, 3, ... 16 set for each sampling period is as follows.

First, the value of the additional code information at the position of 0 set in the section “K” is [{16 × (N-bit 1
LSB) / Ns (= N2)}-N-bit 1 LSB]. In addition, 1 set in "ku"
The value of the additional code information at the position of is [{15 × (1 LSB of N bits) / Ns (= N2)} − 1 LS of N bits
B], and hereinafter, the value of the additional code information at the position of 2 set in the section “K” is [{14 × (1 LS of N bits
B) / Ns (= N2)}-N bits of 1 LSB], the value of the additional code information at the position of 3 set in the section "K" is [{13 × (1 LSB of N bits) / Ns (= N
2)}-N-bit 1 LSB], and the value of the additional code information at the position of 4 set in the section “K” is [{12 × (N
Bit 1LSB) / Ns (= N2)}-N bit 1L
SB], the value of the additional code information at the position of 5 set in the section “K” is [{11 × (1 LSB of N bits) /
Ns (= N2)}-N-bit 1LSB], the value of the additional code information at the 6th position set in the section "K" is [{10 × (N-bit 1LSB) / Ns (= N2)}-
N bits of 1 LSB], the value of the additional code information at the 7th position set in the section “K” is [{9 × (N bits of 1 LSB) / Ns (= N2)} − N bits of 1 LSB], In addition, the value of the additional code information at the boundary position β (position of 8) between the section “KU” and the section “YA” in FIG. 12 is [{8 × (1 LSB of N bits) / Ns (= N2)}. -N
1LSB of bit].

Next, the value of the additional code information at the 9th position set in the section "YA" is 7 × (1 LS of N bits).
B) / Ns (= N 2), the value of the additional code information at the 10 positions set in the section “YA” is 6 × (1 of N bits).
LSB) / Ns (= N2), 1 set in the section "YA"
The value of the additional code information at the position 1 is 5 × (1 LSB of N bits) / Ns (= N 2), and the value of the additional code information at the 12 positions set in the section “YA” is 4 × (N 1LSB of bits) / Ns (= N2), the value of the additional code information at the 13 positions set in the section "YA" is 3 ×
(1 LSB of N bits) / Ns (= N2), the value of the additional code information at the 14 positions set in the section "YA" is:
2 × (N-bit 1 LSB) / Ns (= N 2), the value of the additional code information at the 15 positions set in the section “YA” is (N-bit 1 LSB) / Ns (= N 2), section “ The value of the additional code information at the 16 positions set in “Y” is 0.

Waveform data generator 9 other than the above-mentioned extreme value section
3, the additional code information of the (M−N) bits read from the memory under the control operation of the control circuit 94 is stored in the memory after the additional code information obtained by performing the above operation is sequentially stored in the memory. It is given to the selector 97. Input terminal 2 described above
5, the output terminal 2 of the detection unit 8 of the variation of the signal waveform
When the signal supplied from 0 indicating the extreme value section is “0”, the signal is given to the selector 97 as the signal of “1” by the inverter 95, so that the waveform data other than the extreme value section is obtained. The (MN) -bit additional code information generated by the generator 93 is the selector 9 described above.
7 and the OR circuit 98, the signal is sent to the output terminal 35 of the (MN) bit signal generator 9.

As described above, the value of the N-bit code information which is the object of signal processing changes in a sequential increasing trend or a progressive decreasing trend on the time axis.
When the length of a period (section) in which the value of the N-bit code information for each successive sampling cycle is the same is different between two adjacent sections, or when they are the same, and the above-mentioned adjacent When the two sections do not include the extreme value section, the waveform data generating unit 93 other than the extreme value section uses the method described above with reference to FIG. (M−N) -bit additional code information is applied to generate the additional code information, and the period corresponding to the extreme value according to the N-bit code information targeted for signal processing is the period length of the extreme value interval. The additional code information of (M−N) bits having a predetermined waveform corresponding to is generated by the waveform data generating unit 91 in the extreme value section, but the adjacent 2
When one of the two sections is the extreme value section, the control signal generated by the control circuit 94 is based on the information indicating the extreme value section supplied to the control circuit 94 through the input terminal 25. By being applied to the waveform data generating section 93 other than the extreme value section, the waveform data generating section 93 other than the extreme value section prevents the selector 97 from being provided with the calculation results for the two sections including the extreme value section.

The (M-N) -bit additional code information generated by the (M-N) -bit signal generator 9 as described above is supplied to the adder circuit 7 through the variable delay unit 10. In the variable delay unit 10 of, the least significant digit of the N-bit code information in the state where the delay circuit 6 has received a certain time delay,
The (M-N) -bit additional code information is added in a continuous state by the adder circuit 7 to provide a necessary time delay of (M-N) bits so that the entire code information becomes M-bit code information. Is added to the additional code information. Variable delay unit 10 described above
As for the above, it is possible to give a predetermined time delay to the additional code information of (M−N) bits by controlling the write timing and the read timing using the random access memory. The predetermined delay amount given to the (MN) -bit additional code information in the variable delay unit 10 is determined by the delay control signal generated by the delay control signal generation unit 11.

In FIG. 13, N-bit code information supplied to the input terminal 1 (indicated by the input waveform S at the left end of FIG. 13).
On the other hand, N-bit code information in a state in which a certain time delay is given by the delay circuit 3 (waveform S in the upper part near the center of FIG.
based on the N-bit code information (indicated by the input waveform S at the left end of FIG. 13) supplied to the input terminal 1 described above, and −
(M-) generated by the (N) bit signal generator 9
The signal obtained by delaying the N) -bit additional code information by the variable delay unit 10 for a predetermined time (shown by the waveform Sa in the lower part near the center of FIG. 13) is added by the adding circuit 7, As shown as an output at the right end of the above, the (M−N) -bit additional code information is continuously added to the least significant digit of the N-bit code information by the adder circuit 7, and the whole is M. The state in which the bit code information is used is illustrated and described. The symbols a to h shown in the waveforms in FIG. 13 are for clarifying the correspondence between the waveforms. In addition,
Floor waveform Sa 'shown by a dotted line in the lower part near the center of FIG.
As described above with reference to FIG. 12, when obtaining the value of the additional code information to be generated corresponding to the inside of one section from the position of the boundary between two adjacent sections, 1L of N bits is used.
The calculated value of Sa before subtracting the value of SB is shown.

That is, in the adder circuit 7, the N-bit code information and the (M−N) -bit additional code information are added in a proper time relationship, and the M-bit code information output from the adder circuit 7 is added. However, in order to obtain the waveform as illustrated in the right end of FIG. 13, in the N-bit code information supplied to the input terminal 1 (shown by the input waveform S at the left end of FIG. 13), With respect to the time position of the additional code information for each successive sampling cycle in the N-bit code information (indicated by the waveform Sd in the upper part near the center of FIG. 13) in the state where a certain time delay is given by the delay circuit 6. And the input terminal 1 described above.
Generated by the detection unit 8 of the change mode of the signal waveform and the (M−N) -bit signal generation unit 9 based on the N-bit code information (shown by the input waveform S at the left end of FIG. 13) supplied to The additional code for each successive sampling cycle in the signal obtained by delaying the (MN) bit additional code information by the variable delay unit 10 for a predetermined time (shown by the waveform Sa in the lower part near the center of FIG. 13). The variable delay unit 10 is provided so that the time position of the information is correctly supplied to the adder circuit 7.
It is necessary that the delay time given to the (M−N) -bit additional code information is controlled by the delay control signal generated by the delay control signal generator 11. This point is the same for the additional code information of (M−N) bits generated corresponding to the extreme value section (see FIG. 11).

Therefore, in the delay control signal generator 11, among the signals output from the output terminals 14 to 23 of the signal waveform change detecting section 8, the clock signal CLK output from the output terminal 21 and the output terminal 16, the value of Ns sent from the output terminal 16, the address value of the boundary position between the two sections sent from the output terminal 17, the information on the period length of the extreme value section sent from the output terminal 15, the pole sent from the output terminal 20. Using the information indicating the value section, the address value of the starting point position of the section sent from the terminal 18, the clock signal Pfs, etc., the sampling cycle Ts is calculated from the position of the boundary between two adjacent sections or the starting point of the extreme value section. Exist at positions separated from each other (MN)
Calculate the delay time to be given to the bit additional code information,
The variable delay unit 10 generates a delay control signal whose delay time is given to the (MN) bit additional code information, and supplies it to the variable delay unit 10.

The M-bit digital signal output from the adder circuit 7 in the bit number converting section 3 is an analog signal restored corresponding to the N-bit digital signal, and the N-bit digital signal is obtained. Of the analog signal waveform corresponding to the aforementioned N-bit digital signal within an error range of ± 0.5 LSB for a resolution 1 LSB of 1 / N of 2 existing between the analog signal used for The digital signal is in a state in which the number of bits is converted such that the integrated value and the integrated value of the analog signal waveform corresponding to the M-bit digital signal having a relation of M> N are equivalent. The M-bit digital signal of is supplied to the frequency spectrum analysis unit 4, and the frequency spectrum analysis is performed in the frequency spectrum analysis unit 4.

The frequency spectrum analyzer 4 described above is
For example, any one of those configured to perform frequency spectrum analysis by Fast Fourier Transform (FFT), one configured using a large number of digital band pass filters, or one configured in other ways is used. it can. The frequency spectrum analysis unit 4 performs a frequency spectrum analysis operation on the M-bit digital signal supplied from the bit number conversion unit 3 and outputs the analysis result as output data of the dynamic range of the N-bit digital signal. It is given to the terminal 2 and the display unit 5. In the frequency spectrum analyzer of the present invention, the N-bit digital signal that is the target of the frequency spectrum analysis is converted into the M-bit digital signal having the relation of M> N by the number of bits, and the M-bit Since the frequency spectrum analysis is performed on the digital signal, when the frequency spectrum analysis on the N-bit digital signal is performed on the N-bit digital signal, it is determined that the least significant digit signal in the N-bit digital signal is obtained. A corresponding digital signal of a minute signal level is also subjected to frequency spectrum analysis as a smooth waveform with a resolution of 2 (M−N) power when performing frequency spectrum analysis on an M-bit digital signal.
As described above, when the frequency spectrum analysis of the N-bit digital signal is performed on the N-bit digital signal, a digital signal having a minute signal level corresponding to the least significant digit signal in the N-bit digital signal is obtained. Correspondingly, many harmonic components (see (b) of FIG. 14) appearing in the frequency spectrum analysis result can be prevented from appearing in the frequency spectrum analysis result as in (a) of FIG.

In the implementation of the frequency spectrum analyzer of the present invention, an N-bit digital signal to be subjected to frequency spectrum analysis is converted into M, which has a relation of M> N.
As a means for converting the bit number into a bit digital signal, a difference between N bit digital signals which are separated from each other by one adjacent sampling period is selected for the N bit digital signal subjected to the bit number conversion. On the basis of the result of detecting the information of the change mode, the additional code information of (M−N) bits set so as to correspond to the predetermined analog signal waveform is generated to convert the N-bit digital signal to M. The number of bits is not limited to the above-described means for converting the number of bits of an M-bit digital signal having a relationship of> N. For example, an N-bit digital signal to be subjected to the number of bits conversion. The smoothing process according to the change mode of the difference between the N-bit digital signals which are separated by one adjacent sampling period in sequence, and correspond to the analog signal waveform. A means for generating additional code information of (M−N) bits set so that the N-bit digital signal is converted into an M-bit digital signal having a relation of M> N by the number of bits is used. May be.

[0074]

As is apparent from the above detailed description, the frequency spectrum analyzing apparatus of the present invention provides the analog signal used to obtain the N-bit digital signal and the N-bit digital signal. A resolution of 1 / N to the power of 2 existing between the restored analog signal and 1L
An analog signal waveform corresponding to an M-bit digital signal having a relation of M> N with an integral value of the analog signal waveform represented by the N-bit digital signal described above within an error range of ± 0.5 LSB with respect to SB. So that they are equivalent to the integrated value of N-bit digital signals that are subject to bit number conversion
The (M−N) -bit additional code information set so as to correspond to the analog signal waveform is detected based on the result of detecting the information of the change state of the difference between the N-bit digital signals separated by the sampling period. The N-bit digital signal is continuously connected to the least significant digit to convert the number of bits into the M-bit digital signal, and the FFT or digital band pass filter group is applied to the M-bit digital signal having the above M> N relationship. The frequency spectrum is analyzed by the method, and the analysis result is taken out in the dynamic range of the N-bit digital signal. In the frequency spectrum analyzer of the present invention, the N-bit digital signal to be subjected to the frequency spectrum analysis is obtained. As a signal obtained by converting the number of bits into an M-bit digital signal having a relation of M> N, Since the frequency spectrum analysis is performed on the N.sup.th digital signal, conventionally, when the frequency spectrum analysis of the N-bit digital signal is performed on the N-bit digital signal, as described above, Although many harmonic components were shown in the analysis result of the frequency spectrum due to the digital signal of the minute signal level corresponding to the signal of the least significant digit, the lowest frequency in the frequency spectrum analysis for the N-bit digital signal described above. A digital signal having a minute signal level corresponding to a digit signal is also subjected to frequency spectrum analysis as a smooth waveform with a resolution of 2 (M−N) when the frequency spectrum of the M-bit digital signal according to the present invention is analyzed. As described above, N
When the frequency spectrum analysis of the bit digital signal is performed on the N bit digital signal, it is generated corresponding to the digital signal of the minute signal level corresponding to the signal of the least significant digit in the N bit digital signal. Since many harmonic components can be prevented from appearing in the analysis result of the frequency spectrum, the present invention can satisfactorily solve the above-mentioned problems.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a frequency spectrum analyzer of the present invention.

FIG. 2 is a block diagram showing a partial specific configuration example of the components of the frequency spectrum analyzer of the present invention.

FIG. 3 is a block diagram showing a partial specific configuration example of the components of the frequency spectrum analyzer of the present invention.

FIG. 4 is a diagram for explaining the operation of the apparatus.

FIG. 5 is a diagram for explaining the operation of the apparatus.

FIG. 6 is a diagram for explaining the operation of the apparatus.

FIG. 7 is a diagram for explaining the operation of the apparatus.

FIG. 8 is a diagram for explaining the operation of the apparatus.

FIG. 9 is a diagram for explaining the operation of the apparatus.

FIG. 10 is a diagram for explaining the operation of the apparatus.

FIG. 11 is a diagram for explaining the operation of the apparatus.

FIG. 12 is a diagram for explaining the operation of the apparatus.

FIG. 13 is a diagram for explaining the operation of the apparatus.

FIG. 14 is a diagram illustrating an output state of the frequency spectrum analyzer.

[Explanation of symbols]

1 ... N-bit digital signal input terminal obtained by converting an analog signal into a digital signal with a resolution of 1 / N. 2 ... N-bit dynamic range output data output from a frequency spectrum analyzer Output terminals, 3
... Bit number converter, 4 ... Frequency spectrum analyzer, 5 ...
A display unit of output data of N-bit dynamic range output from the frequency spectrum analyzer, 6 ... Delay circuit, 7 ... Adder circuit, 8 ... Signal waveform conversion mode detection unit,
9 ... (MN) bit signal generator, 10 ... Variable delay unit,
11 ... Delay control signal generator,

Claims (2)

[Claims] 1. A frequency spectrum analyzer for analyzing an N-bit digital signal obtained by converting an analog signal into a digital signal with a resolution of 1 / N of 2 and analyzing the N-bit digital signal into a frequency spectrum. ± 1 for resolution 1LSB of 1 / N of 2 existing between the analog signal restored corresponding to the digital signal and the analog signal used to obtain the N-bit digital signal.
Within the error range of 0.5 LSB, the integrated value of the analog signal waveform corresponding to the above-mentioned N-bit digital signal and the analog signal waveform corresponding to the M-bit digital signal having a relation of M> N A bit number conversion unit that performs bit number conversion such that the integrated value becomes equivalent, a frequency spectrum analysis unit that analyzes the M-bit digital signal output from the bit number conversion unit into a frequency spectrum, and A frequency spectrum analyzer comprising means for setting a dynamic range of an output signal from the frequency spectrum analyzer to a dynamic range of an N-bit digital signal. 2. A frequency spectrum analyzer for analyzing an N-bit digital signal obtained by converting an analog signal into a digital signal with a resolution of 1 / N of 2 and converting the analog signal into 2 An N-bit digital signal obtained by converting it into a digital signal with a resolution of 1 / N is restored to the analog signal used to obtain the N-bit digital signal and the N-bit digital signal. The integral of the analog signal waveform corresponding to the above-mentioned N-bit digital signal is within the error range of ± 0.5 LSB for the resolution 1 LSB of 1 / N of 2 existing between the analog signal obtained by M that has a relation of M> N with the value
The bit number conversion is performed so that the integrated value of the analog signal waveform corresponding to the bit digital signal becomes equivalent, and the N-bit digital signal that is the target of the bit number conversion is sequentially adjacent. Information of the change mode of the difference between the N-bit digital signals separated by one sampling period is detected, and the N-bit digital signals separated by the successive adjacent one sampling period in the N-bit digital signal are detected. Depending on the change mode of the difference between the signals, (MN) bit additional code information set so as to correspond to the analog signal waveform is generated, and this is used as the least significant digit of the N-bit digital signal. A bit number conversion unit for converting the bit number by continuously generating the (M−N) -bit additional code information and generating an M-bit digital signal, and the bit number conversion unit described above. A frequency spectrum analysis unit for analyzing the M-bit digital signal output from the frequency spectrum analysis unit, and means for setting the dynamic range of the output signal from the frequency spectrum analysis unit to the dynamic range of the N-bit digital signal. Frequency spectrum analyzer.